Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.

The remaining ones are more complicated and may require adjustments in other
parts of the simulator.

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index d0aa13d38604f20e84b46c29cb2bdf3436ae0025..ce0c92213c5dd2187a63854b6eda9e21aca7b46e 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -203,21 +203,13 @@ decode OPCODE default Unknown::unknown() {
                 31: decode IMM {
                     1: decode INTIMM {
                         // return EV5 for FULL_SYSTEM and EV6 otherwise
-                        1: implver({{
-#if FULL_SYSTEM
-                             Rc = 1;
-#else
-                             Rc = 2;
-#endif
-                        }});
+                        1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
                     }
                 }
             }
 
-#if FULL_SYSTEM
             // The mysterious 11.25...
             0x25: WarnUnimpl::eleven25();
-#endif
         }
 
         0x12: decode INTFUNC {
@@ -784,15 +776,11 @@ decode OPCODE default Unknown::unknown() {
 
         format BasicOperate {
             0xc000: rpcc({{
-#if FULL_SYSTEM
-        /* Rb is a fake dependency so here is a fun way to get
-         * the parser to understand that.
-         */
-                Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
-
-#else
-                Ra = curTick();
-#endif
+                /* Rb is a fake dependency so here is a fun way to get
+                 * the parser to understand that.
+                 */
+                uint64_t unused_var M5_VAR_USED = Rb;
+                Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
             }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
@@ -817,23 +805,20 @@ decode OPCODE default Unknown::unknown() {
             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
         }
 
-#if FULL_SYSTEM
-        format BasicOperate {
-            0xe000: rc({{
+        0xe000: decode FULL_SYSTEM {
+            0: FailUnimpl::rc_se();
+            default: BasicOperate::rc({{
                 Ra = IntrFlag;
                 IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
-            0xf000: rs({{
+        }
+        0xf000: decode FULL_SYSTEM {
+            0: FailUnimpl::rs_se();
+            default: BasicOperate::rs({{
                 Ra = IntrFlag;
                 IntrFlag = 1;
             }}, IsNonSpeculative, IsUnverifiable);
         }
-#else
-        format FailUnimpl {
-            0xe000: rc();
-            0xf000: rs();
-        }
-#endif
     }
 
 #if FULL_SYSTEM

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index b1d01724d427cf85ad49bde5629dd8b738df8815..e3a6b18ab424720ef0929cf8621e7a825f84065a 100644 (file)
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -42,21 +42,14 @@ output exec {{
     /// instruction in full-system mode.
     /// @retval Full-system mode: NoFault if FP is enabled, FenFault
     /// if not.  Non-full-system mode: always returns NoFault.
-#if FULL_SYSTEM
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;  // dummy... this ipr access should not fault
-        if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+        if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
     }
-#else
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
-    {
-        return NoFault;
-    }
-#endif
 }};
 
 output header {{