add comment on SUBVL in setpc

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 4a0cb4284e8e56f07fde44516f154bb038a1d3c0..cf70568171f9acdfc0e70774c390aaf65a571f56 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -317,6 +317,20 @@ uint64_t sv_insn_t::rd_bitset(reg_t reg, int bit, bool set)
     return val;
 }
 
+/* called by the instruction: in scalar mode it performs the branch.
+   in SV mode, the fact that the bxx.h even tried to call setpc is
+   taken to mean that the compare succeeded, and save_branch_rd is
+   used instead to accumulate that information [or the target_reg
+   used instead, and copied into save_branch_rd]
+
+   at the **END** of the vector loop (back in insn_template_sv.cc)
+   the *accumulated* results in save_branch_rd are tested to see
+   if they *all* succeeded, and if so *then* the branch is taken.
+
+   TODO: the loop has to be modified to be aware of SUBVL, because
+   only if *all* subvector elements succeed is the save_branch_rd
+   bit allowed to be set.
+*/
 void sv_insn_t::setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
                       reg_t *target_reg, bool zeroing, bool inv)
 {