Packed SigBit::data and SigBit::offset in a union

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 0122531447a3276a9d00807d22f429898d757146..79ddd2e02594ed2744b8783497a03cb5656ed2da 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1681,9 +1681,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
 {
        wire = bit.wire;
+       offset = 0;
        if (wire == NULL)
                data = RTLIL::Const(bit.data);
-       offset = bit.offset;
+       else
+               offset = bit.offset;
        width = 1;
 }
 

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 796d45df1a88a721922a7052c0565deb0e5ec47f..43c7e1050ed75d2844089b76598711c98950dd54 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -707,15 +707,17 @@ struct RTLIL::SigChunk
 struct RTLIL::SigBit
 {
        RTLIL::Wire *wire;
-       RTLIL::State data;
-       int offset;
-
-       SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
-       SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
-       SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); }
-       SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); }
-       SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); }
-       SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
+       union {
+               RTLIL::State data;
+               int offset;
+       };
+
+       SigBit() : wire(NULL), data(RTLIL::State::S0) { }
+       SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
+       SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
+       SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
+       SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); }
+       SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
        SigBit(const RTLIL::SigSpec &sig);
 
        bool operator <(const RTLIL::SigBit &other) const {