Added RTLIL::Cell::has(portname)

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 4bc8710e95974df951d4dde86bdef12fc9576c00..653a9f22dce303961010c3d4173cb23a307ad54e 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
                        for (RTLIL::Wire *wire : ports) {
                                log_assert(wire != NULL);
                                RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
-                               if (cell->connections().count(wire->name) > 0) {
+                               if (cell->has(wire->name)) {
                                        sig = sigmap(cell->connections().at(wire->name));
                                        sig.extend(wire->width, false);
                                }

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6bef90e383bc101759eecfbbbedd4a401984c7d8..d9186c0435ac8d0db66b55e99f2e15a6a5496884 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -301,7 +301,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
 
 std::string cellname(RTLIL::Cell *cell)
 {
-       if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0)
+       if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q"))
        {
                RTLIL::SigSpec sig = cell->get("\\Q");
                if (SIZE(sig) != 1 || sig.is_fully_const())
@@ -908,7 +908,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
                for (auto &it : module->cells)
                {
                        RTLIL::Cell *cell = it.second;
-                       if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0)
+                       if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
                                continue;
 
                        RTLIL::SigSpec sig = cell->get("\\Q");

diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index 952dd6a3a3c4d45454169928861fd9cdc78a26a7..09437a0aa2bc0ab3db52086db2393cb73edb48fb 100644 (file)
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -202,7 +202,7 @@ cell_body:
                delete $5;
        } |
        cell_body TOK_CONNECT TOK_ID sigspec EOL {
-               if (current_cell->connections().count($3) != 0)
+               if (current_cell->has($3))
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
                current_cell->set($3, *$4);
                delete $4;

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 4050d2dcf929cd5c565f6c6984c8a6c06b1484c3..3a5c5347cfc732b509865c8b3966bf9dc5a486c3 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -87,21 +87,21 @@ struct ConstEval
        {
                RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-               assert(cell->connections().count("\\Y") > 0);
+               assert(cell->has("\\Y"));
                sig_y = values_map(assign_map(cell->get("\\Y")));
                if (sig_y.is_fully_const())
                        return true;
 
-               if (cell->connections().count("\\S") > 0) {
+               if (cell->has("\\S")) {
                        sig_s = cell->get("\\S");
                        if (!eval(sig_s, undef, cell))
                                return false;
                }
 
-               if (cell->connections().count("\\A") > 0)
+               if (cell->has("\\A"))
                        sig_a = cell->get("\\A");
 
-               if (cell->connections().count("\\B") > 0)
+               if (cell->has("\\B"))
                        sig_b = cell->get("\\B");
 
                if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ceb2b0f52c179339f67237b70e057ccb458b4bb9..059357d21dd8e9daf42cc19ebe3b4c7665eaee34 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -348,9 +348,9 @@ namespace {
 
                void port(const char *name, int width)
                {
-                       if (cell->connections().count(name) == 0)
+                       if (!cell->has(name))
                                error(__LINE__);
-                       if (cell->connections().at(name).size() != width)
+                       if (cell->get(name).size() != width)
                                error(__LINE__);
                        expected_ports.insert(name);
                }
@@ -379,9 +379,9 @@ namespace {
 
                        for (const char *p = ports; *p; p++) {
                                char portname[3] = { '\\', *p, 0 };
-                               if (cell->connections().count(portname) == 0)
+                               if (!cell->has(portname))
                                        error(__LINE__);
-                               if (cell->connections().at(portname).size() != 1)
+                               if (cell->get(portname).size() != 1)
                                        error(__LINE__);
                        }
 
@@ -1340,6 +1340,11 @@ RTLIL::Memory::Memory()
        size = 0;
 }
 
+bool RTLIL::Cell::has(RTLIL::IdString portname)
+{
+       return connections_.count(portname) != 0;
+}
+
 void RTLIL::Cell::unset(RTLIL::IdString portname)
 {
        connections_.erase(portname);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 25d0a8309c74f52cb3e87fa3e8fb3cc204b03c9a..73d3727cec294eb8abe6e2444bf25610785ab8b7 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -488,6 +488,7 @@ public:
        RTLIL_ATTRIBUTE_MEMBERS
 
        // access cell ports
+       bool has(RTLIL::IdString portname);
        void unset(RTLIL::IdString portname);
        void set(RTLIL::IdString portname, RTLIL::SigSpec signal);
        const RTLIL::SigSpec &get(RTLIL::IdString portname) const;

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 1401193fd4ccc6c2ad3a918f55a85437b059559e..f94ea639b43a7bfaffa9b292fece64fad5687a8b 100644 (file)
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -75,7 +75,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
                        continue;
                if (mod->get_bool_attribute("\\blackbox"))
                        continue;
-               if (it.second->connections().count(name) > 0)
+               if (it.second->has(name))
                        continue;
 
                it.second->set(name, wire);

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index be851afa668de700f315167e835dd0bb08fc7739..55fe336f423ba119955560120070673ce5b9804f 100644 (file)
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -80,7 +80,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
                        continue;
                if (cellport.second != "\\A" && cellport.second != "\\B")
                        return false;
-               if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0)
+               if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y"))
                        return false;
                for (auto &port_it : cell->connections())
                        if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")

diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index ed80d7c31550fb3342571d3aafa6b94fbf3088cd..186ea2fd4f3318d871c9b1b0842f5a88dc103a7b 100644 (file)
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -47,13 +47,13 @@ struct FsmExpand
                                return true;
 
                RTLIL::SigSpec new_signals;
-               if (cell->connections().count("\\A") > 0)
+               if (cell->has("\\A"))
                        new_signals.append(assign_map(cell->get("\\A")));
-               if (cell->connections().count("\\B") > 0)
+               if (cell->has("\\B"))
                        new_signals.append(assign_map(cell->get("\\B")));
-               if (cell->connections().count("\\S") > 0)
+               if (cell->has("\\S"))
                        new_signals.append(assign_map(cell->get("\\S")));
-               if (cell->connections().count("\\Y") > 0)
+               if (cell->has("\\Y"))
                        new_signals.append(assign_map(cell->get("\\Y")));
 
                new_signals.sort_and_unify();
@@ -65,7 +65,7 @@ struct FsmExpand
                if (new_signals.size() > 3)
                        return false;
 
-               if (cell->connections().count("\\Y") > 0) {
+               if (cell->has("\\Y")) {
                        new_signals.append(assign_map(cell->get("\\Y")));
                        new_signals.sort_and_unify();
                        new_signals.remove_const();
@@ -148,11 +148,11 @@ struct FsmExpand
                for (int i = 0; i < (1 << input_sig.size()); i++) {
                        RTLIL::Const in_val(i, input_sig.size());
                        RTLIL::SigSpec A, B, S;
-                       if (cell->connections().count("\\A") > 0)
+                       if (cell->has("\\A"))
                                A = assign_map(cell->get("\\A"));
-                       if (cell->connections().count("\\B") > 0)
+                       if (cell->has("\\B"))
                                B = assign_map(cell->get("\\B"));
-                       if (cell->connections().count("\\S") > 0)
+                       if (cell->has("\\S"))
                                S = assign_map(cell->get("\\S"));
                        A.replace(input_sig, RTLIL::SigSpec(in_val));
                        B.replace(input_sig, RTLIL::SigSpec(in_val));

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index e89bba89326010571a1321c32ac4732505181d51..ff3ac7608281140db17407ecedf2633888af5ecf 100644 (file)
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -350,7 +350,7 @@ struct FsmExtractPass : public Pass {
                                                assign_map.apply(sig);
                                                sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
                                        }
-                                       if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 &&
+                                       if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") &&
                                                        cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
                                                RTLIL::SigSpec sig = conn_it.second;
                                                assign_map.apply(sig);

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index e52882316b1883d3a35e5c26513a63c56e154042..000a9ec2b7121b0617d2209c6f32e1cccf7cc0c9 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -88,7 +88,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i
 
 static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
 {
-       std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A";
+       std::string b_name = cell->has("\\B") ? "\\B" : "\\A";
 
        bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
        bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
@@ -321,7 +321,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
                                cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
                {
                        RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-                       RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
+                       RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
 
                        if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
                                sig_a = RTLIL::SigSpec();

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index a84faf792a5e55865f81468ef310af733409f61b..198f834774324d0d087e80ec328de83774c5582a 100644 (file)
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -83,7 +83,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
        SigPool dffsignals;
 
        for (auto &it : module->cells) {
-               if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q"))
+               if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
                        dffsignals.add(sigmap(it.second->get("\\Q")));
        }
 
@@ -628,7 +628,7 @@ struct ExposePass : public Pass {
                                                        log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
                                                        RTLIL::SigSpec sig;
-                                                       if (cell->connections().count(p->name) != 0)
+                                                       if (cell->has(p->name))
                                                                sig = cell->connections().at(p->name);
                                                        sig.extend(w->width);
                                                        if (w->port_input)