*/
void squashFromTC(unsigned tid);
+#if FULL_SYSTEM
+ /** Posts an interrupt. */
+ void post_interrupt(int int_num, int index);
+ /** HW return from error interrupt. */
+ Fault hwrei(unsigned tid);
+
+ bool simPalCheck(int palFunc, unsigned tid);
+
+ /** Returns the Fault for any valid interrupt. */
+ Fault getInterrupts();
+
+ /** Processes any an interrupt fault. */
+ void processInterrupts(Fault interrupt);
+
+ /** Halts the CPU. */
+ void halt() { panic("Halt not implemented!\n"); }
+#endif
+
/** Traps to handle given fault. */
void trap(Fault fault, unsigned tid);
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
- SimObjectParam<AlphaISA::ITB *> itb;
- SimObjectParam<AlphaISA::DTB *> dtb;
+ SimObjectParam<SparcISA::ITB *> itb;
+ SimObjectParam<SparcISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
bool
SparcDynInst<Impl>::simPalCheck(int palFunc)
{
- return this->cpu->simPalCheck(palFunc, this->threadNumber);
+ panic("simPalCheck called, but there's no PAL in SPARC!\n");
+ return false;
}
#else
template <class Impl>
#if FULL_SYSTEM
/** Returns a pointer to the ITB. */
- virtual AlphaISA::ITB *getITBPtr() { return cpu->itb; }
+ TheISA::ITB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
- virtual AlphaISA::DTB *getDTBPtr() { return cpu->dtb; }
+ TheISA::DTB *getDTBPtr() { return cpu->dtb; }
#endif
/** Returns a pointer to this CPU. */