synth_gatemate: Apply new test practice with assert-max

diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys
index c0055e521707211e4cf689d65418ebff2930caf3..bf261ba5ac01b5d4e5d195700e92fac387732c56 100644 (file)
--- a/tests/arch/gatemate/add_sub.ys
+++ b/tests/arch/gatemate/add_sub.ys
@@ -5,5 +5,5 @@ equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivale
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:CC_ADDF
-select -assert-count 4 t:CC_LUT1
+select -assert-max 4 t:CC_LUT1
 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D

diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index 3f9401d689e123bf06f895f503a5799e292dd516..b2ded6e9d7f58bb0f53030bf8723ea8f21c0bdf7 100644 (file)
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -28,7 +28,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
 
 design -load read
@@ -39,5 +39,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
-select -assert-count 1 t:CC_LUT2
+select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D

diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
index 6e3e3a1bebb274800321dbdaf5ff635659d9ff14..6b43ead7ac7f93af2c0341a0f6ca8c40c9154399 100644 (file)
--- a/tests/arch/gatemate/fsm.ys
+++ b/tests/arch/gatemate/fsm.ys
@@ -14,7 +14,7 @@ cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:CC_BUFG
 select -assert-count 6 t:CC_DFF
-select -assert-count 4 t:CC_LUT2
-select -assert-count 2 t:CC_LUT3
-select -assert-count 8 t:CC_LUT4
+select -assert-max 5 t:CC_LUT2
+select -assert-max 4 t:CC_LUT3
+select -assert-max 9 t:CC_LUT4
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys
index 807650b813c6740a1df1463a58f34cc8c30e28a3..5f64c6db5bae3627bf5c093a6b956142d59ee603 100644 (file)
--- a/tests/arch/gatemate/latches.ys
+++ b/tests/arch/gatemate/latches.ys
@@ -25,5 +25,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_DLT
-select -assert-count 2 t:CC_LUT3
+select -assert-max 2 t:CC_LUT3
 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D

diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
index 2718375a2e68e9efa67b09f743d7c9aad882c9af..026406bc8a1d7484b262e1c35e88181253ef47cd 100644 (file)
--- a/tests/arch/gatemate/logic.ys
+++ b/tests/arch/gatemate/logic.ys
@@ -4,7 +4,7 @@ proc
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_LUT1
-select -assert-count 6 t:CC_LUT2
-select -assert-count 2 t:CC_LUT4
+select -assert-max 1 t:CC_LUT1
+select -assert-max 6 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D

diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys
index d10d07f1e2b22e2932a294c3fbe51ae94c76e7b9..ded5fe7293380d31d87a5a7a9266a47290dbe8d6 100644 (file)
--- a/tests/arch/gatemate/mul.ys
+++ b/tests/arch/gatemate/mul.ys
@@ -28,6 +28,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd mul_unsigned_sync # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_MULT
 select -assert-count 1 t:CC_BUFG
-select -assert-count 18 t:CC_LUT4
+select -assert-max 18 t:CC_LUT4
 select -assert-count 18 t:CC_DFF
 select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D

diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys
index 96cb05bfed0cbb5276d04124f75355de1f0d4022..d900fa5e48b107165ab2b34815b99f28079b53bc 100644 (file)
--- a/tests/arch/gatemate/tribuf.ys
+++ b/tests/arch/gatemate/tribuf.ys
@@ -8,6 +8,6 @@ equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate #
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 2 t:CC_IBUF
-select -assert-count 1 t:CC_LUT1
+select -assert-max 1 t:CC_LUT1
 select -assert-count 1 t:CC_TOBUF
 select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D