cpus: add nop instruction and use it to simplify the BIOS.

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 03690eb818ab51ca9c1d76ab3850bf759800752d..302aa70dcc6bf5077ce14e21508da3c2d9c9eb01 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -53,6 +53,7 @@ class BlackParrotRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x50000000: 0x10000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index f05329fa767b1428daef754b00812f57d57231f3..2b6273f3d6034499d55d62f64bf6a8fd53c6c70b 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -23,6 +23,7 @@ class LM32(CPU):
     endianness           = "big"
     gcc_triple           = "lm32-elf"
     linker_output_format = "elf32-lm32"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 808ac0a74a337d218dfe3d3caba1d84e445408bb..76eb59dc7ab6910feb01cd6b769138006bf142a6 100644 (file)
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -21,6 +21,7 @@ class Microwatt(CPU):
     endianness           = "little"
     gcc_triple           = ("powerpc64le-linux")
     linker_output_format = "elf64-powerpcle"
+    nop                  = "nop"
     io_regions           = {0xc0000000: 0x10000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 524cd7f0e092dead04c96fa8bb2328dfb3dcc21c..2a6f21f9eb68842e1563d50a51c712a4414caf44 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -22,6 +22,7 @@ class Minerva(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 8e91dd94c6eafcb0ae7d7dee9854409a4e79c371..5f05ef340213a9a3dc56e5c02b3a9a4320f23672 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -23,6 +23,7 @@ class MOR1KX(CPU):
     gcc_triple           = "or1k-elf"
     clang_triple         = "or1k-linux"
     linker_output_format = "elf32-or1k"
+    nop                  = "l.nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 761a926e169f3a46d21fa90bd52e884638f01964..b3bfc0747cf1b243cdc2bc965e2de043c7f0e522 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -39,6 +39,7 @@ class PicoRV32(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index cac2b05bb5d2145f16501ed1f9efbee3d6f02372..e0100c769dcd4a7af74eb8a114fd5b3beff9c7f3 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -72,6 +72,7 @@ class RocketRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x10000000: 0x70000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index ee31b3487f7eabede52fba105b0c07ba340f7551..dbb6a1b4058c3cfb5818c925176ffb1815f68a67 100644 (file)
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -22,6 +22,7 @@ class SERV(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 990333bd95abcbed380ba8c57b823bf63c95c0a0..45fc0df9dec55baa06532bb650d4f75deb376589 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -82,6 +82,7 @@ class VexRiscv(CPU, AutoCSR):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0256fc77b1849f4f618fdbff2117d897f6008d74..8d51076259f3347eca5ba4ecb5cb2eec4b3c5ba7 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -793,9 +793,11 @@ class SoC(Module):
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
             self.add_config("CPU_RESET_ADDR", reset_address)
         # Add constants
-        self.add_config("CPU_TYPE",       str(name))
-        self.add_config("CPU_VARIANT",    str(variant.split('+')[0]))
+        self.add_config("CPU_TYPE",    str(name))
+        self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
         self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
+        if hasattr(self.cpu, "nop"):
+            self.add_constant("CONFIG_CPU_NOP", self.cpu.nop)
 
     def add_timer(self, name="timer0"):
         self.check_if_exists(name)

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 1e139d5d2b97c841d32b759e40af8a2b41e39099..1923b49b028bc9ba8484b3af34ebf4eb431cd8aa 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -29,31 +29,8 @@
 
 __attribute__((unused)) static void cdelay(int i)
 {
-       /* FIXME: move nop definitions to CPUs */
        while(i > 0) {
-#if defined (__lm32__)
-               __asm__ volatile("nop");
-#elif defined (__or1k__)
-               __asm__ volatile("l.nop");
-#elif defined (__picorv32__)
-               __asm__ volatile("nop");
-#elif defined (__vexriscv__)
-               __asm__ volatile("nop");
-#elif defined (__minerva__)
-               __asm__ volatile("nop");
-#elif defined (__rocket__)
-               __asm__ volatile("nop");
-#elif defined (__powerpc__)
-               __asm__ volatile("nop");
-#elif defined (__microwatt__)
-               __asm__ volatile("nop");
-#elif defined (__blackparrot__)
-               __asm__ volatile("nop");
-#elif defined (__serv__)
-               __asm__ volatile("nop");
-#else
-#error Unsupported architecture
-#endif
+               __asm__ volatile(CONFIG_CPU_NOP);
                i--;
        }
 }