Add support for M340 part.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7230e8b7f7e138361a51fa0c277d8995244e5889..2325da36166f43ae938297f56de09dbf4e94d3b0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2000-02-10  Nick Clifton  <nickc@cygnus.com>
+
+       * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
+       classes.
+       (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
+       "mulsh.h" instructions.
+       * mcore-dis.c (imsk array): Add masks for MULSH and OPSR
+       classes.
+       (print_insn_mcore): Add support for little endian targets.
+       Add support for MULSH and OPSR classes.
+
 2000-02-07  Nick Clifton  <nickc@cygnus.com>
 
        * arm-dis.c (parse_arm_diassembler_option): Rename again.

diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index 518ef5b6930947367760c3d16d9ac7287766243e..096cec9aec06a90e80a00c5f5c7dd382f83db3e6 100644 (file)
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble Motorola M*Core instructions.
-   Copyright (C) 1993, 1999 Free Software Foundation, Inc.
+   Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -57,6 +57,9 @@ static const unsigned short imsk[] =
     /* OMc */ 0xFF00,
     /* SIa */ 0xFE00,
 
+  /* MULSH */ 0xFF00,    
+  /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
+                
     /* JC  */ 0,               /* JC,JU,JL don't appear in object */
     /* JU  */ 0,
     /* JL  */ 0,
@@ -105,7 +108,12 @@ print_insn_mcore (memaddr, info)
       return -1;
     }
 
+  if (info->endian == BFD_ENDIAN_BIG)
     inst = (ibytes[0] << 8) | ibytes[1];
+  else if (info->endian == BFD_ENDIAN_LITTLE)
+    inst = (ibytes[1] << 8) | ibytes[0];
+  else
+    abort ();
 
   /* Just a linear search of the table.  */
   for (op = mcore_table; op->name != 0; op ++)
@@ -129,6 +137,7 @@ print_insn_mcore (memaddr, info)
        case JSR: fprintf (stream, "\t%s", name); break;
        case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
        case O1R1: fprintf (stream, "\t%s, r1", name); break;
+       case MULSH:
        case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
        case X1: fprintf (stream, "\tr1, %s", name); break;
        case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
@@ -193,6 +202,10 @@ print_insn_mcore (memaddr, info)
                break;
              }
            
+           if (info->endian == BFD_ENDIAN_LITTLE)
+             val = (ibytes[3] << 24) | (ibytes[2] << 16)
+               | (ibytes[1] << 8) | (ibytes[0]);
+           else
              val = (ibytes[0] << 24) | (ibytes[1] << 16)
                | (ibytes[2] << 8) | (ibytes[3]);
            
@@ -218,6 +231,10 @@ print_insn_mcore (memaddr, info)
                break;
              }
 
+           if (info->endian == BFD_ENDIAN_LITTLE)
+             val = (ibytes[3] << 24) | (ibytes[2] << 16)
+               | (ibytes[1] << 8) | (ibytes[0]);
+           else
              val = (ibytes[0] << 24) | (ibytes[1] << 16)
                | (ibytes[2] << 8) | (ibytes[3]);
            
@@ -237,6 +254,18 @@ print_insn_mcore (memaddr, info)
          }
          break;
          
+       case OPSR:
+         {
+           static char * fields[] = 
+           {
+             "af", "ie",    "fe",    "fe,ie", 
+             "ee", "ee,ie", "ee,fe", "ee,fe,ie"
+           };
+           
+           fprintf (stream, "\t%s", fields[inst & 0x7]);
+         }
+         break;
+         
        default:
          /* if the disassembler lags the instruction set */
          fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);

diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h
index e0bc333b4c17c6bc279cc26737729247c01b0476..6ff05eeca1663912d6fc96e2a44243d5312a1db8 100644 (file)
--- a/opcodes/mcore-opc.h
+++ b/opcodes/mcore-opc.h
@@ -1,5 +1,5 @@
 /* Assembler instructions for Motorola's Mcore processor
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
 
    
 This program is free software; you can redistribute it and/or modify
@@ -24,6 +24,7 @@ typedef enum
   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
   O1R1,  OMb,  OMc,  SIa,
+  MULSH, OPSR,
   JC,    JU,   JL,   RSI,  DO21,  OB2
 }
 mcore_opclass;
@@ -48,6 +49,7 @@ mcore_opcode_info mcore_table[] =
   { "stop",    O0,     0,      0x0004 },
   { "wait",    O0,     0,      0x0005 },
   { "doze",    O0,     0,      0x0006 },
+  { "idly4",    O0,     0,      0x0007 },
   { "trap",    OT,     0,      0x0008 },
 /* SPACE:                       0x000C - 0x000F */
 /* SPACE:                       0x0010 - 0x001F */
@@ -99,6 +101,8 @@ mcore_opcode_info mcore_table[] =
   { "tst",     O2,     0,      0x0E00 },
   { "cmpne",   O2,     0,      0x0F00 },
   { "mfcr",    OC,     0,      0x1000 },
+  { "psrclr",  OPSR,   0,      0x11F0 },
+  { "psrset",  OPSR,   0,      0x11F8 },
   { "mov",     O2,     0,      0x1200 },
   { "bgenr",   O2,     0,      0x1300 },
   { "rsub",    O2,     0,      0x1400 },
@@ -147,6 +151,8 @@ mcore_opcode_info mcore_table[] =
   { "movi",    I7,     0,      0x6000 },
 #define MCORE_INST_BMASKI_ALT  0x6000
 #define MCORE_INST_BGENI_ALT   0x6000
+  { "mulsh",    MULSH,  0,      0x6800 },
+  { "muls.h",   MULSH,  0,      0x6800 },
 /* SPACE:                       0x6900 - 0x6FFF */
   { "jmpi",    LJ,     1,      0x7000 },
   { "jsri",    LJ,     0,      0x7F00 },