2002-02-11 Chris Demetriou <cgd@broadcom.com>

        * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
        indicating that ALU32_END or ALU64_END are there to check
        for overflow.
        (DADD): Likewise, but also remove previous comment about
        overflow checking.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 548f1cc76b2ed2578bf249dd4ca224ea012da65f..e7d21dce91d19313aec499acac5ff23aea4c6629 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,11 @@
+2002-02-11  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
+       indicating that ALU32_END or ALU64_END are there to check
+       for overflow.
+       (DADD): Likewise, but also remove previous comment about
+       overflow checking.
+
 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 4511d177756c29768c8e32109e2cc672ab987798..6576b7776baf7e06f237cfb4fb4ef21eb13d4a3d 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -237,7 +237,7 @@
   {
     ALU32_BEGIN (GPR[RS]);
     ALU32_ADD (GPR[RT]);
-    ALU32_END (GPR[RD]);
+    ALU32_END (GPR[RD]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RD]);
 }
@@ -255,7 +255,7 @@
   {
     ALU32_BEGIN (GPR[RS]);
     ALU32_ADD (EXTEND16 (IMMEDIATE));
-    ALU32_END (GPR[RT]);
+    ALU32_END (GPR[RT]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RT]);
 }
@@ -709,12 +709,11 @@
 *vr4100:
 *vr5000:
 {
-  /* this check's for overflow */
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   {
     ALU64_BEGIN (GPR[RS]);
     ALU64_ADD (GPR[RT]);
-    ALU64_END (GPR[RD]);
+    ALU64_END (GPR[RD]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RD]);
 }
@@ -732,7 +731,7 @@
   {
     ALU64_BEGIN (GPR[RS]);
     ALU64_ADD (EXTEND16 (IMMEDIATE));
-    ALU64_END (GPR[RT]);
+    ALU64_END (GPR[RT]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RT]);
 }
@@ -1181,7 +1180,7 @@
   {
     ALU64_BEGIN (GPR[RS]);
     ALU64_SUB (GPR[RT]);
-    ALU64_END (GPR[RD]);
+    ALU64_END (GPR[RD]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RD]);
 }
@@ -2210,7 +2209,7 @@
   {
     ALU32_BEGIN (GPR[RS]);
     ALU32_SUB (GPR[RT]);
-    ALU32_END (GPR[RD]);
+    ALU32_END (GPR[RD]);   /* This checks for overflow.  */
   }
   TRACE_ALU_RESULT (GPR[RD]);
 }