Remove tohost/fromhost registers

diff --git a/riscv/htif.cc b/riscv/htif.cc
index 36f8b6b7aa9f8de9766b03b1a1756bdce3beadeb..10dd3e2e776823ccc39addabe9c74e0eb01634e0 100644 (file)
--- a/riscv/htif.cc
+++ b/riscv/htif.cc
@@ -93,16 +93,6 @@ void htif_isasim_t::tick_once()
 
       switch (regno)
       {
-        case CSR_MTOHOST:
-          old_val = proc->get_state()->tohost;
-          if (write)
-            proc->get_state()->tohost = new_val;
-          break;
-        case CSR_MFROMHOST:
-          old_val = proc->get_state()->fromhost;
-          if (write && old_val == 0)
-            proc->set_csr(CSR_MFROMHOST, new_val);
-          break;
         case CSR_MRESET:
           old_val = !proc->running();
           if (write)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f4c64ac564033727ebf960595d5e0f56fb06b528..6eb5ddb9fc8c975e1efadca13f66f2e96a1d4d23 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -349,14 +349,6 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
     case CSR_MBADADDR: state.mbadaddr = val; break;
-    case CSR_MTOHOST:
-      if (state.tohost == 0)
-        state.tohost = val;
-      break;
-    case CSR_MFROMHOST:
-      state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
-      state.fromhost = val;
-      break;
   }
 }
 
@@ -446,12 +438,6 @@ reg_t processor_t::get_csr(int which)
     case CSR_MTVEC: return state.mtvec;
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
-    case CSR_MTOHOST:
-      sim->get_htif()->tick(); // not necessary, but faster
-      return state.tohost;
-    case CSR_MFROMHOST:
-      sim->get_htif()->tick(); // not necessary, but faster
-      return state.fromhost;
   }
   throw trap_illegal_instruction();
 }

diff --git a/riscv/processor.h b/riscv/processor.h
index 9b48cc20890249418c665e8b2389d3add367f779..ccf72efa3f6eb3fde5c470bac41d4095ec773d3d 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -61,8 +61,6 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
-  reg_t tohost;
-  reg_t fromhost;
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state

diff --git a/riscv/sim.cc b/riscv/sim.cc
index edbe2ed0a71f1ffe7c7d52985b1bb0a27bd316a9..a4ae309a7240f97fe3bf9cde565bce167d2a166d 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -102,13 +102,6 @@ bool sim_t::running()
   return false;
 }
 
-void sim_t::stop()
-{
-  procs[0]->state.tohost = 1;
-  while (htif->tick())
-    ;
-}
-
 void sim_t::set_debug(bool value)
 {
   debug = value;

diff --git a/riscv/sim.h b/riscv/sim.h
index c5457b196941180c50c394c860330bbc709413ab..af2d910e44243f82fc52c901be3feb905da54578 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -23,7 +23,6 @@ public:
   // run the simulation to completion
   int run();
   bool running();
-  void stop();
   void set_debug(bool value);
   void set_log(bool value);
   void set_histogram(bool value);
@@ -86,7 +85,6 @@ private:
   reg_t get_freg(const std::vector<std::string>& args);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
-  reg_t get_tohost(const std::vector<std::string>& args);
 
   friend class htif_isasim_t;
   friend class processor_t;