create cpu dir and move lm32/mor1kx in it

diff --git a/misoclib/cpu/__init__.py b/misoclib/cpu/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/misoclib/cpu/lm32/__init__.py b/misoclib/cpu/lm32/__init__.py
new file mode 100644 (file)
index 0000000..ac6b376
--- /dev/null
+++ b/misoclib/cpu/lm32/__init__.py
@@ -0,0 +1,62 @@
+import os
+
+from migen.fhdl.std import *
+from migen.bus import wishbone
+
+class LM32(Module):
+       def __init__(self, platform, eba_reset):
+               self.ibus = i = wishbone.Interface()
+               self.dbus = d = wishbone.Interface()
+               self.interrupt = Signal(32)
+
+               ###
+
+               i_adr_o = Signal(32)
+               d_adr_o = Signal(32)
+               self.specials += Instance("lm32_cpu",
+                       p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
+
+                       i_clk_i=ClockSignal(),
+                       i_rst_i=ResetSignal(),
+
+                       i_interrupt=self.interrupt,
+
+                       o_I_ADR_O=i_adr_o,
+                       o_I_DAT_O=i.dat_w,
+                       o_I_SEL_O=i.sel,
+                       o_I_CYC_O=i.cyc,
+                       o_I_STB_O=i.stb,
+                       o_I_WE_O=i.we,
+                       o_I_CTI_O=i.cti,
+                       o_I_BTE_O=i.bte,
+                       i_I_DAT_I=i.dat_r,
+                       i_I_ACK_I=i.ack,
+                       i_I_ERR_I=i.err,
+                       i_I_RTY_I=0,
+
+                       o_D_ADR_O=d_adr_o,
+                       o_D_DAT_O=d.dat_w,
+                       o_D_SEL_O=d.sel,
+                       o_D_CYC_O=d.cyc,
+                       o_D_STB_O=d.stb,
+                       o_D_WE_O=d.we,
+                       o_D_CTI_O=d.cti,
+                       o_D_BTE_O=d.bte,
+                       i_D_DAT_I=d.dat_r,
+                       i_D_ACK_I=d.ack,
+                       i_D_ERR_I=d.err,
+                       i_D_RTY_I=0)
+
+               self.comb += [
+                       self.ibus.adr.eq(i_adr_o[2:]),
+                       self.dbus.adr.eq(d_adr_o[2:])
+               ]
+
+               # add Verilog sources
+               platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
+                               "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
+                               "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
+                               "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
+                               "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
+                               "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
+               platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
\ No newline at end of file

diff --git a/misoclib/cpu/mor1kx/__init__.py b/misoclib/cpu/mor1kx/__init__.py
new file mode 100644 (file)
index 0000000..bc7ef28
--- /dev/null
+++ b/misoclib/cpu/mor1kx/__init__.py
@@ -0,0 +1,78 @@
+import os
+
+from migen.fhdl.std import *
+from migen.bus import wishbone
+
+class MOR1KX(Module):
+       def __init__(self, platform, reset_pc):
+               self.ibus = i = wishbone.Interface()
+               self.dbus = d = wishbone.Interface()
+               self.interrupt = Signal(32)
+
+               ###
+
+               i_adr_o = Signal(32)
+               d_adr_o = Signal(32)
+               self.specials += Instance("mor1kx",
+                       p_FEATURE_INSTRUCTIONCACHE="ENABLED",
+                       p_OPTION_ICACHE_BLOCK_WIDTH=4,
+                       p_OPTION_ICACHE_SET_WIDTH=8,
+                       p_OPTION_ICACHE_WAYS=1,
+                       p_OPTION_ICACHE_LIMIT_WIDTH=31,
+                       p_FEATURE_DATACACHE="ENABLED",
+                       p_OPTION_DCACHE_BLOCK_WIDTH=4,
+                       p_OPTION_DCACHE_SET_WIDTH=8,
+                       p_OPTION_DCACHE_WAYS=1,
+                       p_OPTION_DCACHE_LIMIT_WIDTH=31,
+                       p_FEATURE_TIMER="NONE",
+                       p_OPTION_PIC_TRIGGER="LEVEL",
+                       p_FEATURE_SYSCALL="NONE",
+                       p_FEATURE_TRAP="NONE",
+                       p_FEATURE_RANGE="NONE",
+                       p_FEATURE_OVERFLOW="NONE",
+                       p_FEATURE_ADDC="NONE",
+                       p_FEATURE_CMOV="NONE",
+                       p_FEATURE_FFL1="NONE",
+                       p_OPTION_CPU0="CAPPUCCINO",
+                       p_OPTION_RESET_PC=reset_pc,
+                       p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
+                       p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
+
+                       i_clk=ClockSignal(),
+                       i_rst=ResetSignal(),
+
+                       i_irq_i=self.interrupt,
+
+                       o_iwbm_adr_o=i_adr_o,
+                       o_iwbm_dat_o=i.dat_w,
+                       o_iwbm_sel_o=i.sel,
+                       o_iwbm_cyc_o=i.cyc,
+                       o_iwbm_stb_o=i.stb,
+                       o_iwbm_we_o=i.we,
+                       o_iwbm_cti_o=i.cti,
+                       o_iwbm_bte_o=i.bte,
+                       i_iwbm_dat_i=i.dat_r,
+                       i_iwbm_ack_i=i.ack,
+                       i_iwbm_err_i=i.err,
+                       i_iwbm_rty_i=0,
+
+                       o_dwbm_adr_o=d_adr_o,
+                       o_dwbm_dat_o=d.dat_w,
+                       o_dwbm_sel_o=d.sel,
+                       o_dwbm_cyc_o=d.cyc,
+                       o_dwbm_stb_o=d.stb,
+                       o_dwbm_we_o=d.we,
+                       o_dwbm_cti_o=d.cti,
+                       o_dwbm_bte_o=d.bte,
+                       i_dwbm_dat_i=d.dat_r,
+                       i_dwbm_ack_i=d.ack,
+                       i_dwbm_err_i=d.err,
+                       i_dwbm_rty_i=0)
+
+               self.comb += [
+                       self.ibus.adr.eq(i_adr_o[2:]),
+                       self.dbus.adr.eq(d_adr_o[2:])
+               ]
+
+               # add Verilog sources
+               platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index 1e99d20a449f4b21fea42c6cc54a5158dbd645ad..0db10b2e9b3cd96ec020f697e60011b3a5d09d9e 100644 (file)
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -6,7 +6,8 @@ from migen.bank import csrgen
 from migen.bus import wishbone, csr, lasmibus, dfi
 from migen.bus import wishbone2lasmi, wishbone2csr
 
-from misoclib import lm32, mor1kx, uart, identifier, timer
+from misoclib import uart, identifier, timer
+from misoclib.cpu import lm32, mor1kx
 from misoclib.sdram import lasmicon
 from misoclib.sdram import dfii
 from misoclib.sdram import memtest

diff --git a/misoclib/lm32/__init__.py b/misoclib/lm32/__init__.py
deleted file mode 100644 (file)
index ac6b376..0000000
--- a/misoclib/lm32/__init__.py
+++ /dev/null
@@ -1,62 +0,0 @@
-import os
-
-from migen.fhdl.std import *
-from migen.bus import wishbone
-
-class LM32(Module):
-       def __init__(self, platform, eba_reset):
-               self.ibus = i = wishbone.Interface()
-               self.dbus = d = wishbone.Interface()
-               self.interrupt = Signal(32)
-
-               ###
-
-               i_adr_o = Signal(32)
-               d_adr_o = Signal(32)
-               self.specials += Instance("lm32_cpu",
-                       p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
-
-                       i_clk_i=ClockSignal(),
-                       i_rst_i=ResetSignal(),
-
-                       i_interrupt=self.interrupt,
-
-                       o_I_ADR_O=i_adr_o,
-                       o_I_DAT_O=i.dat_w,
-                       o_I_SEL_O=i.sel,
-                       o_I_CYC_O=i.cyc,
-                       o_I_STB_O=i.stb,
-                       o_I_WE_O=i.we,
-                       o_I_CTI_O=i.cti,
-                       o_I_BTE_O=i.bte,
-                       i_I_DAT_I=i.dat_r,
-                       i_I_ACK_I=i.ack,
-                       i_I_ERR_I=i.err,
-                       i_I_RTY_I=0,
-
-                       o_D_ADR_O=d_adr_o,
-                       o_D_DAT_O=d.dat_w,
-                       o_D_SEL_O=d.sel,
-                       o_D_CYC_O=d.cyc,
-                       o_D_STB_O=d.stb,
-                       o_D_WE_O=d.we,
-                       o_D_CTI_O=d.cti,
-                       o_D_BTE_O=d.bte,
-                       i_D_DAT_I=d.dat_r,
-                       i_D_ACK_I=d.ack,
-                       i_D_ERR_I=d.err,
-                       i_D_RTY_I=0)
-
-               self.comb += [
-                       self.ibus.adr.eq(i_adr_o[2:]),
-                       self.dbus.adr.eq(d_adr_o[2:])
-               ]
-
-               # add Verilog sources
-               platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
-                               "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
-                               "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
-                               "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
-                               "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
-                               "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
-               platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
\ No newline at end of file

diff --git a/misoclib/mor1kx/__init__.py b/misoclib/mor1kx/__init__.py
deleted file mode 100644 (file)
index bc7ef28..0000000
--- a/misoclib/mor1kx/__init__.py
+++ /dev/null
@@ -1,78 +0,0 @@
-import os
-
-from migen.fhdl.std import *
-from migen.bus import wishbone
-
-class MOR1KX(Module):
-       def __init__(self, platform, reset_pc):
-               self.ibus = i = wishbone.Interface()
-               self.dbus = d = wishbone.Interface()
-               self.interrupt = Signal(32)
-
-               ###
-
-               i_adr_o = Signal(32)
-               d_adr_o = Signal(32)
-               self.specials += Instance("mor1kx",
-                       p_FEATURE_INSTRUCTIONCACHE="ENABLED",
-                       p_OPTION_ICACHE_BLOCK_WIDTH=4,
-                       p_OPTION_ICACHE_SET_WIDTH=8,
-                       p_OPTION_ICACHE_WAYS=1,
-                       p_OPTION_ICACHE_LIMIT_WIDTH=31,
-                       p_FEATURE_DATACACHE="ENABLED",
-                       p_OPTION_DCACHE_BLOCK_WIDTH=4,
-                       p_OPTION_DCACHE_SET_WIDTH=8,
-                       p_OPTION_DCACHE_WAYS=1,
-                       p_OPTION_DCACHE_LIMIT_WIDTH=31,
-                       p_FEATURE_TIMER="NONE",
-                       p_OPTION_PIC_TRIGGER="LEVEL",
-                       p_FEATURE_SYSCALL="NONE",
-                       p_FEATURE_TRAP="NONE",
-                       p_FEATURE_RANGE="NONE",
-                       p_FEATURE_OVERFLOW="NONE",
-                       p_FEATURE_ADDC="NONE",
-                       p_FEATURE_CMOV="NONE",
-                       p_FEATURE_FFL1="NONE",
-                       p_OPTION_CPU0="CAPPUCCINO",
-                       p_OPTION_RESET_PC=reset_pc,
-                       p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
-                       p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
-
-                       i_clk=ClockSignal(),
-                       i_rst=ResetSignal(),
-
-                       i_irq_i=self.interrupt,
-
-                       o_iwbm_adr_o=i_adr_o,
-                       o_iwbm_dat_o=i.dat_w,
-                       o_iwbm_sel_o=i.sel,
-                       o_iwbm_cyc_o=i.cyc,
-                       o_iwbm_stb_o=i.stb,
-                       o_iwbm_we_o=i.we,
-                       o_iwbm_cti_o=i.cti,
-                       o_iwbm_bte_o=i.bte,
-                       i_iwbm_dat_i=i.dat_r,
-                       i_iwbm_ack_i=i.ack,
-                       i_iwbm_err_i=i.err,
-                       i_iwbm_rty_i=0,
-
-                       o_dwbm_adr_o=d_adr_o,
-                       o_dwbm_dat_o=d.dat_w,
-                       o_dwbm_sel_o=d.sel,
-                       o_dwbm_cyc_o=d.cyc,
-                       o_dwbm_stb_o=d.stb,
-                       o_dwbm_we_o=d.we,
-                       o_dwbm_cti_o=d.cti,
-                       o_dwbm_bte_o=d.bte,
-                       i_dwbm_dat_i=d.dat_r,
-                       i_dwbm_ack_i=d.ack,
-                       i_dwbm_err_i=d.err,
-                       i_dwbm_rty_i=0)
-
-               self.comb += [
-                       self.ibus.adr.eq(i_adr_o[2:]),
-                       self.dbus.adr.eq(d_adr_o[2:])
-               ]
-
-               # add Verilog sources
-               platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))