.PHONY: TAGS
-clean:
+_clean:
rm -f *.o work-*cf unisim-*cf $(all)
rm -f fpga/*.o fpga/work-*cf
rm -f sim-unisim/*.o sim-unisim/unisim-*cf
rm -f TAGS
+ rm -f scripts/mw_debug/*.o
+ rm -f scripts/mw_debug/mw_debug
-distclean: clean
+clean: _clean
+ make -f scripts/mw_debug/Makefile clean
+
+distclean: _clean
rm -f *~ fpga/~
+ rm -rf litedram/build
+ rm -f litedram/extras/*~
+ rm -f litedram/gen-src/*~
+ rm -f litedram/gen-src/sdram_init/*~
+ make -f scripts/mw_debug/Makefile distclean
--- /dev/null
+// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
+// Date : 23/03/2020, 17:06:53
+// Component : VexRiscv
+
+
+`define Src2CtrlEnum_defaultEncoding_type [1:0]
+`define Src2CtrlEnum_defaultEncoding_RS 2'b00
+`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
+`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
+`define Src2CtrlEnum_defaultEncoding_PC 2'b11
+
+`define EnvCtrlEnum_defaultEncoding_type [1:0]
+`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
+`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
+`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
+
+`define Src1CtrlEnum_defaultEncoding_type [1:0]
+`define Src1CtrlEnum_defaultEncoding_RS 2'b00
+`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
+`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
+`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
+
+`define BranchCtrlEnum_defaultEncoding_type [1:0]
+`define BranchCtrlEnum_defaultEncoding_INC 2'b00
+`define BranchCtrlEnum_defaultEncoding_B 2'b01
+`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
+`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
+
+`define AluCtrlEnum_defaultEncoding_type [1:0]
+`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
+`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
+`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
+
+`define ShiftCtrlEnum_defaultEncoding_type [1:0]
+`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
+`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
+`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
+`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
+
+`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
+`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
+`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
+`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
+
+module StreamFifoLowLatency (
+ input io_push_valid,
+ output io_push_ready,
+ input io_push_payload_error,
+ input [31:0] io_push_payload_inst,
+ output reg io_pop_valid,
+ input io_pop_ready,
+ output reg io_pop_payload_error,
+ output reg [31:0] io_pop_payload_inst,
+ input io_flush,
+ output [0:0] io_occupancy,
+ input clk,
+ input reset);
+ wire _zz_5_;
+ wire [0:0] _zz_6_;
+ reg _zz_1_;
+ reg pushPtr_willIncrement;
+ reg pushPtr_willClear;
+ wire pushPtr_willOverflowIfInc;
+ wire pushPtr_willOverflow;
+ reg popPtr_willIncrement;
+ reg popPtr_willClear;
+ wire popPtr_willOverflowIfInc;
+ wire popPtr_willOverflow;
+ wire ptrMatch;
+ reg risingOccupancy;
+ wire empty;
+ wire full;
+ wire pushing;
+ wire popping;
+ wire [32:0] _zz_2_;
+ wire [32:0] _zz_3_;
+ reg [32:0] _zz_4_;
+ assign _zz_5_ = (! empty);
+ assign _zz_6_ = _zz_2_[0 : 0];
+ always @ (*) begin
+ _zz_1_ = 1'b0;
+ if(pushing)begin
+ _zz_1_ = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ pushPtr_willIncrement = 1'b0;
+ if(pushing)begin
+ pushPtr_willIncrement = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ pushPtr_willClear = 1'b0;
+ if(io_flush)begin
+ pushPtr_willClear = 1'b1;
+ end
+ end
+
+ assign pushPtr_willOverflowIfInc = 1'b1;
+ assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
+ always @ (*) begin
+ popPtr_willIncrement = 1'b0;
+ if(popping)begin
+ popPtr_willIncrement = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ popPtr_willClear = 1'b0;
+ if(io_flush)begin
+ popPtr_willClear = 1'b1;
+ end
+ end
+
+ assign popPtr_willOverflowIfInc = 1'b1;
+ assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
+ assign ptrMatch = 1'b1;
+ assign empty = (ptrMatch && (! risingOccupancy));
+ assign full = (ptrMatch && risingOccupancy);
+ assign pushing = (io_push_valid && io_push_ready);
+ assign popping = (io_pop_valid && io_pop_ready);
+ assign io_push_ready = (! full);
+ always @ (*) begin
+ if(_zz_5_)begin
+ io_pop_valid = 1'b1;
+ end else begin
+ io_pop_valid = io_push_valid;
+ end
+ end
+
+ assign _zz_2_ = _zz_3_;
+ always @ (*) begin
+ if(_zz_5_)begin
+ io_pop_payload_error = _zz_6_[0];
+ end else begin
+ io_pop_payload_error = io_push_payload_error;
+ end
+ end
+
+ always @ (*) begin
+ if(_zz_5_)begin
+ io_pop_payload_inst = _zz_2_[32 : 1];
+ end else begin
+ io_pop_payload_inst = io_push_payload_inst;
+ end
+ end
+
+ assign io_occupancy = (risingOccupancy && ptrMatch);
+ assign _zz_3_ = _zz_4_;
+ always @ (posedge clk) begin
+ if(reset) begin
+ risingOccupancy <= 1'b0;
+ end else begin
+ if((pushing != popping))begin
+ risingOccupancy <= pushing;
+ end
+ if(io_flush)begin
+ risingOccupancy <= 1'b0;
+ end
+ end
+ end
+
+ always @ (posedge clk) begin
+ if(_zz_1_)begin
+ _zz_4_ <= {io_push_payload_inst,io_push_payload_error};
+ end
+ end
+
+endmodule
+
+module VexRiscv (
+ input [31:0] externalResetVector,
+ input timerInterrupt,
+ input softwareInterrupt,
+ input [31:0] externalInterruptArray,
+ output iBusWishbone_CYC,
+ output iBusWishbone_STB,
+ input iBusWishbone_ACK,
+ output iBusWishbone_WE,
+ output [29:0] iBusWishbone_ADR,
+ input [31:0] iBusWishbone_DAT_MISO,
+ output [31:0] iBusWishbone_DAT_MOSI,
+ output [3:0] iBusWishbone_SEL,
+ input iBusWishbone_ERR,
+ output [1:0] iBusWishbone_BTE,
+ output [2:0] iBusWishbone_CTI,
+ output dBusWishbone_CYC,
+ output dBusWishbone_STB,
+ input dBusWishbone_ACK,
+ output dBusWishbone_WE,
+ output [29:0] dBusWishbone_ADR,
+ input [31:0] dBusWishbone_DAT_MISO,
+ output [31:0] dBusWishbone_DAT_MOSI,
+ output reg [3:0] dBusWishbone_SEL,
+ input dBusWishbone_ERR,
+ output [1:0] dBusWishbone_BTE,
+ output [2:0] dBusWishbone_CTI,
+ input clk,
+ input reset);
+ reg [31:0] _zz_161_;
+ reg [31:0] _zz_162_;
+ reg [31:0] _zz_163_;
+ wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
+ wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
+ wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
+ wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
+ wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
+ wire _zz_164_;
+ wire _zz_165_;
+ wire _zz_166_;
+ wire _zz_167_;
+ wire _zz_168_;
+ wire _zz_169_;
+ wire _zz_170_;
+ wire [1:0] _zz_171_;
+ wire _zz_172_;
+ wire _zz_173_;
+ wire _zz_174_;
+ wire _zz_175_;
+ wire _zz_176_;
+ wire _zz_177_;
+ wire _zz_178_;
+ wire _zz_179_;
+ wire _zz_180_;
+ wire _zz_181_;
+ wire _zz_182_;
+ wire _zz_183_;
+ wire _zz_184_;
+ wire _zz_185_;
+ wire _zz_186_;
+ wire _zz_187_;
+ wire [1:0] _zz_188_;
+ wire _zz_189_;
+ wire [3:0] _zz_190_;
+ wire [2:0] _zz_191_;
+ wire [31:0] _zz_192_;
+ wire [2:0] _zz_193_;
+ wire [0:0] _zz_194_;
+ wire [2:0] _zz_195_;
+ wire [0:0] _zz_196_;
+ wire [2:0] _zz_197_;
+ wire [0:0] _zz_198_;
+ wire [2:0] _zz_199_;
+ wire [0:0] _zz_200_;
+ wire [2:0] _zz_201_;
+ wire [2:0] _zz_202_;
+ wire [0:0] _zz_203_;
+ wire [0:0] _zz_204_;
+ wire [0:0] _zz_205_;
+ wire [0:0] _zz_206_;
+ wire [0:0] _zz_207_;
+ wire [0:0] _zz_208_;
+ wire [0:0] _zz_209_;
+ wire [0:0] _zz_210_;
+ wire [0:0] _zz_211_;
+ wire [0:0] _zz_212_;
+ wire [0:0] _zz_213_;
+ wire [0:0] _zz_214_;
+ wire [2:0] _zz_215_;
+ wire [4:0] _zz_216_;
+ wire [11:0] _zz_217_;
+ wire [11:0] _zz_218_;
+ wire [31:0] _zz_219_;
+ wire [31:0] _zz_220_;
+ wire [31:0] _zz_221_;
+ wire [31:0] _zz_222_;
+ wire [31:0] _zz_223_;
+ wire [31:0] _zz_224_;
+ wire [31:0] _zz_225_;
+ wire [31:0] _zz_226_;
+ wire [32:0] _zz_227_;
+ wire [19:0] _zz_228_;
+ wire [11:0] _zz_229_;
+ wire [11:0] _zz_230_;
+ wire [1:0] _zz_231_;
+ wire [1:0] _zz_232_;
+ wire [1:0] _zz_233_;
+ wire [1:0] _zz_234_;
+ wire [0:0] _zz_235_;
+ wire [0:0] _zz_236_;
+ wire [0:0] _zz_237_;
+ wire [0:0] _zz_238_;
+ wire [0:0] _zz_239_;
+ wire [0:0] _zz_240_;
+ wire [6:0] _zz_241_;
+ wire _zz_242_;
+ wire _zz_243_;
+ wire [1:0] _zz_244_;
+ wire [31:0] _zz_245_;
+ wire [31:0] _zz_246_;
+ wire [31:0] _zz_247_;
+ wire _zz_248_;
+ wire [0:0] _zz_249_;
+ wire [0:0] _zz_250_;
+ wire _zz_251_;
+ wire [0:0] _zz_252_;
+ wire [18:0] _zz_253_;
+ wire [31:0] _zz_254_;
+ wire [31:0] _zz_255_;
+ wire [31:0] _zz_256_;
+ wire [31:0] _zz_257_;
+ wire [31:0] _zz_258_;
+ wire [31:0] _zz_259_;
+ wire _zz_260_;
+ wire [1:0] _zz_261_;
+ wire [1:0] _zz_262_;
+ wire _zz_263_;
+ wire [0:0] _zz_264_;
+ wire [14:0] _zz_265_;
+ wire [31:0] _zz_266_;
+ wire [31:0] _zz_267_;
+ wire [31:0] _zz_268_;
+ wire [31:0] _zz_269_;
+ wire [0:0] _zz_270_;
+ wire [0:0] _zz_271_;
+ wire [0:0] _zz_272_;
+ wire [0:0] _zz_273_;
+ wire _zz_274_;
+ wire [0:0] _zz_275_;
+ wire [11:0] _zz_276_;
+ wire [31:0] _zz_277_;
+ wire [31:0] _zz_278_;
+ wire [31:0] _zz_279_;
+ wire _zz_280_;
+ wire [0:0] _zz_281_;
+ wire [1:0] _zz_282_;
+ wire [0:0] _zz_283_;
+ wire [0:0] _zz_284_;
+ wire [1:0] _zz_285_;
+ wire [1:0] _zz_286_;
+ wire _zz_287_;
+ wire [0:0] _zz_288_;
+ wire [8:0] _zz_289_;
+ wire [31:0] _zz_290_;
+ wire [31:0] _zz_291_;
+ wire [31:0] _zz_292_;
+ wire [31:0] _zz_293_;
+ wire [31:0] _zz_294_;
+ wire [31:0] _zz_295_;
+ wire [31:0] _zz_296_;
+ wire [31:0] _zz_297_;
+ wire _zz_298_;
+ wire _zz_299_;
+ wire [0:0] _zz_300_;
+ wire [0:0] _zz_301_;
+ wire [1:0] _zz_302_;
+ wire [1:0] _zz_303_;
+ wire _zz_304_;
+ wire [0:0] _zz_305_;
+ wire [5:0] _zz_306_;
+ wire [31:0] _zz_307_;
+ wire [31:0] _zz_308_;
+ wire [31:0] _zz_309_;
+ wire [31:0] _zz_310_;
+ wire _zz_311_;
+ wire _zz_312_;
+ wire [1:0] _zz_313_;
+ wire [1:0] _zz_314_;
+ wire _zz_315_;
+ wire [0:0] _zz_316_;
+ wire [2:0] _zz_317_;
+ wire [31:0] _zz_318_;
+ wire [31:0] _zz_319_;
+ wire [31:0] _zz_320_;
+ wire [31:0] _zz_321_;
+ wire _zz_322_;
+ wire [0:0] _zz_323_;
+ wire [0:0] _zz_324_;
+ wire [0:0] _zz_325_;
+ wire [1:0] _zz_326_;
+ wire [5:0] _zz_327_;
+ wire [5:0] _zz_328_;
+ wire _zz_329_;
+ wire _zz_330_;
+ wire [31:0] _zz_331_;
+ wire [31:0] _zz_332_;
+ wire [31:0] _zz_333_;
+ wire [31:0] _zz_334_;
+ wire [31:0] _zz_335_;
+ wire [31:0] _zz_336_;
+ wire [31:0] _zz_337_;
+ wire _zz_338_;
+ wire [0:0] _zz_339_;
+ wire [2:0] _zz_340_;
+ wire [31:0] _zz_341_;
+ wire [31:0] _zz_342_;
+ wire _zz_343_;
+ wire _zz_344_;
+ wire [31:0] _zz_345_;
+ wire [31:0] _zz_346_;
+ wire [31:0] _zz_347_;
+ wire _zz_348_;
+ wire [0:0] _zz_349_;
+ wire [12:0] _zz_350_;
+ wire [31:0] _zz_351_;
+ wire [31:0] _zz_352_;
+ wire [31:0] _zz_353_;
+ wire _zz_354_;
+ wire [0:0] _zz_355_;
+ wire [6:0] _zz_356_;
+ wire [31:0] _zz_357_;
+ wire [31:0] _zz_358_;
+ wire [31:0] _zz_359_;
+ wire _zz_360_;
+ wire [0:0] _zz_361_;
+ wire [0:0] _zz_362_;
+ wire [31:0] decode_RS1;
+ wire execute_BRANCH_DO;
+ wire execute_BYPASSABLE_MEMORY_STAGE;
+ wire decode_BYPASSABLE_MEMORY_STAGE;
+ wire decode_SRC2_FORCE_ZERO;
+ wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_1_;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_2_;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_3_;
+ wire [31:0] writeBack_REGFILE_WRITE_DATA;
+ wire [31:0] execute_REGFILE_WRITE_DATA;
+ wire decode_CSR_WRITE_OPCODE;
+ wire [31:0] execute_BRANCH_CALC;
+ wire [31:0] writeBack_FORMAL_PC_NEXT;
+ wire [31:0] memory_FORMAL_PC_NEXT;
+ wire [31:0] execute_FORMAL_PC_NEXT;
+ wire [31:0] decode_FORMAL_PC_NEXT;
+ wire decode_SRC_LESS_UNSIGNED;
+ wire decode_MEMORY_STORE;
+ wire [31:0] memory_MEMORY_READ_DATA;
+ wire decode_BYPASSABLE_EXECUTE_STAGE;
+ wire decode_IS_CSR;
+ wire [31:0] decode_RS2;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_4_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_5_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_6_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_7_;
+ wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_8_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_9_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_10_;
+ wire [1:0] memory_MEMORY_ADDRESS_LOW;
+ wire [1:0] execute_MEMORY_ADDRESS_LOW;
+ wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_11_;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_13_;
+ wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_14_;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_15_;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_16_;
+ wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_17_;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_18_;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_19_;
+ wire decode_CSR_READ_OPCODE;
+ wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_;
+ wire execute_CSR_READ_OPCODE;
+ wire execute_CSR_WRITE_OPCODE;
+ wire execute_IS_CSR;
+ wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_26_;
+ wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_27_;
+ wire _zz_28_;
+ wire _zz_29_;
+ wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_30_;
+ wire [31:0] memory_BRANCH_CALC;
+ wire memory_BRANCH_DO;
+ wire [31:0] _zz_31_;
+ wire [31:0] execute_PC;
+ wire [31:0] execute_RS1;
+ wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_32_;
+ wire _zz_33_;
+ wire decode_RS2_USE;
+ wire decode_RS1_USE;
+ wire execute_REGFILE_WRITE_VALID;
+ wire execute_BYPASSABLE_EXECUTE_STAGE;
+ wire memory_REGFILE_WRITE_VALID;
+ wire [31:0] memory_INSTRUCTION;
+ wire memory_BYPASSABLE_MEMORY_STAGE;
+ wire writeBack_REGFILE_WRITE_VALID;
+ reg [31:0] _zz_34_;
+ wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_;
+ wire _zz_36_;
+ wire [31:0] _zz_37_;
+ wire [31:0] _zz_38_;
+ wire execute_SRC_LESS_UNSIGNED;
+ wire execute_SRC2_FORCE_ZERO;
+ wire execute_SRC_USE_SUB_LESS;
+ wire [31:0] _zz_39_;
+ wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_40_;
+ wire [31:0] _zz_41_;
+ wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_42_;
+ wire [31:0] _zz_43_;
+ wire decode_SRC_USE_SUB_LESS;
+ wire decode_SRC_ADD_ZERO;
+ wire _zz_44_;
+ wire [31:0] execute_SRC_ADD_SUB;
+ wire execute_SRC_LESS;
+ wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_45_;
+ wire [31:0] _zz_46_;
+ wire [31:0] execute_SRC2;
+ wire [31:0] execute_SRC1;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_;
+ wire [31:0] _zz_48_;
+ wire _zz_49_;
+ reg _zz_50_;
+ wire [31:0] _zz_51_;
+ wire [31:0] _zz_52_;
+ wire [31:0] decode_INSTRUCTION_ANTICIPATED;
+ reg decode_REGFILE_WRITE_VALID;
+ wire decode_LEGAL_INSTRUCTION;
+ wire decode_INSTRUCTION_READY;
+ wire _zz_53_;
+ wire _zz_54_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_55_;
+ wire _zz_56_;
+ wire _zz_57_;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_59_;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_60_;
+ wire _zz_61_;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_62_;
+ wire _zz_63_;
+ wire _zz_64_;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_65_;
+ wire _zz_66_;
+ wire _zz_67_;
+ wire _zz_68_;
+ wire _zz_69_;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_;
+ wire _zz_71_;
+ wire writeBack_MEMORY_STORE;
+ reg [31:0] _zz_72_;
+ wire writeBack_MEMORY_ENABLE;
+ wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
+ wire [31:0] writeBack_MEMORY_READ_DATA;
+ wire memory_MMU_FAULT;
+ wire [31:0] memory_MMU_RSP_physicalAddress;
+ wire memory_MMU_RSP_isIoAccess;
+ wire memory_MMU_RSP_allowRead;
+ wire memory_MMU_RSP_allowWrite;
+ wire memory_MMU_RSP_allowExecute;
+ wire memory_MMU_RSP_exception;
+ wire memory_MMU_RSP_refilling;
+ wire [31:0] memory_PC;
+ wire memory_ALIGNEMENT_FAULT;
+ wire [31:0] memory_REGFILE_WRITE_DATA;
+ wire memory_MEMORY_STORE;
+ wire memory_MEMORY_ENABLE;
+ wire [31:0] _zz_73_;
+ wire [31:0] _zz_74_;
+ wire _zz_75_;
+ wire _zz_76_;
+ wire _zz_77_;
+ wire _zz_78_;
+ wire _zz_79_;
+ wire _zz_80_;
+ wire execute_MMU_FAULT;
+ wire [31:0] execute_MMU_RSP_physicalAddress;
+ wire execute_MMU_RSP_isIoAccess;
+ wire execute_MMU_RSP_allowRead;
+ wire execute_MMU_RSP_allowWrite;
+ wire execute_MMU_RSP_allowExecute;
+ wire execute_MMU_RSP_exception;
+ wire execute_MMU_RSP_refilling;
+ wire _zz_81_;
+ wire [31:0] execute_SRC_ADD;
+ wire [1:0] _zz_82_;
+ wire [31:0] execute_RS2;
+ wire [31:0] execute_INSTRUCTION;
+ wire execute_MEMORY_STORE;
+ wire execute_MEMORY_ENABLE;
+ wire execute_ALIGNEMENT_FAULT;
+ wire _zz_83_;
+ wire decode_MEMORY_ENABLE;
+ reg [31:0] _zz_84_;
+ reg [31:0] _zz_85_;
+ wire [31:0] decode_PC;
+ wire [31:0] _zz_86_;
+ wire [31:0] _zz_87_;
+ wire [31:0] _zz_88_;
+ wire [31:0] decode_INSTRUCTION;
+ wire [31:0] _zz_89_;
+ wire [31:0] writeBack_PC;
+ wire [31:0] writeBack_INSTRUCTION;
+ reg decode_arbitration_haltItself;
+ reg decode_arbitration_haltByOther;
+ reg decode_arbitration_removeIt;
+ reg decode_arbitration_flushIt;
+ reg decode_arbitration_flushNext;
+ wire decode_arbitration_isValid;
+ wire decode_arbitration_isStuck;
+ wire decode_arbitration_isStuckByOthers;
+ wire decode_arbitration_isFlushed;
+ wire decode_arbitration_isMoving;
+ wire decode_arbitration_isFiring;
+ reg execute_arbitration_haltItself;
+ wire execute_arbitration_haltByOther;
+ reg execute_arbitration_removeIt;
+ wire execute_arbitration_flushIt;
+ reg execute_arbitration_flushNext;
+ reg execute_arbitration_isValid;
+ wire execute_arbitration_isStuck;
+ wire execute_arbitration_isStuckByOthers;
+ wire execute_arbitration_isFlushed;
+ wire execute_arbitration_isMoving;
+ wire execute_arbitration_isFiring;
+ reg memory_arbitration_haltItself;
+ wire memory_arbitration_haltByOther;
+ reg memory_arbitration_removeIt;
+ reg memory_arbitration_flushIt;
+ reg memory_arbitration_flushNext;
+ reg memory_arbitration_isValid;
+ wire memory_arbitration_isStuck;
+ wire memory_arbitration_isStuckByOthers;
+ wire memory_arbitration_isFlushed;
+ wire memory_arbitration_isMoving;
+ wire memory_arbitration_isFiring;
+ wire writeBack_arbitration_haltItself;
+ wire writeBack_arbitration_haltByOther;
+ reg writeBack_arbitration_removeIt;
+ wire writeBack_arbitration_flushIt;
+ reg writeBack_arbitration_flushNext;
+ reg writeBack_arbitration_isValid;
+ wire writeBack_arbitration_isStuck;
+ wire writeBack_arbitration_isStuckByOthers;
+ wire writeBack_arbitration_isFlushed;
+ wire writeBack_arbitration_isMoving;
+ wire writeBack_arbitration_isFiring;
+ wire [31:0] lastStageInstruction /* verilator public */ ;
+ wire [31:0] lastStagePc /* verilator public */ ;
+ wire lastStageIsValid /* verilator public */ ;
+ wire lastStageIsFiring /* verilator public */ ;
+ reg IBusSimplePlugin_fetcherHalt;
+ reg IBusSimplePlugin_fetcherflushIt;
+ reg IBusSimplePlugin_incomingInstruction;
+ wire IBusSimplePlugin_pcValids_0;
+ wire IBusSimplePlugin_pcValids_1;
+ wire IBusSimplePlugin_pcValids_2;
+ wire IBusSimplePlugin_pcValids_3;
+ wire iBus_cmd_valid;
+ wire iBus_cmd_ready;
+ wire [31:0] iBus_cmd_payload_pc;
+ wire iBus_rsp_valid;
+ wire iBus_rsp_payload_error;
+ wire [31:0] iBus_rsp_payload_inst;
+ wire IBusSimplePlugin_decodeExceptionPort_valid;
+ reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code;
+ wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr;
+ wire IBusSimplePlugin_mmuBus_cmd_isValid;
+ wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress;
+ wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation;
+ wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress;
+ wire IBusSimplePlugin_mmuBus_rsp_isIoAccess;
+ wire IBusSimplePlugin_mmuBus_rsp_allowRead;
+ wire IBusSimplePlugin_mmuBus_rsp_allowWrite;
+ wire IBusSimplePlugin_mmuBus_rsp_allowExecute;
+ wire IBusSimplePlugin_mmuBus_rsp_exception;
+ wire IBusSimplePlugin_mmuBus_rsp_refilling;
+ wire IBusSimplePlugin_mmuBus_end;
+ wire IBusSimplePlugin_mmuBus_busy;
+ wire IBusSimplePlugin_redoBranch_valid;
+ wire [31:0] IBusSimplePlugin_redoBranch_payload;
+ reg DBusSimplePlugin_memoryExceptionPort_valid;
+ reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
+ wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
+ wire DBusSimplePlugin_mmuBus_cmd_isValid;
+ wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
+ wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
+ wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
+ wire DBusSimplePlugin_mmuBus_rsp_isIoAccess;
+ wire DBusSimplePlugin_mmuBus_rsp_allowRead;
+ wire DBusSimplePlugin_mmuBus_rsp_allowWrite;
+ wire DBusSimplePlugin_mmuBus_rsp_allowExecute;
+ wire DBusSimplePlugin_mmuBus_rsp_exception;
+ wire DBusSimplePlugin_mmuBus_rsp_refilling;
+ wire DBusSimplePlugin_mmuBus_end;
+ wire DBusSimplePlugin_mmuBus_busy;
+ reg DBusSimplePlugin_redoBranch_valid;
+ wire [31:0] DBusSimplePlugin_redoBranch_payload;
+ wire decodeExceptionPort_valid;
+ wire [3:0] decodeExceptionPort_payload_code;
+ wire [31:0] decodeExceptionPort_payload_badAddr;
+ wire BranchPlugin_jumpInterface_valid;
+ wire [31:0] BranchPlugin_jumpInterface_payload;
+ wire BranchPlugin_branchExceptionPort_valid;
+ wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
+ wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
+ reg CsrPlugin_jumpInterface_valid;
+ reg [31:0] CsrPlugin_jumpInterface_payload;
+ wire CsrPlugin_exceptionPendings_0;
+ wire CsrPlugin_exceptionPendings_1;
+ wire CsrPlugin_exceptionPendings_2;
+ wire CsrPlugin_exceptionPendings_3;
+ wire externalInterrupt;
+ wire contextSwitching;
+ reg [1:0] CsrPlugin_privilege;
+ wire CsrPlugin_forceMachineWire;
+ reg CsrPlugin_selfException_valid;
+ reg [3:0] CsrPlugin_selfException_payload_code;
+ wire [31:0] CsrPlugin_selfException_payload_badAddr;
+ wire CsrPlugin_allowInterrupts;
+ wire CsrPlugin_allowException;
+ wire IBusSimplePlugin_jump_pcLoad_valid;
+ wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
+ wire [3:0] _zz_90_;
+ wire [3:0] _zz_91_;
+ wire _zz_92_;
+ wire _zz_93_;
+ wire _zz_94_;
+ wire IBusSimplePlugin_fetchPc_output_valid;
+ wire IBusSimplePlugin_fetchPc_output_ready;
+ wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
+ reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;
+ reg IBusSimplePlugin_fetchPc_corrected;
+ reg IBusSimplePlugin_fetchPc_pcRegPropagate;
+ reg IBusSimplePlugin_fetchPc_booted;
+ reg IBusSimplePlugin_fetchPc_inc;
+ reg [31:0] IBusSimplePlugin_fetchPc_pc;
+ reg IBusSimplePlugin_iBusRsp_stages_0_input_valid;
+ reg IBusSimplePlugin_iBusRsp_stages_0_input_ready;
+ wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
+ wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
+ wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
+ wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
+ reg IBusSimplePlugin_iBusRsp_stages_0_halt;
+ wire IBusSimplePlugin_iBusRsp_stages_0_inputSample;
+ wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
+ wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
+ wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
+ wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
+ wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
+ wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
+ wire IBusSimplePlugin_iBusRsp_stages_1_halt;
+ wire IBusSimplePlugin_iBusRsp_stages_1_inputSample;
+ wire _zz_95_;
+ wire _zz_96_;
+ wire _zz_97_;
+ wire _zz_98_;
+ reg _zz_99_;
+ reg IBusSimplePlugin_iBusRsp_readyForError;
+ wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
+ wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready;
+ wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
+ wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
+ wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
+ wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
+ wire IBusSimplePlugin_injector_decodeInput_valid;
+ wire IBusSimplePlugin_injector_decodeInput_ready;
+ wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
+ wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error;
+ wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
+ wire IBusSimplePlugin_injector_decodeInput_payload_isRvc;
+ reg _zz_100_;
+ reg [31:0] _zz_101_;
+ reg _zz_102_;
+ reg [31:0] _zz_103_;
+ reg _zz_104_;
+ reg IBusSimplePlugin_injector_nextPcCalc_valids_0;
+ reg IBusSimplePlugin_injector_nextPcCalc_valids_1;
+ reg IBusSimplePlugin_injector_nextPcCalc_valids_2;
+ reg IBusSimplePlugin_injector_nextPcCalc_valids_3;
+ reg IBusSimplePlugin_injector_nextPcCalc_valids_4;
+ reg IBusSimplePlugin_injector_decodeRemoved;
+ reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode;
+ reg IBusSimplePlugin_cmd_valid;
+ wire IBusSimplePlugin_cmd_ready;
+ wire [31:0] IBusSimplePlugin_cmd_payload_pc;
+ reg [2:0] IBusSimplePlugin_pendingCmd;
+ wire [2:0] IBusSimplePlugin_pendingCmdNext;
+ reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress;
+ reg IBusSimplePlugin_mmu_joinCtx_isIoAccess;
+ reg IBusSimplePlugin_mmu_joinCtx_allowRead;
+ reg IBusSimplePlugin_mmu_joinCtx_allowWrite;
+ reg IBusSimplePlugin_mmu_joinCtx_allowExecute;
+ reg IBusSimplePlugin_mmu_joinCtx_exception;
+ reg IBusSimplePlugin_mmu_joinCtx_refilling;
+ reg [2:0] IBusSimplePlugin_rspJoin_discardCounter;
+ wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid;
+ wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready;
+ wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
+ wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
+ wire iBus_rsp_takeWhen_valid;
+ wire iBus_rsp_takeWhen_payload_error;
+ wire [31:0] iBus_rsp_takeWhen_payload_inst;
+ wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
+ reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
+ wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
+ wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
+ wire IBusSimplePlugin_rspJoin_join_valid;
+ wire IBusSimplePlugin_rspJoin_join_ready;
+ wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
+ wire IBusSimplePlugin_rspJoin_join_payload_rsp_error;
+ wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
+ wire IBusSimplePlugin_rspJoin_join_payload_isRvc;
+ reg IBusSimplePlugin_rspJoin_exceptionDetected;
+ reg IBusSimplePlugin_rspJoin_redoRequired;
+ wire _zz_105_;
+ wire dBus_cmd_valid;
+ wire dBus_cmd_ready;
+ wire dBus_cmd_payload_wr;
+ wire [31:0] dBus_cmd_payload_address;
+ wire [31:0] dBus_cmd_payload_data;
+ wire [1:0] dBus_cmd_payload_size;
+ wire dBus_rsp_ready;
+ wire dBus_rsp_error;
+ wire [31:0] dBus_rsp_data;
+ wire _zz_106_;
+ reg execute_DBusSimplePlugin_skipCmd;
+ reg [31:0] _zz_107_;
+ reg [3:0] _zz_108_;
+ wire [3:0] execute_DBusSimplePlugin_formalMask;
+ reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
+ wire _zz_109_;
+ reg [31:0] _zz_110_;
+ wire _zz_111_;
+ reg [31:0] _zz_112_;
+ reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
+ wire [25:0] _zz_113_;
+ wire _zz_114_;
+ wire _zz_115_;
+ wire _zz_116_;
+ wire _zz_117_;
+ wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_;
+ wire `Src1CtrlEnum_defaultEncoding_type _zz_119_;
+ wire `Src2CtrlEnum_defaultEncoding_type _zz_120_;
+ wire `AluCtrlEnum_defaultEncoding_type _zz_121_;
+ wire `BranchCtrlEnum_defaultEncoding_type _zz_122_;
+ wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_;
+ wire `EnvCtrlEnum_defaultEncoding_type _zz_124_;
+ wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
+ wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
+ wire [31:0] decode_RegFilePlugin_rs1Data;
+ wire [31:0] decode_RegFilePlugin_rs2Data;
+ reg lastStageRegFileWrite_valid /* verilator public */ ;
+ wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
+ wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
+ reg _zz_125_;
+ reg [31:0] execute_IntAluPlugin_bitwise;
+ reg [31:0] _zz_126_;
+ reg [31:0] _zz_127_;
+ wire _zz_128_;
+ reg [19:0] _zz_129_;
+ wire _zz_130_;
+ reg [19:0] _zz_131_;
+ reg [31:0] _zz_132_;
+ reg [31:0] execute_SrcPlugin_addSub;
+ wire execute_SrcPlugin_less;
+ reg execute_LightShifterPlugin_isActive;
+ wire execute_LightShifterPlugin_isShift;
+ reg [4:0] execute_LightShifterPlugin_amplitudeReg;
+ wire [4:0] execute_LightShifterPlugin_amplitude;
+ wire [31:0] execute_LightShifterPlugin_shiftInput;
+ wire execute_LightShifterPlugin_done;
+ reg [31:0] _zz_133_;
+ reg _zz_134_;
+ reg _zz_135_;
+ wire _zz_136_;
+ reg _zz_137_;
+ reg [4:0] _zz_138_;
+ wire execute_BranchPlugin_eq;
+ wire [2:0] _zz_139_;
+ reg _zz_140_;
+ reg _zz_141_;
+ wire [31:0] execute_BranchPlugin_branch_src1;
+ wire _zz_142_;
+ reg [10:0] _zz_143_;
+ wire _zz_144_;
+ reg [19:0] _zz_145_;
+ wire _zz_146_;
+ reg [18:0] _zz_147_;
+ reg [31:0] _zz_148_;
+ wire [31:0] execute_BranchPlugin_branch_src2;
+ wire [31:0] execute_BranchPlugin_branchAdder;
+ wire [1:0] CsrPlugin_misa_base;
+ wire [25:0] CsrPlugin_misa_extensions;
+ reg [1:0] CsrPlugin_mtvec_mode;
+ reg [29:0] CsrPlugin_mtvec_base;
+ reg [31:0] CsrPlugin_mepc;
+ reg CsrPlugin_mstatus_MIE;
+ reg CsrPlugin_mstatus_MPIE;
+ reg [1:0] CsrPlugin_mstatus_MPP;
+ reg CsrPlugin_mip_MEIP;
+ reg CsrPlugin_mip_MTIP;
+ reg CsrPlugin_mip_MSIP;
+ reg CsrPlugin_mie_MEIE;
+ reg CsrPlugin_mie_MTIE;
+ reg CsrPlugin_mie_MSIE;
+ reg CsrPlugin_mcause_interrupt;
+ reg [3:0] CsrPlugin_mcause_exceptionCode;
+ reg [31:0] CsrPlugin_mtval;
+ reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
+ reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
+ wire _zz_149_;
+ wire _zz_150_;
+ wire _zz_151_;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
+ reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
+ reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
+ reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
+ wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
+ wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
+ wire [1:0] _zz_152_;
+ wire _zz_153_;
+ wire [1:0] _zz_154_;
+ wire _zz_155_;
+ reg CsrPlugin_interrupt_valid;
+ reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
+ reg [1:0] CsrPlugin_interrupt_targetPrivilege;
+ wire CsrPlugin_exception;
+ wire CsrPlugin_lastStageWasWfi;
+ reg CsrPlugin_pipelineLiberator_done;
+ wire CsrPlugin_interruptJump /* verilator public */ ;
+ reg CsrPlugin_hadException;
+ reg [1:0] CsrPlugin_targetPrivilege;
+ reg [3:0] CsrPlugin_trapCause;
+ reg [1:0] CsrPlugin_xtvec_mode;
+ reg [29:0] CsrPlugin_xtvec_base;
+ wire execute_CsrPlugin_inWfi /* verilator public */ ;
+ reg execute_CsrPlugin_wfiWake;
+ wire execute_CsrPlugin_blockedBySideEffects;
+ reg execute_CsrPlugin_illegalAccess;
+ reg execute_CsrPlugin_illegalInstruction;
+ reg [31:0] execute_CsrPlugin_readData;
+ wire execute_CsrPlugin_writeInstruction;
+ wire execute_CsrPlugin_readInstruction;
+ wire execute_CsrPlugin_writeEnable;
+ wire execute_CsrPlugin_readEnable;
+ wire [31:0] execute_CsrPlugin_readToWriteData;
+ reg [31:0] execute_CsrPlugin_writeData;
+ wire [11:0] execute_CsrPlugin_csrAddress;
+ reg [31:0] externalInterruptArray_regNext;
+ reg [31:0] _zz_156_;
+ wire [31:0] _zz_157_;
+ reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
+ reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
+ reg decode_to_execute_SRC_USE_SUB_LESS;
+ reg execute_to_memory_MMU_FAULT;
+ reg decode_to_execute_CSR_READ_OPCODE;
+ reg [31:0] execute_to_memory_MMU_RSP_physicalAddress;
+ reg execute_to_memory_MMU_RSP_isIoAccess;
+ reg execute_to_memory_MMU_RSP_allowRead;
+ reg execute_to_memory_MMU_RSP_allowWrite;
+ reg execute_to_memory_MMU_RSP_allowExecute;
+ reg execute_to_memory_MMU_RSP_exception;
+ reg execute_to_memory_MMU_RSP_refilling;
+ reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
+ reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
+ reg execute_to_memory_ALIGNEMENT_FAULT;
+ reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
+ reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
+ reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
+ reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
+ reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
+ reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
+ reg [31:0] decode_to_execute_RS2;
+ reg decode_to_execute_IS_CSR;
+ reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
+ reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
+ reg decode_to_execute_MEMORY_STORE;
+ reg execute_to_memory_MEMORY_STORE;
+ reg memory_to_writeBack_MEMORY_STORE;
+ reg decode_to_execute_SRC_LESS_UNSIGNED;
+ reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
+ reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
+ reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
+ reg decode_to_execute_MEMORY_ENABLE;
+ reg execute_to_memory_MEMORY_ENABLE;
+ reg memory_to_writeBack_MEMORY_ENABLE;
+ reg [31:0] decode_to_execute_PC;
+ reg [31:0] execute_to_memory_PC;
+ reg [31:0] memory_to_writeBack_PC;
+ reg [31:0] execute_to_memory_BRANCH_CALC;
+ reg decode_to_execute_CSR_WRITE_OPCODE;
+ reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
+ reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
+ reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
+ reg decode_to_execute_SRC2_FORCE_ZERO;
+ reg [31:0] decode_to_execute_INSTRUCTION;
+ reg [31:0] execute_to_memory_INSTRUCTION;
+ reg [31:0] memory_to_writeBack_INSTRUCTION;
+ reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
+ reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
+ reg execute_to_memory_BRANCH_DO;
+ reg [31:0] decode_to_execute_RS1;
+ reg decode_to_execute_REGFILE_WRITE_VALID;
+ reg execute_to_memory_REGFILE_WRITE_VALID;
+ reg memory_to_writeBack_REGFILE_WRITE_VALID;
+ wire iBus_cmd_m2sPipe_valid;
+ wire iBus_cmd_m2sPipe_ready;
+ wire [31:0] iBus_cmd_m2sPipe_payload_pc;
+ reg _zz_158_;
+ reg [31:0] _zz_159_;
+ wire dBus_cmd_halfPipe_valid;
+ wire dBus_cmd_halfPipe_ready;
+ wire dBus_cmd_halfPipe_payload_wr;
+ wire [31:0] dBus_cmd_halfPipe_payload_address;
+ wire [31:0] dBus_cmd_halfPipe_payload_data;
+ wire [1:0] dBus_cmd_halfPipe_payload_size;
+ reg dBus_cmd_halfPipe_regs_valid;
+ reg dBus_cmd_halfPipe_regs_ready;
+ reg dBus_cmd_halfPipe_regs_payload_wr;
+ reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
+ reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
+ reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
+ reg [3:0] _zz_160_;
+ `ifndef SYNTHESIS
+ reg [23:0] decode_SRC2_CTRL_string;
+ reg [23:0] _zz_1__string;
+ reg [23:0] _zz_2__string;
+ reg [23:0] _zz_3__string;
+ reg [39:0] _zz_4__string;
+ reg [39:0] _zz_5__string;
+ reg [39:0] _zz_6__string;
+ reg [39:0] _zz_7__string;
+ reg [39:0] decode_ENV_CTRL_string;
+ reg [39:0] _zz_8__string;
+ reg [39:0] _zz_9__string;
+ reg [39:0] _zz_10__string;
+ reg [95:0] decode_SRC1_CTRL_string;
+ reg [95:0] _zz_11__string;
+ reg [95:0] _zz_12__string;
+ reg [95:0] _zz_13__string;
+ reg [31:0] decode_BRANCH_CTRL_string;
+ reg [31:0] _zz_14__string;
+ reg [31:0] _zz_15__string;
+ reg [31:0] _zz_16__string;
+ reg [63:0] decode_ALU_CTRL_string;
+ reg [63:0] _zz_17__string;
+ reg [63:0] _zz_18__string;
+ reg [63:0] _zz_19__string;
+ reg [71:0] decode_SHIFT_CTRL_string;
+ reg [71:0] _zz_20__string;
+ reg [71:0] _zz_21__string;
+ reg [71:0] _zz_22__string;
+ reg [39:0] decode_ALU_BITWISE_CTRL_string;
+ reg [39:0] _zz_23__string;
+ reg [39:0] _zz_24__string;
+ reg [39:0] _zz_25__string;
+ reg [39:0] memory_ENV_CTRL_string;
+ reg [39:0] _zz_26__string;
+ reg [39:0] execute_ENV_CTRL_string;
+ reg [39:0] _zz_27__string;
+ reg [39:0] writeBack_ENV_CTRL_string;
+ reg [39:0] _zz_30__string;
+ reg [31:0] execute_BRANCH_CTRL_string;
+ reg [31:0] _zz_32__string;
+ reg [71:0] execute_SHIFT_CTRL_string;
+ reg [71:0] _zz_35__string;
+ reg [23:0] execute_SRC2_CTRL_string;
+ reg [23:0] _zz_40__string;
+ reg [95:0] execute_SRC1_CTRL_string;
+ reg [95:0] _zz_42__string;
+ reg [63:0] execute_ALU_CTRL_string;
+ reg [63:0] _zz_45__string;
+ reg [39:0] execute_ALU_BITWISE_CTRL_string;
+ reg [39:0] _zz_47__string;
+ reg [39:0] _zz_55__string;
+ reg [39:0] _zz_58__string;
+ reg [31:0] _zz_59__string;
+ reg [63:0] _zz_60__string;
+ reg [23:0] _zz_62__string;
+ reg [95:0] _zz_65__string;
+ reg [71:0] _zz_70__string;
+ reg [71:0] _zz_118__string;
+ reg [95:0] _zz_119__string;
+ reg [23:0] _zz_120__string;
+ reg [63:0] _zz_121__string;
+ reg [31:0] _zz_122__string;
+ reg [39:0] _zz_123__string;
+ reg [39:0] _zz_124__string;
+ reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
+ reg [71:0] decode_to_execute_SHIFT_CTRL_string;
+ reg [63:0] decode_to_execute_ALU_CTRL_string;
+ reg [31:0] decode_to_execute_BRANCH_CTRL_string;
+ reg [95:0] decode_to_execute_SRC1_CTRL_string;
+ reg [39:0] decode_to_execute_ENV_CTRL_string;
+ reg [39:0] execute_to_memory_ENV_CTRL_string;
+ reg [39:0] memory_to_writeBack_ENV_CTRL_string;
+ reg [23:0] decode_to_execute_SRC2_CTRL_string;
+ `endif
+
+ (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
+ assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
+ assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR);
+ assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00));
+ assign _zz_167_ = (! execute_arbitration_isStuckByOthers);
+ assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00));
+ assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
+ assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
+ assign _zz_171_ = writeBack_INSTRUCTION[29 : 28];
+ assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling);
+ assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute)));
+ assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE));
+ assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers))));
+ assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
+ assign _zz_177_ = (1'b1 || (! 1'b1));
+ assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
+ assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE));
+ assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
+ assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE));
+ assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL));
+ assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
+ assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0));
+ assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0));
+ assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0));
+ assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid);
+ assign _zz_188_ = writeBack_INSTRUCTION[13 : 12];
+ assign _zz_189_ = execute_INSTRUCTION[13];
+ assign _zz_190_ = (_zz_90_ - (4'b0001));
+ assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)};
+ assign _zz_192_ = {29'd0, _zz_191_};
+ assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_);
+ assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);
+ assign _zz_195_ = {2'd0, _zz_194_};
+ assign _zz_196_ = iBus_rsp_valid;
+ assign _zz_197_ = {2'd0, _zz_196_};
+ assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)));
+ assign _zz_199_ = {2'd0, _zz_198_};
+ assign _zz_200_ = iBus_rsp_valid;
+ assign _zz_201_ = {2'd0, _zz_200_};
+ assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100));
+ assign _zz_203_ = _zz_113_[2 : 2];
+ assign _zz_204_ = _zz_113_[4 : 4];
+ assign _zz_205_ = _zz_113_[5 : 5];
+ assign _zz_206_ = _zz_113_[6 : 6];
+ assign _zz_207_ = _zz_113_[9 : 9];
+ assign _zz_208_ = _zz_113_[10 : 10];
+ assign _zz_209_ = _zz_113_[13 : 13];
+ assign _zz_210_ = _zz_113_[20 : 20];
+ assign _zz_211_ = _zz_113_[21 : 21];
+ assign _zz_212_ = _zz_113_[24 : 24];
+ assign _zz_213_ = _zz_113_[25 : 25];
+ assign _zz_214_ = execute_SRC_LESS;
+ assign _zz_215_ = (3'b100);
+ assign _zz_216_ = execute_INSTRUCTION[19 : 15];
+ assign _zz_217_ = execute_INSTRUCTION[31 : 20];
+ assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
+ assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_));
+ assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_));
+ assign _zz_221_ = execute_SRC1;
+ assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
+ assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_);
+ assign _zz_224_ = (32'b00000000000000000000000000000001);
+ assign _zz_225_ = (32'b00000000000000000000000000000000);
+ assign _zz_226_ = (_zz_227_ >>> 1);
+ assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
+ assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
+ assign _zz_229_ = execute_INSTRUCTION[31 : 20];
+ assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
+ assign _zz_231_ = (_zz_152_ & (~ _zz_232_));
+ assign _zz_232_ = (_zz_152_ - (2'b01));
+ assign _zz_233_ = (_zz_154_ & (~ _zz_234_));
+ assign _zz_234_ = (_zz_154_ - (2'b01));
+ assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7];
+ assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3];
+ assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3];
+ assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11];
+ assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7];
+ assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3];
+ assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
+ assign _zz_242_ = 1'b1;
+ assign _zz_243_ = 1'b1;
+ assign _zz_244_ = {_zz_94_,_zz_93_};
+ assign _zz_245_ = (32'b00000000000000000000000000010000);
+ assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000));
+ assign _zz_247_ = (32'b00000000000000000000000001010000);
+ assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000));
+ assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000));
+ assign _zz_250_ = (1'b0);
+ assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00));
+ assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0));
+ assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}};
+ assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
+ assign _zz_255_ = (32'b00000000000000000000000000100100);
+ assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100));
+ assign _zz_257_ = (32'b00000000000000000001000000010000);
+ assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000));
+ assign _zz_259_ = (32'b00000000000000000001000000000000);
+ assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
+ assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)};
+ assign _zz_262_ = (2'b00);
+ assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0));
+ assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00));
+ assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}};
+ assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
+ assign _zz_267_ = (32'b00000000000000000000000000000100);
+ assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
+ assign _zz_269_ = (32'b00000000000000000000000001000000);
+ assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000));
+ assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000));
+ assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000));
+ assign _zz_273_ = (1'b0);
+ assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000));
+ assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00));
+ assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}};
+ assign _zz_277_ = (32'b00000000000000000110000000010100);
+ assign _zz_278_ = (32'b00000000000000000101000000010100);
+ assign _zz_279_ = (32'b00000000000000000110000000010100);
+ assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000));
+ assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000));
+ assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)};
+ assign _zz_283_ = _zz_117_;
+ assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000));
+ assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)};
+ assign _zz_286_ = (2'b00);
+ assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00));
+ assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00));
+ assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}};
+ assign _zz_290_ = (32'b00000000000000000000000000011000);
+ assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100));
+ assign _zz_292_ = (32'b00000000000000000010000000000000);
+ assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
+ assign _zz_294_ = (32'b00000000000000000001000000000000);
+ assign _zz_295_ = (32'b00000000000000000000000001110000);
+ assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000));
+ assign _zz_297_ = (32'b00000000000000000000000000000000);
+ assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000));
+ assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000));
+ assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000));
+ assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000));
+ assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_};
+ assign _zz_303_ = (2'b00);
+ assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00));
+ assign _zz_305_ = (_zz_312_ != (1'b0));
+ assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}};
+ assign _zz_307_ = (32'b00000000000000000001000001010000);
+ assign _zz_308_ = (32'b00000000000000000010000001010000);
+ assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100));
+ assign _zz_310_ = (32'b00000000000000000000000000000100);
+ assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100));
+ assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000));
+ assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)};
+ assign _zz_314_ = (2'b00);
+ assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000));
+ assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000));
+ assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}};
+ assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100));
+ assign _zz_319_ = (32'b00000000000000000000000000100000);
+ assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
+ assign _zz_321_ = (32'b00000000000000000000000000100000);
+ assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000));
+ assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000));
+ assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000));
+ assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000));
+ assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)};
+ assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}};
+ assign _zz_328_ = (6'b000000);
+ assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0));
+ assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00));
+ assign _zz_331_ = (32'b00000000000000000010000000010100);
+ assign _zz_332_ = (32'b01000000000000000100000000110100);
+ assign _zz_333_ = (32'b00000000000000000000000001010000);
+ assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000));
+ assign _zz_335_ = (32'b00000000000000000000000000000000);
+ assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000));
+ assign _zz_337_ = (32'b00000000000000000000000001000000);
+ assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000));
+ assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000));
+ assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}};
+ assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
+ assign _zz_342_ = (32'b00000000000000000101000000010000);
+ assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000));
+ assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000));
+ assign _zz_345_ = (32'b00000000000000000001000001111111);
+ assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
+ assign _zz_347_ = (32'b00000000000000000010000001110011);
+ assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
+ assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
+ assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}};
+ assign _zz_351_ = (32'b00000000000000000101000001011111);
+ assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
+ assign _zz_353_ = (32'b00000000000000000000000001100011);
+ assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
+ assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011));
+ assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}};
+ assign _zz_357_ = (32'b10111110000000000111000001111111);
+ assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
+ assign _zz_359_ = (32'b00000000000000000000000000110011);
+ assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011));
+ assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011));
+ assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011));
+ always @ (posedge clk) begin
+ if(_zz_50_) begin
+ RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
+ end
+ end
+
+ always @ (posedge clk) begin
+ if(_zz_242_) begin
+ _zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
+ end
+ end
+
+ always @ (posedge clk) begin
+ if(_zz_243_) begin
+ _zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
+ end
+ end
+
+ StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
+ .io_push_valid(iBus_rsp_takeWhen_valid),
+ .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready),
+ .io_push_payload_error(iBus_rsp_takeWhen_payload_error),
+ .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst),
+ .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
+ .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready),
+ .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error),
+ .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst),
+ .io_flush(IBusSimplePlugin_fetcherflushIt),
+ .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy),
+ .clk(clk),
+ .reset(reset)
+ );
+ always @(*) begin
+ case(_zz_244_)
+ 2'b00 : begin
+ _zz_163_ = CsrPlugin_jumpInterface_payload;
+ end
+ 2'b01 : begin
+ _zz_163_ = DBusSimplePlugin_redoBranch_payload;
+ end
+ 2'b10 : begin
+ _zz_163_ = BranchPlugin_jumpInterface_payload;
+ end
+ default : begin
+ _zz_163_ = IBusSimplePlugin_redoBranch_payload;
+ end
+ endcase
+ end
+
+ `ifndef SYNTHESIS
+ always @(*) begin
+ case(decode_SRC2_CTRL)
+ `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
+ default : decode_SRC2_CTRL_string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_1_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC ";
+ default : _zz_1__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_2_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC ";
+ default : _zz_2__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_3_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC ";
+ default : _zz_3__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_4_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL";
+ default : _zz_4__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_5_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL";
+ default : _zz_5__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_6_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL";
+ default : _zz_6__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_7_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL";
+ default : _zz_7__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL";
+ default : decode_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_8_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL";
+ default : _zz_8__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_9_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL";
+ default : _zz_9__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_10_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL";
+ default : _zz_10__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_SRC1_CTRL)
+ `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
+ default : decode_SRC1_CTRL_string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_11_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 ";
+ default : _zz_11__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_12_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 ";
+ default : _zz_12__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_13_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 ";
+ default : _zz_13__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_BRANCH_CTRL)
+ `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
+ default : decode_BRANCH_CTRL_string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_14_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR";
+ default : _zz_14__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_15_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR";
+ default : _zz_15__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_16_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR";
+ default : _zz_16__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_ALU_CTRL)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
+ default : decode_ALU_CTRL_string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_17_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE ";
+ default : _zz_17__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_18_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE ";
+ default : _zz_18__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_19_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE ";
+ default : _zz_19__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_SHIFT_CTRL)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
+ default : decode_SHIFT_CTRL_string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_20_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 ";
+ default : _zz_20__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_21_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 ";
+ default : _zz_21__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_22_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 ";
+ default : _zz_22__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_ALU_BITWISE_CTRL)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
+ default : decode_ALU_BITWISE_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_23_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1";
+ default : _zz_23__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_24_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1";
+ default : _zz_24__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_25_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1";
+ default : _zz_25__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(memory_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL";
+ default : memory_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_26_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL";
+ default : _zz_26__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL";
+ default : execute_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_27_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL";
+ default : _zz_27__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(writeBack_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL";
+ default : writeBack_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_30_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL";
+ default : _zz_30__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_BRANCH_CTRL)
+ `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
+ default : execute_BRANCH_CTRL_string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_32_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR";
+ default : _zz_32__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_SHIFT_CTRL)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
+ default : execute_SHIFT_CTRL_string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_35_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 ";
+ default : _zz_35__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_SRC2_CTRL)
+ `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
+ default : execute_SRC2_CTRL_string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_40_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC ";
+ default : _zz_40__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(execute_SRC1_CTRL)
+ `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
+ default : execute_SRC1_CTRL_string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_42_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 ";
+ default : _zz_42__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_ALU_CTRL)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
+ default : execute_ALU_CTRL_string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_45_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE ";
+ default : _zz_45__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_ALU_BITWISE_CTRL)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
+ default : execute_ALU_BITWISE_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_47_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1";
+ default : _zz_47__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_55_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL";
+ default : _zz_55__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_58_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1";
+ default : _zz_58__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_59_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR";
+ default : _zz_59__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_60_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE ";
+ default : _zz_60__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_62_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC ";
+ default : _zz_62__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_65_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 ";
+ default : _zz_65__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_70_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1 ";
+ default : _zz_70__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_118_)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1 ";
+ default : _zz_118__string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_119_)
+ `Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1 ";
+ default : _zz_119__string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_120_)
+ `Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC ";
+ default : _zz_120__string = "???";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_121_)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE ";
+ default : _zz_121__string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_122_)
+ `BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR";
+ default : _zz_122__string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_123_)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1";
+ default : _zz_123__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(_zz_124_)
+ `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL";
+ default : _zz_124__string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_ALU_BITWISE_CTRL)
+ `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
+ default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_SHIFT_CTRL)
+ `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
+ `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
+ default : decode_to_execute_SHIFT_CTRL_string = "?????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_ALU_CTRL)
+ `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
+ `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
+ default : decode_to_execute_ALU_CTRL_string = "????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_BRANCH_CTRL)
+ `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
+ `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
+ `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
+ `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
+ default : decode_to_execute_BRANCH_CTRL_string = "????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_SRC1_CTRL)
+ `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
+ `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
+ `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
+ default : decode_to_execute_SRC1_CTRL_string = "????????????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
+ default : decode_to_execute_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(execute_to_memory_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
+ default : execute_to_memory_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(memory_to_writeBack_ENV_CTRL)
+ `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
+ `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
+ `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
+ default : memory_to_writeBack_ENV_CTRL_string = "?????";
+ endcase
+ end
+ always @(*) begin
+ case(decode_to_execute_SRC2_CTRL)
+ `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
+ `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
+ `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
+ `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
+ default : decode_to_execute_SRC2_CTRL_string = "???";
+ endcase
+ end
+ `endif
+
+ assign decode_RS1 = _zz_52_;
+ assign execute_BRANCH_DO = _zz_33_;
+ assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
+ assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_;
+ assign decode_SRC2_FORCE_ZERO = _zz_44_;
+ assign decode_SRC2_CTRL = _zz_1_;
+ assign _zz_2_ = _zz_3_;
+ assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
+ assign execute_REGFILE_WRITE_DATA = _zz_46_;
+ assign decode_CSR_WRITE_OPCODE = _zz_29_;
+ assign execute_BRANCH_CALC = _zz_31_;
+ assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
+ assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
+ assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
+ assign decode_FORMAL_PC_NEXT = _zz_86_;
+ assign decode_SRC_LESS_UNSIGNED = _zz_63_;
+ assign decode_MEMORY_STORE = _zz_56_;
+ assign memory_MEMORY_READ_DATA = _zz_73_;
+ assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_;
+ assign decode_IS_CSR = _zz_64_;
+ assign decode_RS2 = _zz_51_;
+ assign _zz_4_ = _zz_5_;
+ assign _zz_6_ = _zz_7_;
+ assign decode_ENV_CTRL = _zz_8_;
+ assign _zz_9_ = _zz_10_;
+ assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
+ assign execute_MEMORY_ADDRESS_LOW = _zz_82_;
+ assign decode_SRC1_CTRL = _zz_11_;
+ assign _zz_12_ = _zz_13_;
+ assign decode_BRANCH_CTRL = _zz_14_;
+ assign _zz_15_ = _zz_16_;
+ assign decode_ALU_CTRL = _zz_17_;
+ assign _zz_18_ = _zz_19_;
+ assign decode_CSR_READ_OPCODE = _zz_28_;
+ assign decode_SHIFT_CTRL = _zz_20_;
+ assign _zz_21_ = _zz_22_;
+ assign decode_ALU_BITWISE_CTRL = _zz_23_;
+ assign _zz_24_ = _zz_25_;
+ assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
+ assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
+ assign execute_IS_CSR = decode_to_execute_IS_CSR;
+ assign memory_ENV_CTRL = _zz_26_;
+ assign execute_ENV_CTRL = _zz_27_;
+ assign writeBack_ENV_CTRL = _zz_30_;
+ assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
+ assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
+ assign execute_PC = decode_to_execute_PC;
+ assign execute_RS1 = decode_to_execute_RS1;
+ assign execute_BRANCH_CTRL = _zz_32_;
+ assign decode_RS2_USE = _zz_67_;
+ assign decode_RS1_USE = _zz_61_;
+ assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
+ assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
+ assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
+ assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
+ assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
+ assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
+ always @ (*) begin
+ _zz_34_ = execute_REGFILE_WRITE_DATA;
+ if(_zz_164_)begin
+ _zz_34_ = _zz_133_;
+ end
+ if(_zz_165_)begin
+ _zz_34_ = execute_CsrPlugin_readData;
+ end
+ end
+
+ assign execute_SHIFT_CTRL = _zz_35_;
+ assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
+ assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
+ assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
+ assign _zz_39_ = execute_PC;
+ assign execute_SRC2_CTRL = _zz_40_;
+ assign execute_SRC1_CTRL = _zz_42_;
+ assign decode_SRC_USE_SUB_LESS = _zz_68_;
+ assign decode_SRC_ADD_ZERO = _zz_57_;
+ assign execute_SRC_ADD_SUB = _zz_38_;
+ assign execute_SRC_LESS = _zz_36_;
+ assign execute_ALU_CTRL = _zz_45_;
+ assign execute_SRC2 = _zz_41_;
+ assign execute_SRC1 = _zz_43_;
+ assign execute_ALU_BITWISE_CTRL = _zz_47_;
+ assign _zz_48_ = writeBack_INSTRUCTION;
+ assign _zz_49_ = writeBack_REGFILE_WRITE_VALID;
+ always @ (*) begin
+ _zz_50_ = 1'b0;
+ if(lastStageRegFileWrite_valid)begin
+ _zz_50_ = 1'b1;
+ end
+ end
+
+ assign decode_INSTRUCTION_ANTICIPATED = _zz_89_;
+ always @ (*) begin
+ decode_REGFILE_WRITE_VALID = _zz_69_;
+ if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
+ decode_REGFILE_WRITE_VALID = 1'b0;
+ end
+ end
+
+ assign decode_LEGAL_INSTRUCTION = _zz_71_;
+ assign decode_INSTRUCTION_READY = 1'b1;
+ assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE;
+ always @ (*) begin
+ _zz_72_ = writeBack_REGFILE_WRITE_DATA;
+ if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
+ _zz_72_ = writeBack_DBusSimplePlugin_rspFormated;
+ end
+ end
+
+ assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
+ assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
+ assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
+ assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT;
+ assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress;
+ assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess;
+ assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead;
+ assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite;
+ assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute;
+ assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception;
+ assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling;
+ assign memory_PC = execute_to_memory_PC;
+ assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;
+ assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
+ assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
+ assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
+ assign execute_MMU_FAULT = _zz_81_;
+ assign execute_MMU_RSP_physicalAddress = _zz_74_;
+ assign execute_MMU_RSP_isIoAccess = _zz_75_;
+ assign execute_MMU_RSP_allowRead = _zz_76_;
+ assign execute_MMU_RSP_allowWrite = _zz_77_;
+ assign execute_MMU_RSP_allowExecute = _zz_78_;
+ assign execute_MMU_RSP_exception = _zz_79_;
+ assign execute_MMU_RSP_refilling = _zz_80_;
+ assign execute_SRC_ADD = _zz_37_;
+ assign execute_RS2 = decode_to_execute_RS2;
+ assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
+ assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
+ assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
+ assign execute_ALIGNEMENT_FAULT = _zz_83_;
+ assign decode_MEMORY_ENABLE = _zz_66_;
+ always @ (*) begin
+ _zz_84_ = memory_FORMAL_PC_NEXT;
+ if(DBusSimplePlugin_redoBranch_valid)begin
+ _zz_84_ = DBusSimplePlugin_redoBranch_payload;
+ end
+ if(BranchPlugin_jumpInterface_valid)begin
+ _zz_84_ = BranchPlugin_jumpInterface_payload;
+ end
+ end
+
+ always @ (*) begin
+ _zz_85_ = decode_FORMAL_PC_NEXT;
+ if(IBusSimplePlugin_redoBranch_valid)begin
+ _zz_85_ = IBusSimplePlugin_redoBranch_payload;
+ end
+ end
+
+ assign decode_PC = _zz_88_;
+ assign decode_INSTRUCTION = _zz_87_;
+ assign writeBack_PC = memory_to_writeBack_PC;
+ assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
+ always @ (*) begin
+ decode_arbitration_haltItself = 1'b0;
+ if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
+ decode_arbitration_haltItself = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ decode_arbitration_haltByOther = 1'b0;
+ if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin
+ decode_arbitration_haltByOther = 1'b1;
+ end
+ if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
+ decode_arbitration_haltByOther = decode_arbitration_isValid;
+ end
+ if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
+ decode_arbitration_haltByOther = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ decode_arbitration_removeIt = 1'b0;
+ if(_zz_166_)begin
+ decode_arbitration_removeIt = 1'b1;
+ end
+ if(decode_arbitration_isFlushed)begin
+ decode_arbitration_removeIt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ decode_arbitration_flushIt = 1'b0;
+ if(IBusSimplePlugin_redoBranch_valid)begin
+ decode_arbitration_flushIt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ decode_arbitration_flushNext = 1'b0;
+ if(IBusSimplePlugin_redoBranch_valid)begin
+ decode_arbitration_flushNext = 1'b1;
+ end
+ if(_zz_166_)begin
+ decode_arbitration_flushNext = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ execute_arbitration_haltItself = 1'b0;
+ if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin
+ execute_arbitration_haltItself = 1'b1;
+ end
+ if(_zz_164_)begin
+ if(_zz_167_)begin
+ if(! execute_LightShifterPlugin_done) begin
+ execute_arbitration_haltItself = 1'b1;
+ end
+ end
+ end
+ if(_zz_165_)begin
+ if(execute_CsrPlugin_blockedBySideEffects)begin
+ execute_arbitration_haltItself = 1'b1;
+ end
+ end
+ end
+
+ assign execute_arbitration_haltByOther = 1'b0;
+ always @ (*) begin
+ execute_arbitration_removeIt = 1'b0;
+ if(CsrPlugin_selfException_valid)begin
+ execute_arbitration_removeIt = 1'b1;
+ end
+ if(execute_arbitration_isFlushed)begin
+ execute_arbitration_removeIt = 1'b1;
+ end
+ end
+
+ assign execute_arbitration_flushIt = 1'b0;
+ always @ (*) begin
+ execute_arbitration_flushNext = 1'b0;
+ if(CsrPlugin_selfException_valid)begin
+ execute_arbitration_flushNext = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ memory_arbitration_haltItself = 1'b0;
+ if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin
+ memory_arbitration_haltItself = 1'b1;
+ end
+ end
+
+ assign memory_arbitration_haltByOther = 1'b0;
+ always @ (*) begin
+ memory_arbitration_removeIt = 1'b0;
+ if(_zz_168_)begin
+ memory_arbitration_removeIt = 1'b1;
+ end
+ if(memory_arbitration_isFlushed)begin
+ memory_arbitration_removeIt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ memory_arbitration_flushIt = 1'b0;
+ if(DBusSimplePlugin_redoBranch_valid)begin
+ memory_arbitration_flushIt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ memory_arbitration_flushNext = 1'b0;
+ if(DBusSimplePlugin_redoBranch_valid)begin
+ memory_arbitration_flushNext = 1'b1;
+ end
+ if(BranchPlugin_jumpInterface_valid)begin
+ memory_arbitration_flushNext = 1'b1;
+ end
+ if(_zz_168_)begin
+ memory_arbitration_flushNext = 1'b1;
+ end
+ end
+
+ assign writeBack_arbitration_haltItself = 1'b0;
+ assign writeBack_arbitration_haltByOther = 1'b0;
+ always @ (*) begin
+ writeBack_arbitration_removeIt = 1'b0;
+ if(writeBack_arbitration_isFlushed)begin
+ writeBack_arbitration_removeIt = 1'b1;
+ end
+ end
+
+ assign writeBack_arbitration_flushIt = 1'b0;
+ always @ (*) begin
+ writeBack_arbitration_flushNext = 1'b0;
+ if(_zz_169_)begin
+ writeBack_arbitration_flushNext = 1'b1;
+ end
+ if(_zz_170_)begin
+ writeBack_arbitration_flushNext = 1'b1;
+ end
+ end
+
+ assign lastStageInstruction = writeBack_INSTRUCTION;
+ assign lastStagePc = writeBack_PC;
+ assign lastStageIsValid = writeBack_arbitration_isValid;
+ assign lastStageIsFiring = writeBack_arbitration_isFiring;
+ always @ (*) begin
+ IBusSimplePlugin_fetcherHalt = 1'b0;
+ if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin
+ IBusSimplePlugin_fetcherHalt = 1'b1;
+ end
+ if(_zz_169_)begin
+ IBusSimplePlugin_fetcherHalt = 1'b1;
+ end
+ if(_zz_170_)begin
+ IBusSimplePlugin_fetcherHalt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ IBusSimplePlugin_fetcherflushIt = 1'b0;
+ if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin
+ IBusSimplePlugin_fetcherflushIt = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ IBusSimplePlugin_incomingInstruction = 1'b0;
+ if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin
+ IBusSimplePlugin_incomingInstruction = 1'b1;
+ end
+ if(IBusSimplePlugin_injector_decodeInput_valid)begin
+ IBusSimplePlugin_incomingInstruction = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_jumpInterface_valid = 1'b0;
+ if(_zz_169_)begin
+ CsrPlugin_jumpInterface_valid = 1'b1;
+ end
+ if(_zz_170_)begin
+ CsrPlugin_jumpInterface_valid = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
+ if(_zz_169_)begin
+ CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
+ end
+ if(_zz_170_)begin
+ case(_zz_171_)
+ 2'b11 : begin
+ CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
+ end
+ default : begin
+ end
+ endcase
+ end
+ end
+
+ assign CsrPlugin_forceMachineWire = 1'b0;
+ assign CsrPlugin_allowInterrupts = 1'b1;
+ assign CsrPlugin_allowException = 1'b1;
+ assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000));
+ assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}};
+ assign _zz_91_ = (_zz_90_ & (~ _zz_190_));
+ assign _zz_92_ = _zz_91_[3];
+ assign _zz_93_ = (_zz_91_[1] || _zz_92_);
+ assign _zz_94_ = (_zz_91_[2] || _zz_92_);
+ assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_;
+ always @ (*) begin
+ IBusSimplePlugin_fetchPc_corrected = 1'b0;
+ if(IBusSimplePlugin_jump_pcLoad_valid)begin
+ IBusSimplePlugin_fetchPc_corrected = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0;
+ if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin
+ IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_);
+ if(IBusSimplePlugin_jump_pcLoad_valid)begin
+ IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload;
+ end
+ IBusSimplePlugin_fetchPc_pc[0] = 1'b0;
+ IBusSimplePlugin_fetchPc_pc[1] = 1'b0;
+ end
+
+ assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted);
+ assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc;
+ always @ (*) begin
+ IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;
+ if(IBusSimplePlugin_mmuBus_busy)begin
+ IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0;
+ end
+ end
+
+ assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready;
+ assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload;
+ assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1;
+ always @ (*) begin
+ IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
+ if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin
+ IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1;
+ end
+ if(_zz_172_)begin
+ IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;
+ end
+ end
+
+ assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt);
+ always @ (*) begin
+ IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_);
+ if(IBusSimplePlugin_mmuBus_busy)begin
+ IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0;
+ end
+ end
+
+ assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_);
+ assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
+ assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0;
+ assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt);
+ assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_);
+ assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_);
+ assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;
+ assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_;
+ assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready);
+ assign _zz_98_ = _zz_99_;
+ assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_;
+ assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg;
+ always @ (*) begin
+ IBusSimplePlugin_iBusRsp_readyForError = 1'b1;
+ if(IBusSimplePlugin_injector_decodeInput_valid)begin
+ IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
+ end
+ if((! IBusSimplePlugin_pcValids_0))begin
+ IBusSimplePlugin_iBusRsp_readyForError = 1'b0;
+ end
+ end
+
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);
+ assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_;
+ assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_;
+ assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_;
+ assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_;
+ assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_;
+ assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst);
+ assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1;
+ assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2;
+ assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3;
+ assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4;
+ assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);
+ assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved));
+ assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc;
+ assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
+ assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100));
+ assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;
+ assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;
+ assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc;
+ assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_);
+ always @ (*) begin
+ IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111)));
+ if(_zz_172_)begin
+ IBusSimplePlugin_cmd_valid = 1'b0;
+ end
+ end
+
+ assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid;
+ assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload;
+ assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
+ assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt);
+ assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)};
+ assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))));
+ assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error;
+ assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst;
+ assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
+ assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
+ assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
+ assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload;
+ always @ (*) begin
+ IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error;
+ if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin
+ IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0;
+ end
+ end
+
+ assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst;
+ always @ (*) begin
+ IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0;
+ if(_zz_173_)begin
+ IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ IBusSimplePlugin_rspJoin_redoRequired = 1'b0;
+ if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin
+ IBusSimplePlugin_rspJoin_redoRequired = 1'b1;
+ end
+ end
+
+ assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid);
+ assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc;
+ assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;
+ assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
+ assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc;
+ assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready);
+ assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);
+ assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired));
+ assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_);
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_);
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc;
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error;
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
+ assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc;
+ assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError);
+ assign IBusSimplePlugin_redoBranch_payload = decode_PC;
+ always @ (*) begin
+ IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx);
+ if(_zz_173_)begin
+ IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100);
+ end
+ end
+
+ assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)};
+ assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError);
+ assign _zz_106_ = 1'b0;
+ assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
+ always @ (*) begin
+ execute_DBusSimplePlugin_skipCmd = 1'b0;
+ if(execute_ALIGNEMENT_FAULT)begin
+ execute_DBusSimplePlugin_skipCmd = 1'b1;
+ end
+ if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
+ execute_DBusSimplePlugin_skipCmd = 1'b1;
+ end
+ end
+
+ assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_));
+ assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
+ assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
+ always @ (*) begin
+ case(dBus_cmd_payload_size)
+ 2'b00 : begin
+ _zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
+ end
+ 2'b01 : begin
+ _zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
+ end
+ default : begin
+ _zz_107_ = execute_RS2[31 : 0];
+ end
+ endcase
+ end
+
+ assign dBus_cmd_payload_data = _zz_107_;
+ assign _zz_82_ = dBus_cmd_payload_address[1 : 0];
+ always @ (*) begin
+ case(dBus_cmd_payload_size)
+ 2'b00 : begin
+ _zz_108_ = (4'b0001);
+ end
+ 2'b01 : begin
+ _zz_108_ = (4'b0011);
+ end
+ default : begin
+ _zz_108_ = (4'b1111);
+ end
+ endcase
+ end
+
+ assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]);
+ assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
+ assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
+ assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
+ assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
+ assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
+ assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
+ assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
+ assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
+ assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
+ assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
+ assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
+ assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception;
+ assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling;
+ assign _zz_73_ = dBus_rsp_data;
+ always @ (*) begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
+ if(_zz_174_)begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
+ end
+ if(memory_ALIGNEMENT_FAULT)begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
+ end
+ if(memory_MMU_RSP_refilling)begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
+ end else begin
+ if(memory_MMU_FAULT)begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
+ end
+ end
+ if(_zz_175_)begin
+ DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
+ if(_zz_174_)begin
+ DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101);
+ end
+ if(memory_ALIGNEMENT_FAULT)begin
+ DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_};
+ end
+ if(! memory_MMU_RSP_refilling) begin
+ if(memory_MMU_FAULT)begin
+ DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101));
+ end
+ end
+ end
+
+ assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;
+ always @ (*) begin
+ DBusSimplePlugin_redoBranch_valid = 1'b0;
+ if(memory_MMU_RSP_refilling)begin
+ DBusSimplePlugin_redoBranch_valid = 1'b1;
+ end
+ if(_zz_175_)begin
+ DBusSimplePlugin_redoBranch_valid = 1'b0;
+ end
+ end
+
+ assign DBusSimplePlugin_redoBranch_payload = memory_PC;
+ always @ (*) begin
+ writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
+ case(writeBack_MEMORY_ADDRESS_LOW)
+ 2'b01 : begin
+ writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
+ end
+ 2'b10 : begin
+ writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
+ end
+ 2'b11 : begin
+ writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
+ end
+ default : begin
+ end
+ endcase
+ end
+
+ assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
+ always @ (*) begin
+ _zz_110_[31] = _zz_109_;
+ _zz_110_[30] = _zz_109_;
+ _zz_110_[29] = _zz_109_;
+ _zz_110_[28] = _zz_109_;
+ _zz_110_[27] = _zz_109_;
+ _zz_110_[26] = _zz_109_;
+ _zz_110_[25] = _zz_109_;
+ _zz_110_[24] = _zz_109_;
+ _zz_110_[23] = _zz_109_;
+ _zz_110_[22] = _zz_109_;
+ _zz_110_[21] = _zz_109_;
+ _zz_110_[20] = _zz_109_;
+ _zz_110_[19] = _zz_109_;
+ _zz_110_[18] = _zz_109_;
+ _zz_110_[17] = _zz_109_;
+ _zz_110_[16] = _zz_109_;
+ _zz_110_[15] = _zz_109_;
+ _zz_110_[14] = _zz_109_;
+ _zz_110_[13] = _zz_109_;
+ _zz_110_[12] = _zz_109_;
+ _zz_110_[11] = _zz_109_;
+ _zz_110_[10] = _zz_109_;
+ _zz_110_[9] = _zz_109_;
+ _zz_110_[8] = _zz_109_;
+ _zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
+ end
+
+ assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
+ always @ (*) begin
+ _zz_112_[31] = _zz_111_;
+ _zz_112_[30] = _zz_111_;
+ _zz_112_[29] = _zz_111_;
+ _zz_112_[28] = _zz_111_;
+ _zz_112_[27] = _zz_111_;
+ _zz_112_[26] = _zz_111_;
+ _zz_112_[25] = _zz_111_;
+ _zz_112_[24] = _zz_111_;
+ _zz_112_[23] = _zz_111_;
+ _zz_112_[22] = _zz_111_;
+ _zz_112_[21] = _zz_111_;
+ _zz_112_[20] = _zz_111_;
+ _zz_112_[19] = _zz_111_;
+ _zz_112_[18] = _zz_111_;
+ _zz_112_[17] = _zz_111_;
+ _zz_112_[16] = _zz_111_;
+ _zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
+ end
+
+ always @ (*) begin
+ case(_zz_188_)
+ 2'b00 : begin
+ writeBack_DBusSimplePlugin_rspFormated = _zz_110_;
+ end
+ 2'b01 : begin
+ writeBack_DBusSimplePlugin_rspFormated = _zz_112_;
+ end
+ default : begin
+ writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
+ end
+ endcase
+ end
+
+ assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress;
+ assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
+ assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
+ assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
+ assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
+ assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
+ assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
+ assign IBusSimplePlugin_mmuBus_busy = 1'b0;
+ assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
+ assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
+ assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
+ assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
+ assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
+ assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
+ assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
+ assign DBusSimplePlugin_mmuBus_busy = 1'b0;
+ assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
+ assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
+ assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
+ assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
+ assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}};
+ assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000));
+ assign _zz_118_ = _zz_113_[1 : 0];
+ assign _zz_70_ = _zz_118_;
+ assign _zz_69_ = _zz_203_[0];
+ assign _zz_68_ = _zz_204_[0];
+ assign _zz_67_ = _zz_205_[0];
+ assign _zz_66_ = _zz_206_[0];
+ assign _zz_119_ = _zz_113_[8 : 7];
+ assign _zz_65_ = _zz_119_;
+ assign _zz_64_ = _zz_207_[0];
+ assign _zz_63_ = _zz_208_[0];
+ assign _zz_120_ = _zz_113_[12 : 11];
+ assign _zz_62_ = _zz_120_;
+ assign _zz_61_ = _zz_209_[0];
+ assign _zz_121_ = _zz_113_[15 : 14];
+ assign _zz_60_ = _zz_121_;
+ assign _zz_122_ = _zz_113_[17 : 16];
+ assign _zz_59_ = _zz_122_;
+ assign _zz_123_ = _zz_113_[19 : 18];
+ assign _zz_58_ = _zz_123_;
+ assign _zz_57_ = _zz_210_[0];
+ assign _zz_56_ = _zz_211_[0];
+ assign _zz_124_ = _zz_113_[23 : 22];
+ assign _zz_55_ = _zz_124_;
+ assign _zz_54_ = _zz_212_[0];
+ assign _zz_53_ = _zz_213_[0];
+ assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
+ assign decodeExceptionPort_payload_code = (4'b0010);
+ assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
+ assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
+ assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
+ assign decode_RegFilePlugin_rs1Data = _zz_161_;
+ assign decode_RegFilePlugin_rs2Data = _zz_162_;
+ assign _zz_52_ = decode_RegFilePlugin_rs1Data;
+ assign _zz_51_ = decode_RegFilePlugin_rs2Data;
+ always @ (*) begin
+ lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring);
+ if(_zz_125_)begin
+ lastStageRegFileWrite_valid = 1'b1;
+ end
+ end
+
+ assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7];
+ assign lastStageRegFileWrite_payload_data = _zz_72_;
+ always @ (*) begin
+ case(execute_ALU_BITWISE_CTRL)
+ `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
+ execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
+ end
+ `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
+ execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
+ end
+ default : begin
+ execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
+ end
+ endcase
+ end
+
+ always @ (*) begin
+ case(execute_ALU_CTRL)
+ `AluCtrlEnum_defaultEncoding_BITWISE : begin
+ _zz_126_ = execute_IntAluPlugin_bitwise;
+ end
+ `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
+ _zz_126_ = {31'd0, _zz_214_};
+ end
+ default : begin
+ _zz_126_ = execute_SRC_ADD_SUB;
+ end
+ endcase
+ end
+
+ assign _zz_46_ = _zz_126_;
+ assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
+ always @ (*) begin
+ case(execute_SRC1_CTRL)
+ `Src1CtrlEnum_defaultEncoding_RS : begin
+ _zz_127_ = execute_RS1;
+ end
+ `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
+ _zz_127_ = {29'd0, _zz_215_};
+ end
+ `Src1CtrlEnum_defaultEncoding_IMU : begin
+ _zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
+ end
+ default : begin
+ _zz_127_ = {27'd0, _zz_216_};
+ end
+ endcase
+ end
+
+ assign _zz_43_ = _zz_127_;
+ assign _zz_128_ = _zz_217_[11];
+ always @ (*) begin
+ _zz_129_[19] = _zz_128_;
+ _zz_129_[18] = _zz_128_;
+ _zz_129_[17] = _zz_128_;
+ _zz_129_[16] = _zz_128_;
+ _zz_129_[15] = _zz_128_;
+ _zz_129_[14] = _zz_128_;
+ _zz_129_[13] = _zz_128_;
+ _zz_129_[12] = _zz_128_;
+ _zz_129_[11] = _zz_128_;
+ _zz_129_[10] = _zz_128_;
+ _zz_129_[9] = _zz_128_;
+ _zz_129_[8] = _zz_128_;
+ _zz_129_[7] = _zz_128_;
+ _zz_129_[6] = _zz_128_;
+ _zz_129_[5] = _zz_128_;
+ _zz_129_[4] = _zz_128_;
+ _zz_129_[3] = _zz_128_;
+ _zz_129_[2] = _zz_128_;
+ _zz_129_[1] = _zz_128_;
+ _zz_129_[0] = _zz_128_;
+ end
+
+ assign _zz_130_ = _zz_218_[11];
+ always @ (*) begin
+ _zz_131_[19] = _zz_130_;
+ _zz_131_[18] = _zz_130_;
+ _zz_131_[17] = _zz_130_;
+ _zz_131_[16] = _zz_130_;
+ _zz_131_[15] = _zz_130_;
+ _zz_131_[14] = _zz_130_;
+ _zz_131_[13] = _zz_130_;
+ _zz_131_[12] = _zz_130_;
+ _zz_131_[11] = _zz_130_;
+ _zz_131_[10] = _zz_130_;
+ _zz_131_[9] = _zz_130_;
+ _zz_131_[8] = _zz_130_;
+ _zz_131_[7] = _zz_130_;
+ _zz_131_[6] = _zz_130_;
+ _zz_131_[5] = _zz_130_;
+ _zz_131_[4] = _zz_130_;
+ _zz_131_[3] = _zz_130_;
+ _zz_131_[2] = _zz_130_;
+ _zz_131_[1] = _zz_130_;
+ _zz_131_[0] = _zz_130_;
+ end
+
+ always @ (*) begin
+ case(execute_SRC2_CTRL)
+ `Src2CtrlEnum_defaultEncoding_RS : begin
+ _zz_132_ = execute_RS2;
+ end
+ `Src2CtrlEnum_defaultEncoding_IMI : begin
+ _zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]};
+ end
+ `Src2CtrlEnum_defaultEncoding_IMS : begin
+ _zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
+ end
+ default : begin
+ _zz_132_ = _zz_39_;
+ end
+ endcase
+ end
+
+ assign _zz_41_ = _zz_132_;
+ always @ (*) begin
+ execute_SrcPlugin_addSub = _zz_219_;
+ if(execute_SRC2_FORCE_ZERO)begin
+ execute_SrcPlugin_addSub = execute_SRC1;
+ end
+ end
+
+ assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
+ assign _zz_38_ = execute_SrcPlugin_addSub;
+ assign _zz_37_ = execute_SrcPlugin_addSub;
+ assign _zz_36_ = execute_SrcPlugin_less;
+ assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
+ assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
+ assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
+ assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
+ always @ (*) begin
+ case(execute_SHIFT_CTRL)
+ `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
+ _zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1);
+ end
+ default : begin
+ _zz_133_ = _zz_226_;
+ end
+ endcase
+ end
+
+ always @ (*) begin
+ _zz_134_ = 1'b0;
+ if(_zz_137_)begin
+ if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin
+ _zz_134_ = 1'b1;
+ end
+ end
+ if(_zz_176_)begin
+ if(_zz_177_)begin
+ if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
+ _zz_134_ = 1'b1;
+ end
+ end
+ end
+ if(_zz_178_)begin
+ if(_zz_179_)begin
+ if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
+ _zz_134_ = 1'b1;
+ end
+ end
+ end
+ if(_zz_180_)begin
+ if(_zz_181_)begin
+ if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
+ _zz_134_ = 1'b1;
+ end
+ end
+ end
+ if((! decode_RS1_USE))begin
+ _zz_134_ = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ _zz_135_ = 1'b0;
+ if(_zz_137_)begin
+ if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin
+ _zz_135_ = 1'b1;
+ end
+ end
+ if(_zz_176_)begin
+ if(_zz_177_)begin
+ if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
+ _zz_135_ = 1'b1;
+ end
+ end
+ end
+ if(_zz_178_)begin
+ if(_zz_179_)begin
+ if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
+ _zz_135_ = 1'b1;
+ end
+ end
+ end
+ if(_zz_180_)begin
+ if(_zz_181_)begin
+ if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
+ _zz_135_ = 1'b1;
+ end
+ end
+ end
+ if((! decode_RS2_USE))begin
+ _zz_135_ = 1'b0;
+ end
+ end
+
+ assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring);
+ assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
+ assign _zz_139_ = execute_INSTRUCTION[14 : 12];
+ always @ (*) begin
+ if((_zz_139_ == (3'b000))) begin
+ _zz_140_ = execute_BranchPlugin_eq;
+ end else if((_zz_139_ == (3'b001))) begin
+ _zz_140_ = (! execute_BranchPlugin_eq);
+ end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin
+ _zz_140_ = (! execute_SRC_LESS);
+ end else begin
+ _zz_140_ = execute_SRC_LESS;
+ end
+ end
+
+ always @ (*) begin
+ case(execute_BRANCH_CTRL)
+ `BranchCtrlEnum_defaultEncoding_INC : begin
+ _zz_141_ = 1'b0;
+ end
+ `BranchCtrlEnum_defaultEncoding_JAL : begin
+ _zz_141_ = 1'b1;
+ end
+ `BranchCtrlEnum_defaultEncoding_JALR : begin
+ _zz_141_ = 1'b1;
+ end
+ default : begin
+ _zz_141_ = _zz_140_;
+ end
+ endcase
+ end
+
+ assign _zz_33_ = _zz_141_;
+ assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC);
+ assign _zz_142_ = _zz_228_[19];
+ always @ (*) begin
+ _zz_143_[10] = _zz_142_;
+ _zz_143_[9] = _zz_142_;
+ _zz_143_[8] = _zz_142_;
+ _zz_143_[7] = _zz_142_;
+ _zz_143_[6] = _zz_142_;
+ _zz_143_[5] = _zz_142_;
+ _zz_143_[4] = _zz_142_;
+ _zz_143_[3] = _zz_142_;
+ _zz_143_[2] = _zz_142_;
+ _zz_143_[1] = _zz_142_;
+ _zz_143_[0] = _zz_142_;
+ end
+
+ assign _zz_144_ = _zz_229_[11];
+ always @ (*) begin
+ _zz_145_[19] = _zz_144_;
+ _zz_145_[18] = _zz_144_;
+ _zz_145_[17] = _zz_144_;
+ _zz_145_[16] = _zz_144_;
+ _zz_145_[15] = _zz_144_;
+ _zz_145_[14] = _zz_144_;
+ _zz_145_[13] = _zz_144_;
+ _zz_145_[12] = _zz_144_;
+ _zz_145_[11] = _zz_144_;
+ _zz_145_[10] = _zz_144_;
+ _zz_145_[9] = _zz_144_;
+ _zz_145_[8] = _zz_144_;
+ _zz_145_[7] = _zz_144_;
+ _zz_145_[6] = _zz_144_;
+ _zz_145_[5] = _zz_144_;
+ _zz_145_[4] = _zz_144_;
+ _zz_145_[3] = _zz_144_;
+ _zz_145_[2] = _zz_144_;
+ _zz_145_[1] = _zz_144_;
+ _zz_145_[0] = _zz_144_;
+ end
+
+ assign _zz_146_ = _zz_230_[11];
+ always @ (*) begin
+ _zz_147_[18] = _zz_146_;
+ _zz_147_[17] = _zz_146_;
+ _zz_147_[16] = _zz_146_;
+ _zz_147_[15] = _zz_146_;
+ _zz_147_[14] = _zz_146_;
+ _zz_147_[13] = _zz_146_;
+ _zz_147_[12] = _zz_146_;
+ _zz_147_[11] = _zz_146_;
+ _zz_147_[10] = _zz_146_;
+ _zz_147_[9] = _zz_146_;
+ _zz_147_[8] = _zz_146_;
+ _zz_147_[7] = _zz_146_;
+ _zz_147_[6] = _zz_146_;
+ _zz_147_[5] = _zz_146_;
+ _zz_147_[4] = _zz_146_;
+ _zz_147_[3] = _zz_146_;
+ _zz_147_[2] = _zz_146_;
+ _zz_147_[1] = _zz_146_;
+ _zz_147_[0] = _zz_146_;
+ end
+
+ always @ (*) begin
+ case(execute_BRANCH_CTRL)
+ `BranchCtrlEnum_defaultEncoding_JAL : begin
+ _zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
+ end
+ `BranchCtrlEnum_defaultEncoding_JALR : begin
+ _zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]};
+ end
+ default : begin
+ _zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
+ end
+ endcase
+ end
+
+ assign execute_BranchPlugin_branch_src2 = _zz_148_;
+ assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
+ assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
+ assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
+ assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
+ assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]);
+ assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
+ assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload;
+ always @ (*) begin
+ CsrPlugin_privilege = (2'b11);
+ if(CsrPlugin_forceMachineWire)begin
+ CsrPlugin_privilege = (2'b11);
+ end
+ end
+
+ assign CsrPlugin_misa_base = (2'b01);
+ assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
+ assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
+ assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
+ assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
+ assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
+ assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
+ assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid};
+ assign _zz_153_ = _zz_231_[0];
+ assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid};
+ assign _zz_155_ = _zz_233_[0];
+ always @ (*) begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
+ if(_zz_166_)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
+ end
+ if(decode_arbitration_isFlushed)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
+ if(CsrPlugin_selfException_valid)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
+ end
+ if(execute_arbitration_isFlushed)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
+ if(_zz_168_)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
+ end
+ if(memory_arbitration_isFlushed)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
+ if(writeBack_arbitration_isFlushed)begin
+ CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
+ end
+ end
+
+ assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
+ assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
+ assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
+ assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
+ assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
+ assign CsrPlugin_lastStageWasWfi = 1'b0;
+ always @ (*) begin
+ CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3);
+ if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
+ CsrPlugin_pipelineLiberator_done = 1'b0;
+ end
+ if(CsrPlugin_hadException)begin
+ CsrPlugin_pipelineLiberator_done = 1'b0;
+ end
+ end
+
+ assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
+ always @ (*) begin
+ CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
+ if(CsrPlugin_hadException)begin
+ CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_trapCause = CsrPlugin_interrupt_code;
+ if(CsrPlugin_hadException)begin
+ CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_xtvec_mode = (2'bxx);
+ case(CsrPlugin_targetPrivilege)
+ 2'b11 : begin
+ CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
+ end
+ default : begin
+ end
+ endcase
+ end
+
+ always @ (*) begin
+ CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
+ case(CsrPlugin_targetPrivilege)
+ 2'b11 : begin
+ CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
+ end
+ default : begin
+ end
+ endcase
+ end
+
+ assign contextSwitching = CsrPlugin_jumpInterface_valid;
+ assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
+ assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
+ assign execute_CsrPlugin_inWfi = 1'b0;
+ assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
+ always @ (*) begin
+ execute_CsrPlugin_illegalAccess = 1'b1;
+ case(execute_CsrPlugin_csrAddress)
+ 12'b101111000000 : begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ 12'b001100000000 : begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ 12'b001101000001 : begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ 12'b001100000101 : begin
+ if(execute_CSR_WRITE_OPCODE)begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ end
+ 12'b001101000100 : begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ 12'b001101000011 : begin
+ if(execute_CSR_READ_OPCODE)begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ end
+ 12'b111111000000 : begin
+ if(execute_CSR_READ_OPCODE)begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ end
+ 12'b001100000100 : begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ 12'b001101000010 : begin
+ if(execute_CSR_READ_OPCODE)begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ end
+ default : begin
+ end
+ endcase
+ if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
+ execute_CsrPlugin_illegalAccess = 1'b1;
+ end
+ if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
+ execute_CsrPlugin_illegalAccess = 1'b0;
+ end
+ end
+
+ always @ (*) begin
+ execute_CsrPlugin_illegalInstruction = 1'b0;
+ if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
+ if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
+ execute_CsrPlugin_illegalInstruction = 1'b1;
+ end
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_selfException_valid = 1'b0;
+ if(_zz_182_)begin
+ CsrPlugin_selfException_valid = 1'b1;
+ end
+ end
+
+ always @ (*) begin
+ CsrPlugin_selfException_payload_code = (4'bxxxx);
+ if(_zz_182_)begin
+ case(CsrPlugin_privilege)
+ 2'b00 : begin
+ CsrPlugin_selfException_payload_code = (4'b1000);
+ end
+ default : begin
+ CsrPlugin_selfException_payload_code = (4'b1011);
+ end
+ endcase
+ end
+ end
+
+ assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
+ always @ (*) begin
+ execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
+ case(execute_CsrPlugin_csrAddress)
+ 12'b101111000000 : begin
+ execute_CsrPlugin_readData[31 : 0] = _zz_156_;
+ end
+ 12'b001100000000 : begin
+ execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
+ execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
+ execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
+ end
+ 12'b001101000001 : begin
+ execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
+ end
+ 12'b001100000101 : begin
+ end
+ 12'b001101000100 : begin
+ execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
+ execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
+ execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
+ end
+ 12'b001101000011 : begin
+ execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
+ end
+ 12'b111111000000 : begin
+ execute_CsrPlugin_readData[31 : 0] = _zz_157_;
+ end
+ 12'b001100000100 : begin
+ execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
+ execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
+ execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
+ end
+ 12'b001101000010 : begin
+ execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
+ execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
+ end
+ default : begin
+ end
+ endcase
+ end
+
+ assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
+ assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
+ assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
+ assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
+ assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
+ always @ (*) begin
+ case(_zz_189_)
+ 1'b0 : begin
+ execute_CsrPlugin_writeData = execute_SRC1;
+ end
+ default : begin
+ execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
+ end
+ endcase
+ end
+
+ assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
+ assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext);
+ assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000));
+ assign _zz_25_ = decode_ALU_BITWISE_CTRL;
+ assign _zz_23_ = _zz_58_;
+ assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL;
+ assign _zz_22_ = decode_SHIFT_CTRL;
+ assign _zz_20_ = _zz_70_;
+ assign _zz_35_ = decode_to_execute_SHIFT_CTRL;
+ assign _zz_19_ = decode_ALU_CTRL;
+ assign _zz_17_ = _zz_60_;
+ assign _zz_45_ = decode_to_execute_ALU_CTRL;
+ assign _zz_16_ = decode_BRANCH_CTRL;
+ assign _zz_14_ = _zz_59_;
+ assign _zz_32_ = decode_to_execute_BRANCH_CTRL;
+ assign _zz_13_ = decode_SRC1_CTRL;
+ assign _zz_11_ = _zz_65_;
+ assign _zz_42_ = decode_to_execute_SRC1_CTRL;
+ assign _zz_10_ = decode_ENV_CTRL;
+ assign _zz_7_ = execute_ENV_CTRL;
+ assign _zz_5_ = memory_ENV_CTRL;
+ assign _zz_8_ = _zz_55_;
+ assign _zz_27_ = decode_to_execute_ENV_CTRL;
+ assign _zz_26_ = execute_to_memory_ENV_CTRL;
+ assign _zz_30_ = memory_to_writeBack_ENV_CTRL;
+ assign _zz_3_ = decode_SRC2_CTRL;
+ assign _zz_1_ = _zz_62_;
+ assign _zz_40_ = decode_to_execute_SRC2_CTRL;
+ assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
+ assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
+ assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
+ assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
+ assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
+ assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
+ assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
+ assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
+ assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
+ assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
+ assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
+ assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
+ assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
+ assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
+ assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
+ assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
+ assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
+ assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
+ assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
+ assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
+ assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready);
+ assign iBus_cmd_m2sPipe_valid = _zz_158_;
+ assign iBus_cmd_m2sPipe_payload_pc = _zz_159_;
+ assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2);
+ assign iBusWishbone_CTI = (3'b000);
+ assign iBusWishbone_BTE = (2'b00);
+ assign iBusWishbone_SEL = (4'b1111);
+ assign iBusWishbone_WE = 1'b0;
+ assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
+ assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid;
+ assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid;
+ assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK);
+ assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK);
+ assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO;
+ assign iBus_rsp_payload_error = 1'b0;
+ assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
+ assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
+ assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
+ assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
+ assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
+ assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
+ assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
+ assign dBusWishbone_CTI = (3'b000);
+ assign dBusWishbone_BTE = (2'b00);
+ always @ (*) begin
+ case(dBus_cmd_halfPipe_payload_size)
+ 2'b00 : begin
+ _zz_160_ = (4'b0001);
+ end
+ 2'b01 : begin
+ _zz_160_ = (4'b0011);
+ end
+ default : begin
+ _zz_160_ = (4'b1111);
+ end
+ endcase
+ end
+
+ always @ (*) begin
+ dBusWishbone_SEL = _zz_241_[3:0];
+ if((! dBus_cmd_halfPipe_payload_wr))begin
+ dBusWishbone_SEL = (4'b1111);
+ end
+ end
+
+ assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
+ assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
+ assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
+ assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
+ assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
+ assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
+ assign dBus_rsp_data = dBusWishbone_DAT_MISO;
+ assign dBus_rsp_error = 1'b0;
+ always @ (posedge clk) begin
+ if(reset) begin
+ IBusSimplePlugin_fetchPc_pcReg <= externalResetVector;
+ IBusSimplePlugin_fetchPc_booted <= 1'b0;
+ IBusSimplePlugin_fetchPc_inc <= 1'b0;
+ _zz_99_ <= 1'b0;
+ _zz_100_ <= 1'b0;
+ IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
+ IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
+ IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
+ IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
+ IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
+ IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
+ IBusSimplePlugin_pendingCmd <= (3'b000);
+ IBusSimplePlugin_rspJoin_discardCounter <= (3'b000);
+ _zz_125_ <= 1'b1;
+ execute_LightShifterPlugin_isActive <= 1'b0;
+ _zz_137_ <= 1'b0;
+ CsrPlugin_mstatus_MIE <= 1'b0;
+ CsrPlugin_mstatus_MPIE <= 1'b0;
+ CsrPlugin_mstatus_MPP <= (2'b11);
+ CsrPlugin_mie_MEIE <= 1'b0;
+ CsrPlugin_mie_MTIE <= 1'b0;
+ CsrPlugin_mie_MSIE <= 1'b0;
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
+ CsrPlugin_interrupt_valid <= 1'b0;
+ CsrPlugin_hadException <= 1'b0;
+ execute_CsrPlugin_wfiWake <= 1'b0;
+ _zz_156_ <= (32'b00000000000000000000000000000000);
+ execute_arbitration_isValid <= 1'b0;
+ memory_arbitration_isValid <= 1'b0;
+ writeBack_arbitration_isValid <= 1'b0;
+ memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
+ memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
+ _zz_158_ <= 1'b0;
+ dBus_cmd_halfPipe_regs_valid <= 1'b0;
+ dBus_cmd_halfPipe_regs_ready <= 1'b1;
+ end else begin
+ IBusSimplePlugin_fetchPc_booted <= 1'b1;
+ if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin
+ IBusSimplePlugin_fetchPc_inc <= 1'b0;
+ end
+ if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin
+ IBusSimplePlugin_fetchPc_inc <= 1'b1;
+ end
+ if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin
+ IBusSimplePlugin_fetchPc_inc <= 1'b0;
+ end
+ if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin
+ IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ _zz_99_ <= 1'b0;
+ end
+ if(_zz_97_)begin
+ _zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid;
+ end
+ if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
+ _zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ _zz_100_ <= 1'b0;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;
+ end
+ if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
+ end
+ if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
+ end
+ if((! execute_arbitration_isStuck))begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
+ end
+ if((! memory_arbitration_isStuck))begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0;
+ end
+ if(decode_arbitration_removeIt)begin
+ IBusSimplePlugin_injector_decodeRemoved <= 1'b1;
+ end
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_injector_decodeRemoved <= 1'b0;
+ end
+ IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext;
+ IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_);
+ if(IBusSimplePlugin_fetcherflushIt)begin
+ IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_);
+ end
+ _zz_125_ <= 1'b0;
+ if(_zz_164_)begin
+ if(_zz_167_)begin
+ execute_LightShifterPlugin_isActive <= 1'b1;
+ if(execute_LightShifterPlugin_done)begin
+ execute_LightShifterPlugin_isActive <= 1'b0;
+ end
+ end
+ end
+ if(execute_arbitration_removeIt)begin
+ execute_LightShifterPlugin_isActive <= 1'b0;
+ end
+ _zz_137_ <= _zz_136_;
+ if((! decode_arbitration_isStuck))begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
+ end else begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
+ end
+ if((! execute_arbitration_isStuck))begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
+ end else begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
+ end
+ if((! memory_arbitration_isStuck))begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
+ end else begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
+ end else begin
+ CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
+ end
+ CsrPlugin_interrupt_valid <= 1'b0;
+ if(_zz_183_)begin
+ if(_zz_184_)begin
+ CsrPlugin_interrupt_valid <= 1'b1;
+ end
+ if(_zz_185_)begin
+ CsrPlugin_interrupt_valid <= 1'b1;
+ end
+ if(_zz_186_)begin
+ CsrPlugin_interrupt_valid <= 1'b1;
+ end
+ end
+ CsrPlugin_hadException <= CsrPlugin_exception;
+ if(_zz_169_)begin
+ case(CsrPlugin_targetPrivilege)
+ 2'b11 : begin
+ CsrPlugin_mstatus_MIE <= 1'b0;
+ CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
+ CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
+ end
+ default : begin
+ end
+ endcase
+ end
+ if(_zz_170_)begin
+ case(_zz_171_)
+ 2'b11 : begin
+ CsrPlugin_mstatus_MPP <= (2'b00);
+ CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
+ CsrPlugin_mstatus_MPIE <= 1'b1;
+ end
+ default : begin
+ end
+ endcase
+ end
+ execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000));
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
+ end
+ if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
+ execute_arbitration_isValid <= 1'b0;
+ end
+ if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
+ execute_arbitration_isValid <= decode_arbitration_isValid;
+ end
+ if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
+ memory_arbitration_isValid <= 1'b0;
+ end
+ if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
+ memory_arbitration_isValid <= execute_arbitration_isValid;
+ end
+ if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
+ writeBack_arbitration_isValid <= 1'b0;
+ end
+ if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
+ writeBack_arbitration_isValid <= memory_arbitration_isValid;
+ end
+ case(execute_CsrPlugin_csrAddress)
+ 12'b101111000000 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ _zz_156_ <= execute_CsrPlugin_writeData[31 : 0];
+ end
+ end
+ 12'b001100000000 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
+ CsrPlugin_mstatus_MPIE <= _zz_235_[0];
+ CsrPlugin_mstatus_MIE <= _zz_236_[0];
+ end
+ end
+ 12'b001101000001 : begin
+ end
+ 12'b001100000101 : begin
+ end
+ 12'b001101000100 : begin
+ end
+ 12'b001101000011 : begin
+ end
+ 12'b111111000000 : begin
+ end
+ 12'b001100000100 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ CsrPlugin_mie_MEIE <= _zz_238_[0];
+ CsrPlugin_mie_MTIE <= _zz_239_[0];
+ CsrPlugin_mie_MSIE <= _zz_240_[0];
+ end
+ end
+ 12'b001101000010 : begin
+ end
+ default : begin
+ end
+ endcase
+ if(iBus_cmd_ready)begin
+ _zz_158_ <= iBus_cmd_valid;
+ end
+ if(_zz_187_)begin
+ dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
+ dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
+ end else begin
+ dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
+ dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
+ end
+ end
+ end
+
+ always @ (posedge clk) begin
+ if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin
+ _zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc;
+ _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error;
+ _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
+ _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc;
+ end
+ if(IBusSimplePlugin_injector_decodeInput_ready)begin
+ IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst;
+ end
+ if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin
+ IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress;
+ IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess;
+ IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead;
+ IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite;
+ IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute;
+ IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception;
+ IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling;
+ end
+ if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
+ $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
+ end
+ if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin
+ $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend");
+ end
+ if(_zz_164_)begin
+ if(_zz_167_)begin
+ execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
+ end
+ end
+ if(_zz_136_)begin
+ _zz_138_ <= _zz_48_[11 : 7];
+ end
+ CsrPlugin_mip_MEIP <= externalInterrupt;
+ CsrPlugin_mip_MTIP <= timerInterrupt;
+ CsrPlugin_mip_MSIP <= softwareInterrupt;
+ CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
+ if(writeBack_arbitration_isFiring)begin
+ CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
+ end
+ if(_zz_166_)begin
+ CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
+ CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
+ end
+ if(CsrPlugin_selfException_valid)begin
+ CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code;
+ CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr;
+ end
+ if(_zz_168_)begin
+ CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code);
+ CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr);
+ end
+ if(_zz_183_)begin
+ if(_zz_184_)begin
+ CsrPlugin_interrupt_code <= (4'b0111);
+ CsrPlugin_interrupt_targetPrivilege <= (2'b11);
+ end
+ if(_zz_185_)begin
+ CsrPlugin_interrupt_code <= (4'b0011);
+ CsrPlugin_interrupt_targetPrivilege <= (2'b11);
+ end
+ if(_zz_186_)begin
+ CsrPlugin_interrupt_code <= (4'b1011);
+ CsrPlugin_interrupt_targetPrivilege <= (2'b11);
+ end
+ end
+ if(_zz_169_)begin
+ case(CsrPlugin_targetPrivilege)
+ 2'b11 : begin
+ CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
+ CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
+ CsrPlugin_mepc <= writeBack_PC;
+ if(CsrPlugin_hadException)begin
+ CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
+ end
+ end
+ default : begin
+ end
+ endcase
+ end
+ externalInterruptArray_regNext <= externalInterruptArray;
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SHIFT_CTRL <= _zz_21_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_MMU_FAULT <= execute_MMU_FAULT;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress;
+ execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess;
+ execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead;
+ execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite;
+ execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute;
+ execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception;
+ execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_ALU_CTRL <= _zz_18_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_BRANCH_CTRL <= _zz_15_;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SRC1_CTRL <= _zz_12_;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_ENV_CTRL <= _zz_9_;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_ENV_CTRL <= _zz_6_;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_ENV_CTRL <= _zz_4_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_RS2 <= decode_RS2;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_IS_CSR <= decode_IS_CSR;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_FORMAL_PC_NEXT <= _zz_85_;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_PC <= decode_PC;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_PC <= _zz_39_;
+ end
+ if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
+ memory_to_writeBack_PC <= memory_PC;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
+ end
+ if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin
+ execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SRC2_CTRL <= _zz_2_;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_RS1 <= decode_RS1;
+ end
+ if((! execute_arbitration_isStuck))begin
+ decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
+ end
+ if((! memory_arbitration_isStuck))begin
+ execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
+ end
+ if((! writeBack_arbitration_isStuck))begin
+ memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
+ end
+ case(execute_CsrPlugin_csrAddress)
+ 12'b101111000000 : begin
+ end
+ 12'b001100000000 : begin
+ end
+ 12'b001101000001 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
+ end
+ end
+ 12'b001100000101 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
+ CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
+ end
+ end
+ 12'b001101000100 : begin
+ if(execute_CsrPlugin_writeEnable)begin
+ CsrPlugin_mip_MSIP <= _zz_237_[0];
+ end
+ end
+ 12'b001101000011 : begin
+ end
+ 12'b111111000000 : begin
+ end
+ 12'b001100000100 : begin
+ end
+ 12'b001101000010 : begin
+ end
+ default : begin
+ end
+ endcase
+ if(iBus_cmd_ready)begin
+ _zz_159_ <= iBus_cmd_payload_pc;
+ end
+ if(_zz_187_)begin
+ dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
+ dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
+ dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
+ dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
+ end
+ end
+
+endmodule
+
--- /dev/null
+#!/usr/bin/python3
+from fusesoc.capi2.generator import Generator
+import os
+import sys
+import pathlib
+
+class LiteDRAMGenerator(Generator):
+ def run(self):
+ board = self.config.get('board')
+
+ # Collect a bunch of directory path
+ script_dir = os.path.dirname(sys.argv[0])
+ base_dir = os.path.join(script_dir, os.pardir)
+ gen_dir = os.path.join(base_dir, "generated", board)
+ extras_dir = os.path.join(base_dir, "extras")
+
+ print("Adding LiteDRAM for board... ", board)
+
+ # Grab init-cpu.txt if it exists
+ cpu_file = os.path.join(gen_dir, "init-cpu.txt")
+ if os.path.exists(cpu_file):
+ cpu = pathlib.Path(cpu_file).read_text()
+ else:
+ cpu = None
+
+ # Add files to fusesoc
+ files = []
+ f = os.path.join(gen_dir, "litedram_core.v")
+ files.append({f : {'file_type' : 'verilogSource'}})
+ f = os.path.join(gen_dir, "litedram-wrapper.vhdl")
+ files.append({f : {'file_type' : 'vhdlSource-2008'}})
+ f = os.path.join(gen_dir, "litedram_core.init")
+ files.append({f : {'file_type' : 'user'}})
+
+ # Look for init CPU types and add corresponding files
+ if cpu == "vexriscv":
+ f = os.path.join(base_dir, "extras", "VexRiscv.v")
+ files.append({f : {'file_type' : 'verilogSource'}})
+
+ self.add_files(files)
+
+g = LiteDRAMGenerator()
+g.run()
+g.write()
+
--- /dev/null
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+ # General ------------------------------------------------------------------
+ "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
+ "cpu_variant":"minimal",
+ "speedgrade": -1, # FPGA speedgrade
+ "memtype": "DDR3", # DRAM type
+
+ # PHY ----------------------------------------------------------------------
+ "cmd_delay": 0, # Command additional delay (in taps)
+ "cmd_latency": 0, # Command additional latency
+ "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
+ "sdram_module_nb": 2, # Number of byte groups
+ "sdram_rank_nb": 1, # Number of ranks
+ "sdram_phy": "A7DDRPHY", # Type of FPGA PHY
+
+ # Electrical ---------------------------------------------------------------
+ "rtt_nom": "60ohm", # Nominal termination
+ "rtt_wr": "60ohm", # Write termination
+ "ron": "34ohm", # Output driver impedance
+
+ # Frequency ----------------------------------------------------------------
+ "input_clk_freq": 100e6, # Input clock frequency
+ "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+ "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+ # Core ---------------------------------------------------------------------
+ "cmd_buffer_depth": 16, # Depth of the command buffer
+
+ # User Ports ---------------------------------------------------------------
+ "user_ports": {
+ "native_0": {
+ "type": "native",
+ },
+ },
+
+ # CSR Port -----------------------------------------------------------------
+ "csr_expose": "False", # expose access to CSR (I/O) ports
+ "csr_align" : 32, # CSR alignment
+}
--- /dev/null
+#!/usr/bin/python3
+
+from fusesoc.capi2.generator import Generator
+from litex.build.tools import write_to_file
+from litex.build.tools import replace_in_file
+from litex.build.generic_platform import *
+from litex.build.xilinx import XilinxPlatform
+from litex.build.lattice import LatticePlatform
+from litex.soc.integration.builder import *
+from litedram.gen import *
+import subprocess
+import os
+import sys
+import yaml
+import shutil
+
+def make_new_dir(base, added):
+ r = os.path.join(base, added)
+ if os.path.exists(r):
+ shutil.rmtree(r)
+ os.mkdir(r)
+ return r
+
+gen_src_dir = os.path.dirname(os.path.realpath(__file__))
+base_dir = os.path.join(gen_src_dir, os.pardir)
+build_top_dir = make_new_dir(base_dir, "build")
+gen_src_dir = os.path.join(base_dir, "gen-src")
+gen_dir = make_new_dir(base_dir, "generated")
+
+# Build the init code for microwatt-initialized DRAM
+#
+# XXX Not working yet
+#
+def build_init_code(build_dir):
+
+ # More path fudging
+ sw_dir = os.path.join(build_dir, "software");
+ sw_inc_dir = os.path.join(build_dir, "include")
+ gen_inc_dir = os.path.join(sw_inc_dir, "generated")
+ src_dir = os.path.join(gen_src_dir, "sdram_init")
+ lxbios_src_dir = os.path.join(soc_directory, "software", "bios")
+ lxbios_inc_dir = os.path.join(soc_directory, "software", "include")
+ print(" sw dir:", sw_dir)
+ print("gen_inc_dir:", gen_inc_dir)
+ print(" src dir:", src_dir)
+ print(" lx src dir:", lxbios_src_dir)
+ print(" lx inc dir:", lxbios_inc_dir)
+
+ # Generate mem.h
+ mem_h = "#define MAIN_RAM_BASE 0x40000000"
+ write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h)
+
+ # Environment
+ env_vars = []
+ def _makefile_escape(s): # From LiteX
+ return s.replace("\\", "\\\\")
+ def add_var(k, v):
+ env_vars.append("{}={}\n".format(k, _makefile_escape(v)))
+
+ add_var("BUILD_DIR", sw_dir)
+ add_var("SRC_DIR", src_dir)
+ add_var("GENINC_DIR", gen_inc_dir)
+ add_var("LXSRC_DIR", lxbios_src_dir)
+ add_var("LXINC_DIR", lxbios_inc_dir)
+ write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars))
+
+ # Build init code
+ print(" Generating init software...")
+ makefile = os.path.join(src_dir, "Makefile")
+ r = subprocess.check_call(["make", "-C", build_dir, "-I", gen_inc_dir, "-f", makefile])
+ print("Make result:", r)
+
+ return os.path.join(sw_dir, "obj", "sdram_init.hex")
+
+def generate_one(t):
+
+ print("Generating target:", t)
+
+ # Muck with directory path
+ build_dir = make_new_dir(build_top_dir, t)
+ t_dir = make_new_dir(gen_dir, t)
+
+ # Grab config file
+ cfile = os.path.join(gen_src_dir, t + ".yml")
+ core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader)
+
+ ### TODO: Make most stuff below a function in litedram gen.py and
+ ### call it rather than duplicate it
+ ###
+
+ # Convert YAML elements to Python/LiteX
+ for k, v in core_config.items():
+ replaces = {"False": False, "True": True, "None": None}
+ for r in replaces.keys():
+ if v == r:
+ core_config[k] = replaces[r]
+ if "clk_freq" in k:
+ core_config[k] = float(core_config[k])
+ if k == "sdram_module":
+ core_config[k] = getattr(litedram_modules, core_config[k])
+ if k == "sdram_phy":
+ core_config[k] = getattr(litedram_phys, core_config[k])
+
+ # Generate core
+ if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
+ platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis")
+ elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
+ platform = XilinxPlatform("", io=[], toolchain="vivado")
+ else:
+ raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
+
+ soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
+
+ # Build into build_dir
+ builder = Builder(soc, output_dir=build_dir, compile_gateware=False)
+ vns = builder.build(build_name="litedram_core", regular_comb=False)
+
+ # Grab generated gatewar dir
+ gw_dir = os.path.join(build_dir, "gateware")
+
+ # Generate init-cpu.txt if any and generate init code if none
+ cpu = core_config["cpu"]
+ if cpu is None:
+ print("Microwatt based inits not supported yet !")
+ src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
+ src_init_file = build_init_code(build_dir)
+ else:
+ write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
+ src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl")
+ src_init_file = os.path.join(gw_dir, "mem.init")
+
+ # Copy generated files to target dir, amend them if necessary
+ core_file = os.path.join(gw_dir, "litedram_core.v")
+ dst_init_file = os.path.join(t_dir, "litedram_core.init")
+ dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl")
+ replace_in_file(core_file, "mem.init", "litedram_core.init")
+ shutil.copy(core_file, t_dir)
+ shutil.copyfile(src_init_file, dst_init_file)
+ shutil.copyfile(src_wrap_file, dst_wrap_file)
+
+def main():
+
+ targets = ['arty','nexys-video']
+ for t in targets:
+ generate_one(t)
+
+ # XXX TODO: Remove build dir unless told not to via cmdline option
+
+if __name__ == "__main__":
+ main()
--- /dev/null
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+ # General ------------------------------------------------------------------
+ "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
+ "cpu_variant":"minimal",
+ "speedgrade": -1, # FPGA speedgrade
+ "memtype": "DDR3", # DRAM type
+
+ # PHY ----------------------------------------------------------------------
+ "cmd_delay": 0, # Command additional delay (in taps)
+ "cmd_latency": 0, # Command additional latency
+ "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
+ "sdram_module_nb": 2, # Number of byte groups
+ "sdram_rank_nb": 1, # Number of ranks
+ "sdram_phy": "A7DDRPHY", # Type of FPGA PHY
+
+ # Electrical ---------------------------------------------------------------
+ "rtt_nom": "60ohm", # Nominal termination
+ "rtt_wr": "60ohm", # Write termination
+ "ron": "34ohm", # Output driver impedance
+
+ # Frequency ----------------------------------------------------------------
+ "input_clk_freq": 100e6, # Input clock frequency
+ "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+ "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+ # Core ---------------------------------------------------------------------
+ "cmd_buffer_depth": 16, # Depth of the command buffer
+
+ # User Ports ---------------------------------------------------------------
+ "user_ports": {
+ "native_0": {
+ "type": "native",
+ },
+ },
+
+ # CSR Port -----------------------------------------------------------------
+ "csr_expose": "False", # expose access to CSR (I/O) ports
+ "csr_align" : 32, # 64-bit alignment
+}
--- /dev/null
+#### Directories
+
+include variables.mak
+OBJ = $(BUILD_DIR)/obj
+
+PROGRAM = sdram_init
+OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o
+
+#### Compiler
+
+ARCH = $(shell uname -m)
+ifneq ("$(ARCH)", "ppc64")
+ifneq ("$(ARCH)", "ppc64le")
+ CROSS_COMPILE = powerpc64le-linux-gnu-
+ endif
+ endif
+
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+OBJCOPY = $(CROSS_COMPILE)objcopy
+
+#### Flags
+
+CPPFLAGS = -nostdinc
+CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include
+CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
+CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks
+ASFLAGS = $(CPPFLAGS) $(CFLAGS)
+LDFLAGS = -static -nostdlib -Ttext-segment=0xffff0000 -T $(SRC_DIR)/$(PROGRAM).lds --gc-sections
+
+#### Pretty print
+
+ifeq ($(VERBOSE),1)
+define Q
+ $(2)
+endef
+else
+define Q
+ @echo " [$1] $(3)"
+ @$(2)
+endef
+endif
+
+#### Rules. This is a bit crappy, I'm sure we can do better with the
+#### handling of the various path, but this will have to do
+#### until I can be bothered getting my head around the finer
+#### points of Makefiles
+
+all: objdir $(OBJ)/$(PROGRAM).hex
+
+$(OBJ)/sdram.o: $(LXSRC_DIR)/sdram.c
+ $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
+$(OBJ)/%.o : $(SRC_DIR)/%.S
+ $(call Q,AS, $(CC) $(ASFLAGS) -c $< -o $@, $@)
+$(OBJ)/%.o : $(SRC_DIR)/%.c
+ $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
+$(OBJ)/%.o : $(SRC_DIR)/libc/src/%.c
+ $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
+
+LIBC_SRC := $(wildcard $(SRC_DIR)/libc/src/*.c)
+LIBC_OBJ := $(patsubst $(SRC_DIR)/libc/src/%.c, $(OBJ)/%.o,$(LIBC_SRC))
+$(OBJ)/libc.o: $(LIBC_OBJ)
+ $(call Q,LD, $(LD) -r -o $@ $^, $@)
+
+$(OBJ)/$(PROGRAM).elf: $(OBJECTS) $(OBJ)/libc.o
+ $(call Q,LD, $(LD) $(LDFLAGS) -o $@ $^, $@)
+
+$(OBJ)/$(PROGRAM).bin: $(OBJ)/$(PROGRAM).elf
+ $(call Q,OC, $(OBJCOPY) -O binary -S $^ $@, $@)
+
+$(OBJ)/$(PROGRAM).hex: $(OBJ)/$(PROGRAM).bin
+ $(call Q,HX, $(SRC_DIR)/bin2hex.py $^ > $@, $@)
+
+objdir:
+ @mkdir -p $(OBJ)
--- /dev/null
+#!/usr/bin/python3
+
+import sys
+import subprocess
+import struct
+
+with open(sys.argv[1], "rb") as f:
+ while True:
+ word = f.read(8)
+ if len(word) == 8:
+ print("%016x" % struct.unpack('Q', word));
+ elif len(word) == 4:
+ print("00000000%08x" % struct.unpack('I', word));
+ elif len(word) == 0:
+ exit(0);
+ else:
+ raise Exception("Bad length")
--- /dev/null
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define STACK_TOP 0xffff4000
+
+#define FIXUP_ENDIAN \
+ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
+ b 191f; /* Skip trampoline if endian is good */ \
+ .long 0xa600607d; /* mfmsr r11 */ \
+ .long 0x01006b69; /* xori r11,r11,1 */ \
+ .long 0x05009f42; /* bcl 20,31,$+4 */ \
+ .long 0xa602487d; /* mflr r10 */ \
+ .long 0x14004a39; /* addi r10,r10,20 */ \
+ .long 0xa64b5a7d; /* mthsrr0 r10 */ \
+ .long 0xa64b7b7d; /* mthsrr1 r11 */ \
+ .long 0x2402004c; /* hrfid */ \
+191:
+
+
+/* Load an immediate 64-bit value into a register */
+#define LOAD_IMM64(r, e) \
+ lis r,(e)@highest; \
+ ori r,r,(e)@higher; \
+ rldicr r,r, 32, 31; \
+ oris r,r, (e)@h; \
+ ori r,r, (e)@l;
+
+ .section ".head","ax"
+
+ . = 0
+.global start
+start:
+ FIXUP_ENDIAN
+
+ /* setup stack */
+ LOAD_IMM64(%r1, STACK_TOP - 0x100)
+ LOAD_IMM64(%r12, main)
+ mtctr %r12,
+ bctrl
+ ba 0
+
+ /* XXX: litedram init should not take exceptions, maybe we could get
+ * rid of these to save space, along with a core tweak to suppress
+ * exceptions in case they happen (just terminate ?)
+ */
+
+#define EXCEPTION(nr) \
+ .= nr; \
+ b .
+
+ /* More exception stubs */
+ EXCEPTION(0x100)
+ EXCEPTION(0x200)
+ EXCEPTION(0x300)
+ EXCEPTION(0x380)
+ EXCEPTION(0x400)
+ EXCEPTION(0x480)
+ EXCEPTION(0x500)
+ EXCEPTION(0x600)
+ EXCEPTION(0x700)
+ EXCEPTION(0x800)
+ EXCEPTION(0x900)
+ EXCEPTION(0x980)
+ EXCEPTION(0xa00)
+ EXCEPTION(0xb00)
+ EXCEPTION(0xc00)
+ EXCEPTION(0xd00)
+ EXCEPTION(0xe00)
+ EXCEPTION(0xe20)
+ EXCEPTION(0xe40)
+ EXCEPTION(0xe60)
+ EXCEPTION(0xe80)
+ EXCEPTION(0xf00)
+ EXCEPTION(0xf20)
+ EXCEPTION(0xf40)
+ EXCEPTION(0xf60)
+ EXCEPTION(0xf80)
+#if 0
+ EXCEPTION(0x1000)
+ EXCEPTION(0x1100)
+ EXCEPTION(0x1200)
+ EXCEPTION(0x1300)
+ EXCEPTION(0x1400)
+ EXCEPTION(0x1500)
+ EXCEPTION(0x1600)
+#endif
+
+ .text
+
--- /dev/null
+static inline void flush_cpu_dcache(void) { }
+static inline void flush_l2_cache(void) { }
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008, 2012 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _ASSERT_H
+#define _ASSERT_H
+
+#define assert(cond) \
+ do { if (!(cond)) { \
+ assert_fail(__FILE__ \
+ ":" stringify(__LINE__) \
+ ":" stringify(cond)); } \
+ } while(0)
+
+void __attribute__((noreturn)) assert_fail(const char *msg);
+
+#define stringify(expr) stringify_1(expr)
+/* Double-indirection required to stringify expansions */
+#define stringify_1(expr) #expr
+
+#endif
--- /dev/null
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __COMPILER_H
+#define __COMPILER_H
+
+#ifndef __ASSEMBLY__
+
+#include <stddef.h>
+
+/* Macros for various compiler bits and pieces */
+#define __packed __attribute__((packed))
+#define __align(x) __attribute__((__aligned__(x)))
+#define __unused __attribute__((unused))
+#define __used __attribute__((used))
+#define __section(x) __attribute__((__section__(x)))
+#define __noreturn __attribute__((noreturn))
+/* not __const as this has a different meaning (const) */
+#define __attrconst __attribute__((const))
+#define __warn_unused_result __attribute__((warn_unused_result))
+#define __noinline __attribute__((noinline))
+
+#if 0 /* Provided by gcc stddef.h */
+#define offsetof(type,m) __builtin_offsetof(type,m)
+#endif
+
+#define __nomcount __attribute__((no_instrument_function))
+
+/* Compiler barrier */
+static inline void barrier(void)
+{
+// asm volatile("" : : : "memory");
+}
+
+#endif /* __ASSEMBLY__ */
+
+/* Stringification macro */
+#define __tostr(x) #x
+#define tostr(x) __tostr(x)
+
+#endif /* __COMPILER_H */
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _CTYPE_H
+#define _CTYPE_H
+
+#include <compiler.h>
+
+int __attrconst isdigit(int c);
+int __attrconst isxdigit(int c);
+int __attrconst isprint(int c);
+int __attrconst isspace(int c);
+
+int __attrconst tolower(int c);
+int __attrconst toupper(int c);
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _ERRNO_H
+#define _ERRNO_H
+
+extern int errno;
+
+/*
+ * Error number definitions
+ */
+#define EPERM 1 /* not permitted */
+#define ENOENT 2 /* file or directory not found */
+#define EIO 5 /* input/output error */
+#define EBADF 9 /* Bad file number */
+#define ENOMEM 12 /* not enough space */
+#define EACCES 13 /* permission denied */
+#define EFAULT 14 /* bad address */
+#define EBUSY 16 /* resource busy */
+#define EEXIST 17 /* file already exists */
+#define ENODEV 19 /* device not found */
+#define EINVAL 22 /* invalid argument */
+#define EDOM 33 /* math argument out of domain of func */
+#define ERANGE 34 /* math result not representable */
+#define ENOSYS 38 /* Function not implemented */
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _STDINT_H
+#define _STDINT_H
+
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
+
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
+
+typedef unsigned long long uint64_t;
+typedef signed long long int64_t;
+
+typedef unsigned long int uintptr_t;
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _STDIO_H
+#define _STDIO_H
+
+#include <stdarg.h>
+#include "stddef.h"
+
+#define EOF (-1)
+
+int _printf(const char *format, ...) __attribute__((format (printf, 1, 2)));
+
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+#define printf(f, ...) do { _printf(pr_fmt(f), ##__VA_ARGS__); } while(0)
+
+int snprintf(char *str, size_t size, const char *format, ...) __attribute__((format (printf, 3, 4)));
+int vsnprintf(char *str, size_t size, const char *format, va_list);
+
+int putchar(int ch);
+int puts(const char *str);
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _STDLIB_H
+#define _STDLIB_H
+
+#include "stddef.h"
+
+#define RAND_MAX 32767
+
+int atoi(const char *str);
+long atol(const char *str);
+unsigned long int strtoul(const char *nptr, char **endptr, int base);
+long int strtol(const char *nptr, char **endptr, int base);
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2016 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _STRING_H
+#define _STRING_H
+
+#include "stddef.h"
+
+char *strcpy(char *dest, const char *src);
+char *strncpy(char *dest, const char *src, size_t n);
+char *strcat(char *dest, const char *src);
+int strcmp(const char *s1, const char *s2);
+int strncmp(const char *s1, const char *s2, size_t n);
+int strcasecmp(const char *s1, const char *s2);
+int strncasecmp(const char *s1, const char *s2, size_t n);
+char *strchr(const char *s, int c);
+char *strrchr(const char *s, int c);
+size_t strlen(const char *s);
+size_t strnlen(const char *s, size_t n);
+char *strstr(const char *hay, const char *needle);
+char *strtok(char *src, const char *pattern);
+char *strdup(const char *src);
+
+void *memset(void *s, int c, size_t n);
+void *memchr(const void *s, int c, size_t n);
+void *memcpy(void *dest, const void *src, size_t n);
+void *memcpy_from_ci(void *destpp, const void *srcpp, size_t len);
+void *memmove(void *dest, const void *src, size_t n);
+int memcmp(const void *s1, const void *s2, size_t n);
+
+static inline int ffs(unsigned long val)
+{
+ return __builtin_ffs(val);
+}
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _UNISTD_H
+#define _UNISTD_H
+
+#include <stddef.h>
+
+typedef long ssize_t;
+
+extern int open(const char *name, int flags);
+extern int close(int fd);
+extern ssize_t read(int fd, void *buf, size_t count);
+extern ssize_t write(int fd, const void *buf, size_t count);
+extern ssize_t lseek(int fd, long offset, int whence);
+
+#endif
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include <ctype.h>
+
+int __attrconst isdigit(int ch)
+{
+ switch (ch) {
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ return 1;
+
+ default:
+ return 0;
+ }
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include <ctype.h>
+
+int __attrconst isprint(int ch)
+{
+ return (ch >= 32 && ch < 127);
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include <ctype.h>
+
+int __attrconst isspace(int ch)
+{
+ switch (ch) {
+ case ' ':
+ case '\f':
+ case '\n':
+ case '\r':
+ case '\t':
+ case '\v':
+ return 1;
+
+ default:
+ return 0;
+ }
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include <ctype.h>
+
+int __attrconst isxdigit(int ch)
+{
+ return (
+ (ch >= '0' && ch <= '9') |
+ (ch >= 'A' && ch <= 'F') |
+ (ch >= 'a' && ch <= 'f') );
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+void *memchr(const void *ptr, int c, size_t n);
+void *memchr(const void *ptr, int c, size_t n)
+{
+ unsigned char ch = (unsigned char)c;
+ const unsigned char *p = ptr;
+
+ while (n-- > 0) {
+ if (*p == ch)
+ return (void *)p;
+ p += 1;
+ }
+
+ return NULL;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+int memcmp(const void *ptr1, const void *ptr2, size_t n);
+int memcmp(const void *ptr1, const void *ptr2, size_t n)
+{
+ const unsigned char *p1 = ptr1;
+ const unsigned char *p2 = ptr2;
+
+ while (n-- > 0) {
+ if (*p1 != *p2)
+ return (*p1 - *p2);
+ p1 += 1;
+ p2 += 1;
+ }
+
+ return 0;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+#include <stdint.h>
+
+void *memcpy(void *dest, const void *src, size_t n);
+void *memcpy(void *dest, const void *src, size_t n)
+{
+ void *ret = dest;
+
+ while (n >= 8) {
+ *(uint64_t *)dest = *(uint64_t *)src;
+ dest += 8;
+ src += 8;
+ n -= 8;
+ }
+
+ while (n > 0) {
+ *(uint8_t *)dest = *(uint8_t *)src;
+ dest += 1;
+ src += 1;
+ n -= 1;
+ }
+
+ return ret;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+void *memcpy(void *dest, const void *src, size_t n);
+void *memmove(void *dest, const void *src, size_t n);
+void *memmove(void *dest, const void *src, size_t n)
+{
+ /* Do the buffers overlap in a bad way? */
+ if (src < dest && src + n >= dest) {
+ char *cdest;
+ const char *csrc;
+ int i;
+
+ /* Copy from end to start */
+ cdest = dest + n - 1;
+ csrc = src + n - 1;
+ for (i = 0; i < n; i++) {
+ *cdest-- = *csrc--;
+ }
+ return dest;
+ } else {
+ /* Normal copy is possible */
+ return memcpy(dest, src, n);
+ }
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#define CACHE_LINE_SIZE 128
+
+#include <stddef.h>
+
+void *memset(void *dest, int c, size_t size);
+void *memset(void *dest, int c, size_t size)
+{
+ unsigned char *d = (unsigned char *)dest;
+ unsigned long big_c = 0;
+
+ if (c) {
+ big_c = c;
+ big_c |= (big_c << 8) | big_c;
+ big_c |= (big_c << 16) | big_c;
+ big_c |= (big_c << 32) | big_c;
+ }
+ while (size >= 8 && c == 0) {
+ *((unsigned long *)d) = big_c;
+ d+=8;
+ size-=8;
+ }
+
+ while (size-- > 0) {
+ *d++ = (unsigned char)c;
+ }
+
+ return dest;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <ctype.h>
+
+int strcasecmp(const char *s1, const char *s2);
+int strcasecmp(const char *s1, const char *s2)
+{
+ while (*s1 != 0 && *s2 != 0) {
+ if (toupper(*s1) != toupper(*s2))
+ break;
+ ++s1;
+ ++s2;
+ }
+
+ return *s1 - *s2;
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+size_t strlen(const char *s);
+char *strcpy(char *dst, const char *src);
+char *strcat(char *dst, const char *src);
+char *strcat(char *dst, const char *src)
+{
+ size_t p;
+
+ p = strlen(dst);
+ strcpy(&dst[p], src);
+
+ return dst;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+char *strchr(const char *s, int c);
+char *strchr(const char *s, int c)
+{
+ char cb = c;
+
+ while (*s != 0) {
+ if (*s == cb) {
+ return (char *)s;
+ }
+ s += 1;
+ }
+
+ return NULL;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+int strcmp(const char *s1, const char *s2);
+int strcmp(const char *s1, const char *s2)
+{
+ while (*s1 != 0 && *s2 != 0) {
+ if (*s1 != *s2)
+ break;
+ s1 += 1;
+ s2 += 1;
+ }
+
+ return *s1 - *s2;
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+char *strcpy(char *dst, const char *src);
+char *strcpy(char *dst, const char *src)
+{
+ char *ptr = dst;
+
+ do {
+ *ptr++ = *src;
+ } while (*src++ != 0);
+
+ return dst;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+size_t strlen(const char *s);
+size_t strlen(const char *s)
+{
+ size_t len = 0;
+
+ while (*s != 0) {
+ len += 1;
+ s += 1;
+ }
+
+ return len;
+}
+
+size_t strnlen(const char *s, size_t n);
+size_t strnlen(const char *s, size_t n)
+{
+ size_t len = 0;
+
+ while (*s != 0 && n) {
+ len += 1;
+ s += 1;
+ n--;
+ }
+
+ return len;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <ctype.h>
+
+int strncasecmp(const char *s1, const char *s2, size_t n);
+int strncasecmp(const char *s1, const char *s2, size_t n)
+{
+ if (n < 1)
+ return 0;
+
+ while (*s1 != 0 && *s2 != 0 && --n > 0) {
+ if (toupper(*s1) != toupper(*s2))
+ break;
+ ++s1;
+ ++s2;
+ }
+
+ return toupper(*s1) - toupper(*s2);
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+int strncmp(const char *s1, const char *s2, size_t n);
+int strncmp(const char *s1, const char *s2, size_t n)
+{
+ if (n < 1)
+ return 0;
+
+ while (*s1 != 0 && *s2 != 0 && --n > 0) {
+ if (*s1 != *s2)
+ break;
+ s1 += 1;
+ s2 += 1;
+ }
+
+ return *s1 - *s2;
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+char *strncpy(char *dst, const char *src, size_t n);
+char *strncpy(char *dst, const char *src, size_t n)
+{
+ char *ret = dst;
+
+ /* Copy string */
+ while (*src != 0 && n > 0) {
+ *dst++ = *src++;
+ n -= 1;
+ }
+
+ /* strncpy always clears the rest of destination string... */
+ while (n > 0) {
+ *dst++ = 0;
+ n -= 1;
+ }
+
+ return ret;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008, 2019 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+char *strrchr(const char *s, int c);
+char *strrchr(const char *s, int c)
+{
+ char *last = NULL;
+ char cb = c;
+
+ while (*s != 0) {
+ if (*s == cb)
+ last = (char *)s;
+ s += 1;
+ }
+
+ return last;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+size_t strlen(const char *s);
+int strncmp(const char *s1, const char *s2, size_t n);
+char *strstr(const char *hay, const char *needle);
+char *strstr(const char *hay, const char *needle)
+{
+ char *pos;
+ size_t hlen, nlen;
+
+ if (hay == NULL || needle == NULL)
+ return NULL;
+
+ hlen = strlen(hay);
+ nlen = strlen(needle);
+ if (nlen < 1)
+ return (char *)hay;
+
+ for (pos = (char *)hay; pos < hay + hlen; pos++) {
+ if (strncmp(pos, needle, nlen) == 0) {
+ return pos;
+ }
+ }
+
+ return NULL;
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stddef.h>
+
+char *strtok(char *src, const char *pattern);
+char *strtok(char *src, const char *pattern)
+{
+ static char *nxtTok;
+ char *retVal = NULL;
+
+ if (!src) {
+ src = nxtTok;
+ if (!src)
+ return retVal;
+ }
+
+ while (*src) {
+ const char *pp = pattern;
+ while (*pp) {
+ if (*pp == *src) {
+ break;
+ }
+ pp++;
+ }
+ if (!*pp) {
+ if (!retVal)
+ retVal = src;
+ else if (!src[-1])
+ break;
+ } else
+ *src = '\0';
+ src++;
+ }
+
+ nxtTok = src;
+
+ return retVal;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stdlib.h>
+
+long int strtol(const char *S, char **PTR,int BASE)
+{
+ long rval = 0;
+ short int negative = 0;
+ short int digit;
+ // *PTR is S, unless PTR is NULL, in which case i override it with my own ptr
+ char* ptr;
+ if (PTR == NULL)
+ {
+ //override
+ PTR = &ptr;
+ }
+ // i use PTR to advance through the string
+ *PTR = (char *) S;
+ //check if BASE is ok
+ if ((BASE < 0) || BASE > 36)
+ {
+ return 0;
+ }
+ // ignore white space at beginning of S
+ while ((**PTR == ' ')
+ || (**PTR == '\t')
+ || (**PTR == '\n')
+ || (**PTR == '\r')
+ )
+ {
+ (*PTR)++;
+ }
+ // check if S starts with "-" in which case the return value is negative
+ if (**PTR == '-')
+ {
+ negative = 1;
+ (*PTR)++;
+ }
+ // if BASE is 0... determine the base from the first chars...
+ if (BASE == 0)
+ {
+ // if S starts with "0x", BASE = 16, else 10
+ if ((**PTR == '0') && (*((*PTR)+1) == 'x'))
+ {
+ BASE = 16;
+ }
+ else
+ {
+ BASE = 10;
+ }
+ }
+ if (BASE == 16)
+ {
+ // S may start with "0x"
+ if ((**PTR == '0') && (*((*PTR)+1) == 'x'))
+ {
+ (*PTR)++;
+ (*PTR)++;
+ }
+ }
+ //until end of string
+ while (**PTR)
+ {
+ if (((**PTR) >= '0') && ((**PTR) <= '9'))
+ {
+ //digit (0..9)
+ digit = **PTR - '0';
+ }
+ else if (((**PTR) >= 'a') && ((**PTR) <='z'))
+ {
+ //alphanumeric digit lowercase(a (10) .. z (35) )
+ digit = (**PTR - 'a') + 10;
+ }
+ else if (((**PTR) >= 'A') && ((**PTR) <='Z'))
+ {
+ //alphanumeric digit uppercase(a (10) .. z (35) )
+ digit = (**PTR - 'A') + 10;
+ }
+ else
+ {
+ //end of parseable number reached...
+ break;
+ }
+ if (digit < BASE)
+ {
+ rval = (rval * BASE) + digit;
+ }
+ else
+ {
+ //digit found, but its too big for current base
+ //end of parseable number reached...
+ break;
+ }
+ //next...
+ (*PTR)++;
+ }
+ if (negative)
+ {
+ return rval * -1;
+ }
+ //else
+ return rval;
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stdlib.h>
+
+unsigned long int strtoul(const char *S, char **PTR,int BASE)
+{
+ unsigned long rval = 0;
+ short int digit;
+ // *PTR is S, unless PTR is NULL, in which case i override it with my own ptr
+ char* ptr;
+ if (PTR == NULL)
+ {
+ //override
+ PTR = &ptr;
+ }
+ // i use PTR to advance through the string
+ *PTR = (char *) S;
+ //check if BASE is ok
+ if ((BASE < 0) || BASE > 36)
+ {
+ return 0;
+ }
+ // ignore white space at beginning of S
+ while ((**PTR == ' ')
+ || (**PTR == '\t')
+ || (**PTR == '\n')
+ || (**PTR == '\r')
+ )
+ {
+ (*PTR)++;
+ }
+ // if BASE is 0... determine the base from the first chars...
+ if (BASE == 0)
+ {
+ // if S starts with "0x", BASE = 16, else 10
+ if ((**PTR == '0') && (*((*PTR)+1) == 'x'))
+ {
+ BASE = 16;
+ }
+ else
+ {
+ BASE = 10;
+ }
+ }
+ if (BASE == 16)
+ {
+ // S may start with "0x"
+ if ((**PTR == '0') && (*((*PTR)+1) == 'x'))
+ {
+ (*PTR)++;
+ (*PTR)++;
+ }
+ }
+ //until end of string
+ while (**PTR)
+ {
+ if (((**PTR) >= '0') && ((**PTR) <='9'))
+ {
+ //digit (0..9)
+ digit = **PTR - '0';
+ }
+ else if (((**PTR) >= 'a') && ((**PTR) <='z'))
+ {
+ //alphanumeric digit lowercase(a (10) .. z (35) )
+ digit = (**PTR - 'a') + 10;
+ }
+ else if (((**PTR) >= 'A') && ((**PTR) <='Z'))
+ {
+ //alphanumeric digit uppercase(a (10) .. z (35) )
+ digit = (**PTR - 'A') + 10;
+ }
+ else
+ {
+ //end of parseable number reached...
+ break;
+ }
+ if (digit < BASE)
+ {
+ rval = (rval * BASE) + digit;
+ }
+ else
+ {
+ //digit found, but its too big for current base
+ //end of parseable number reached...
+ break;
+ }
+ //next...
+ (*PTR)++;
+ }
+ //done
+ return rval;
+}
+
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include <ctype.h>
+
+int __attrconst tolower(int c)
+{
+ return (((c >= 'A') && (c <= 'Z')) ? (c - 'A' + 'a' ) : c);
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <compiler.h>
+#include "ctype.h"
+
+int __attrconst toupper (int cha)
+{
+ if((cha >= 'a') && (cha <= 'z'))
+ return(cha - 'a' + 'A');
+ return(cha);
+}
--- /dev/null
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#include <stdbool.h>
+#include <compiler.h>
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+#include "ctype.h"
+#include <stdarg.h>
+
+static const unsigned long long convert[] = {
+ 0x0, 0xFF, 0xFFFF, 0xFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFFFFULL, 0xFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL
+};
+
+static int
+print_str_fill(char **buffer, size_t bufsize, char *sizec,
+ const char *str, char c)
+{
+ size_t i, sizei, len;
+ char *bstart = *buffer;
+
+ sizei = strtoul(sizec, NULL, 10);
+ len = strlen(str);
+ if (sizei > len) {
+ for (i = 0;
+ (i < (sizei - len)) && ((*buffer - bstart) < bufsize);
+ i++) {
+ **buffer = c;
+ *buffer += 1;
+ }
+ }
+ return 1;
+}
+
+static int
+print_str(char **buffer, size_t bufsize, const char *str)
+{
+ char *bstart = *buffer;
+ size_t i;
+
+ for (i = 0; (i < strlen(str)) && ((*buffer - bstart) < bufsize); i++) {
+ **buffer = str[i];
+ *buffer += 1;
+ }
+ return 1;
+}
+
+static unsigned int __attrconst
+print_intlen(unsigned long value, unsigned short int base)
+{
+ int i = 0;
+
+ while (value > 0) {
+ if (base == 16)
+ value >>= 4;
+ else
+ value /= base;
+ i++;
+ }
+ if (i == 0)
+ i = 1;
+ return i;
+}
+
+static int
+print_itoa(char **buffer, size_t bufsize, unsigned long value,
+ unsigned short base, bool upper)
+{
+ const char zeichen[] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'};
+ char c;
+ int i, len;
+
+ if(base <= 2 || base > 16)
+ return 0;
+
+ len = i = print_intlen(value, base);
+
+ /* Don't print to buffer if bufsize is not enough. */
+ if (len > bufsize)
+ return 0;
+
+ do {
+ c = zeichen[value % base];
+ if (upper)
+ c = toupper(c);
+
+ (*buffer)[--i] = c;
+ value /= base;
+ } while(value);
+
+ *buffer += len;
+
+ return 1;
+}
+
+
+
+static int
+print_fill(char **buffer, size_t bufsize, char *sizec, unsigned long size,
+ unsigned short int base, char c, int optlen)
+{
+ int i, sizei, len;
+ char *bstart = *buffer;
+
+ sizei = strtoul(sizec, NULL, 10);
+ len = print_intlen(size, base) + optlen;
+ if (sizei > len) {
+ for (i = 0;
+ (i < (sizei - len)) && ((*buffer - bstart) < bufsize);
+ i++) {
+ **buffer = c;
+ *buffer += 1;
+ }
+ }
+
+ return 0;
+}
+
+
+static int
+print_format(char **buffer, size_t bufsize, const char *format, void *var)
+{
+ char *start;
+ unsigned int i = 0, length_mod = sizeof(int);
+ unsigned long value = 0;
+ unsigned long signBit;
+ char *form, sizec[32];
+ char sign = ' ';
+ bool upper = false;
+
+ form = (char *) format;
+ start = *buffer;
+
+ form++;
+ if(*form == '0' || *form == '.') {
+ sign = '0';
+ form++;
+ }
+
+ while ((*form != '\0') && ((*buffer - start) < bufsize)) {
+ switch(*form) {
+ case 'u':
+ case 'd':
+ case 'i':
+ sizec[i] = '\0';
+ value = (unsigned long) var;
+ signBit = 0x1ULL << (length_mod * 8 - 1);
+ if ((*form != 'u') && (signBit & value)) {
+ **buffer = '-';
+ *buffer += 1;
+ value = (-(unsigned long)value) & convert[length_mod];
+ }
+ print_fill(buffer, bufsize - (*buffer - start),
+ sizec, value, 10, sign, 0);
+ print_itoa(buffer, bufsize - (*buffer - start),
+ value, 10, upper);
+ break;
+ case 'X':
+ upper = true;
+ /* fallthrough */
+ case 'x':
+ sizec[i] = '\0';
+ value = (unsigned long) var & convert[length_mod];
+ print_fill(buffer, bufsize - (*buffer - start),
+ sizec, value, 16, sign, 0);
+ print_itoa(buffer, bufsize - (*buffer - start),
+ value, 16, upper);
+ break;
+ case 'O':
+ case 'o':
+ sizec[i] = '\0';
+ value = (long int) var & convert[length_mod];
+ print_fill(buffer, bufsize - (*buffer - start),
+ sizec, value, 8, sign, 0);
+ print_itoa(buffer, bufsize - (*buffer - start),
+ value, 8, upper);
+ break;
+ case 'p':
+ sizec[i] = '\0';
+ print_fill(buffer, bufsize - (*buffer - start),
+ sizec, (unsigned long) var, 16, ' ', 2);
+ print_str(buffer, bufsize - (*buffer - start),
+ "0x");
+ print_itoa(buffer, bufsize - (*buffer - start),
+ (unsigned long) var, 16, upper);
+ break;
+ case 'c':
+ sizec[i] = '\0';
+ print_fill(buffer, bufsize - (*buffer - start),
+ sizec, 1, 10, ' ', 0);
+ **buffer = (unsigned long) var;
+ *buffer += 1;
+ break;
+ case 's':
+ sizec[i] = '\0';
+ print_str_fill(buffer,
+ bufsize - (*buffer - start), sizec,
+ (char *) var, ' ');
+
+ print_str(buffer, bufsize - (*buffer - start),
+ (char *) var);
+ break;
+ case 'l':
+ form++;
+ if(*form == 'l') {
+ length_mod = sizeof(long long int);
+ } else {
+ form--;
+ length_mod = sizeof(long int);
+ }
+ break;
+ case 'h':
+ form++;
+ if(*form == 'h') {
+ length_mod = sizeof(signed char);
+ } else {
+ form--;
+ length_mod = sizeof(short int);
+ }
+ break;
+ case 'z':
+ length_mod = sizeof(size_t);
+ break;
+ default:
+ if(*form >= '0' && *form <= '9')
+ sizec[i++] = *form;
+ }
+ form++;
+ }
+
+
+ return (long int) (*buffer - start);
+}
+
+
+/*
+ * The vsnprintf function prints a formatted strings into a buffer.
+ * BUG: buffer size checking does not fully work yet
+ */
+int
+vsnprintf(char *buffer, size_t bufsize, const char *format, va_list arg)
+{
+ char *ptr, *bstart;
+
+ bstart = buffer;
+ ptr = (char *) format;
+
+ /*
+ * Return from here if size passed is zero, otherwise we would
+ * overrun buffer while setting NULL character at the end.
+ */
+ if (!buffer || !bufsize)
+ return 0;
+
+ /* Leave one space for NULL character */
+ bufsize--;
+
+ while(*ptr != '\0' && (buffer - bstart) < bufsize)
+ {
+ if(*ptr == '%') {
+ char formstr[20];
+ int i=0;
+
+ do {
+ formstr[i] = *ptr;
+ ptr++;
+ i++;
+ } while(!(*ptr == 'd' || *ptr == 'i' || *ptr == 'u' || *ptr == 'x' || *ptr == 'X'
+ || *ptr == 'p' || *ptr == 'c' || *ptr == 's' || *ptr == '%'
+ || *ptr == 'O' || *ptr == 'o' ));
+ formstr[i++] = *ptr;
+ formstr[i] = '\0';
+ if(*ptr == '%') {
+ *buffer++ = '%';
+ } else {
+ print_format(&buffer,
+ bufsize - (buffer - bstart),
+ formstr, va_arg(arg, void *));
+ }
+ ptr++;
+ } else {
+
+ *buffer = *ptr;
+
+ buffer++;
+ ptr++;
+ }
+ }
+
+ *buffer = '\0';
+
+ return (buffer - bstart);
+}
--- /dev/null
+#include <unistd.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdarg.h>
+#include <stdio.h>
+
+#include "sdram.h"
+
+/*
+ * Core UART functions to implement for a port
+ */
+
+static uint64_t potato_uart_base;
+
+#define PROC_FREQ 100000000
+#define UART_FREQ 115200
+#define UART_BASE 0xc0002000
+#define SYSCON_BASE 0xc0000000
+
+#define POTATO_CONSOLE_TX 0x00
+#define POTATO_CONSOLE_RX 0x08
+#define POTATO_CONSOLE_STATUS 0x10
+#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01
+#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02
+#define POTATO_CONSOLE_STATUS_RX_FULL 0x04
+#define POTATO_CONSOLE_STATUS_TX_FULL 0x08
+#define POTATO_CONSOLE_CLOCK_DIV 0x18
+#define POTATO_CONSOLE_IRQ_EN 0x20
+
+static inline uint8_t readb(unsigned long addr)
+{
+ __asm__ volatile("sync" : : : "memory");
+ return *((volatile uint8_t *)addr);
+}
+
+static inline uint64_t readq(unsigned long addr)
+{
+ __asm__ volatile("sync" : : : "memory");
+ return *((volatile uint64_t *)addr);
+}
+
+static inline void writeb(uint8_t val, unsigned long addr)
+{
+ __asm__ volatile("sync" : : : "memory");
+ *((volatile uint8_t *)addr) = val;
+}
+
+static inline void writeq(uint64_t val, unsigned long addr)
+{
+ __asm__ volatile("sync" : : : "memory");
+ *((volatile uint64_t *)addr) = val;
+}
+
+static uint8_t potato_uart_reg_read(int offset)
+{
+ return readb(potato_uart_base + offset);
+}
+
+static void potato_uart_reg_write(int offset, uint8_t val)
+{
+ writeb(val, potato_uart_base + offset);
+}
+
+static bool potato_uart_rx_empty(void)
+{
+ uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS);
+
+ return (val & POTATO_CONSOLE_STATUS_RX_EMPTY) != 0;
+}
+
+static int potato_uart_tx_full(void)
+{
+ uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS);
+
+ return (val & POTATO_CONSOLE_STATUS_TX_FULL) != 0;
+}
+
+static char potato_uart_read(void)
+{
+ return potato_uart_reg_read(POTATO_CONSOLE_RX);
+}
+
+static void potato_uart_write(char c)
+{
+ potato_uart_reg_write(POTATO_CONSOLE_TX, c);
+}
+
+static unsigned long potato_uart_divisor(unsigned long proc_freq,
+ unsigned long uart_freq)
+{
+ return proc_freq / (uart_freq * 16) - 1;
+}
+
+void potato_uart_init(void)
+{
+ potato_uart_base = UART_BASE;
+
+ potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV,
+ potato_uart_divisor(PROC_FREQ, UART_FREQ));
+}
+
+int getchar(void)
+{
+ while (potato_uart_rx_empty())
+ /* Do nothing */ ;
+
+ return potato_uart_read();
+}
+
+int putchar(int c)
+{
+ while (potato_uart_tx_full())
+ /* Do Nothing */;
+
+ potato_uart_write(c);
+ return c;
+}
+
+void putstr(const char *str, unsigned long len)
+{
+ for (unsigned long i = 0; i < len; i++) {
+ if (str[i] == '\n')
+ putchar('\r');
+ putchar(str[i]);
+ }
+}
+
+int _printf(const char *fmt, ...)
+{
+ int count;
+ char buffer[320];
+ va_list ap;
+
+ va_start(ap, fmt);
+ count = vsnprintf(buffer, sizeof(buffer), fmt, ap);
+ va_end(ap);
+ putstr(buffer, count);
+ return count;
+}
+
+void flush_cpu_dcache(void) { }
+void flush_cpu_icache(void) { }
+void flush_l2_cache(void) { }
+
+void main(void)
+{
+ int i;
+
+ // Let things settle ... not sure why but UART not happy otherwise
+ potato_uart_init();
+ for (i = 0; i < 10000; i++)
+ potato_uart_reg_read(POTATO_CONSOLE_STATUS);
+ printf("Welcome to Microwatt !\n");
+ printf(" SIG: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x00));
+ printf(" INFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x08));
+ printf(" BRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x10));
+ printf(" DRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x18));
+ printf(" CTRL: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x20));
+ sdrinit();
+ printf("Booting from BRAM...\n");
+}
--- /dev/null
+SECTIONS
+{
+ . = 0xffff0000;
+ start = .;
+ .head : {
+ KEEP(*(.head))
+ }
+ . = 0xffff1000;
+ .text : { *(.text*) *(.sfpr) *(.rodata*) }
+ .data : { *(.data*) }
+ .bss : { *(.bss*) }
+}
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.sim_console.all;
+
+entity litedram_wrapper is
+ generic (
+ DRAM_ABITS : positive;
+ DRAM_ALINES : positive
+ );
+ port(
+ -- LiteDRAM generates the system clock and reset
+ -- from the input clkin
+ clk_in : in std_ulogic;
+ rst : in std_ulogic;
+ system_clk : out std_ulogic;
+ system_reset : out std_ulogic;
+ core_alt_reset : out std_ulogic;
+ pll_locked : out std_ulogic;
+
+ -- Wishbone ports:
+ wb_in : in wishbone_master_out;
+ wb_out : out wishbone_slave_out;
+ wb_is_csr : in std_ulogic;
+ wb_is_init : in std_ulogic;
+
+ -- Init core serial debug
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+
+ -- Misc
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+
+ -- DRAM wires
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : out std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : out std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic
+ );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+ component litedram_core port (
+ clk : in std_ulogic;
+ rst : in std_ulogic;
+ pll_locked : out std_ulogic;
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : out std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : out std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic;
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+ user_clk : out std_ulogic;
+ user_rst : out std_ulogic;
+ csr_port0_adr : in std_ulogic_vector(13 downto 0);
+ csr_port0_we : in std_ulogic;
+ csr_port0_dat_w : in std_ulogic_vector(7 downto 0);
+ csr_port0_dat_r : out std_ulogic_vector(7 downto 0);
+ user_port0_cmd_valid : in std_ulogic;
+ user_port0_cmd_ready : out std_ulogic;
+ user_port0_cmd_we : in std_ulogic;
+ user_port0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ user_port0_wdata_valid : in std_ulogic;
+ user_port0_wdata_ready : out std_ulogic;
+ user_port0_wdata_we : in std_ulogic_vector(15 downto 0);
+ user_port0_wdata_data : in std_ulogic_vector(127 downto 0);
+ user_port0_rdata_valid : out std_ulogic;
+ user_port0_rdata_ready : in std_ulogic;
+ user_port0_rdata_data : out std_ulogic_vector(127 downto 0)
+ );
+ end component;
+
+ signal user_port0_cmd_valid : std_ulogic;
+ signal user_port0_cmd_ready : std_ulogic;
+ signal user_port0_cmd_we : std_ulogic;
+ signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ signal user_port0_wdata_valid : std_ulogic;
+ signal user_port0_wdata_ready : std_ulogic;
+ signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
+ signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
+ signal user_port0_rdata_valid : std_ulogic;
+ signal user_port0_rdata_ready : std_ulogic;
+ signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
+
+ signal ad3 : std_ulogic;
+
+ signal dram_user_reset : std_ulogic;
+
+ signal csr_port0_adr : std_ulogic_vector(13 downto 0);
+ signal csr_port0_we : std_ulogic;
+ signal csr_port0_dat_w : std_ulogic_vector(7 downto 0);
+ signal csr_port0_dat_r : std_ulogic_vector(7 downto 0);
+ signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
+ signal csr_valid : std_ulogic;
+ signal csr_write_valid : std_ulogic;
+
+ signal wb_init_in : wishbone_master_out;
+ signal wb_init_out : wishbone_slave_out;
+
+ type state_t is (CMD, MWRITE, MREAD, CSR);
+ signal state : state_t;
+
+ constant INIT_RAM_SIZE : integer := 16384;
+ constant INIT_RAM_ABITS :integer := 14;
+ constant INIT_RAM_FILE : string := "sdram_init.hex";
+
+ type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
+
+ impure function init_load_ram(name : string) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ variable ram_line : line;
+ begin
+ for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ hread(ram_line, temp_word);
+ temp_ram(i) := temp_word;
+ end loop;
+ return temp_ram;
+ end function;
+
+ signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+ attribute ram_style : string;
+ attribute ram_style of init_ram: signal is "block";
+
+begin
+
+ -- BRAM Memory slave
+ init_ram_0: process(system_clk)
+ variable adr : integer;
+ begin
+ if rising_edge(system_clk) then
+ wb_init_out.ack <= '0';
+ if (wb_init_in.cyc and wb_init_in.stb) = '1' then
+ adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3))));
+ if wb_init_in.we = '0' then
+ wb_init_out.dat <= init_ram(adr);
+ else
+ for i in 0 to 7 loop
+ if wb_init_in.sel(i) = '1' then
+ init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+ wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
+ end if;
+ end loop;
+ end if;
+ wb_init_out.ack <= not wb_init_out.ack;
+ end if;
+ end if;
+ end process;
+
+ wb_init_in.adr <= wb_in.adr;
+ wb_init_in.dat <= wb_in.dat;
+ wb_init_in.sel <= wb_in.sel;
+ wb_init_in.we <= wb_in.we;
+ wb_init_in.stb <= wb_in.stb;
+ wb_init_in.cyc <= wb_in.cyc and wb_is_init;
+
+ -- Address bit 3 selects the top or bottom half of the data
+ -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+ --
+ ad3 <= wb_in.adr(3);
+
+ -- DRAM data interface signals
+ user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
+ when state = CMD else '0';
+ user_port0_cmd_we <= wb_in.we when state = CMD else '0';
+ user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+ user_port0_rdata_ready <= '1' when state = MREAD else '0';
+ user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
+ user_port0_wdata_data <= wb_in.dat & wb_in.dat;
+ user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
+ "00000000" & wb_in.sel;
+
+ -- DRAM CSR interface signals. We only support access to the bottom byte
+ csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
+ csr_write_valid <= wb_in.we and wb_in.sel(0);
+ csr_port0_adr <= wb_in.adr(15 downto 3) & '0' when wb_is_csr = '1' else (others => '0');
+ csr_port0_dat_w <= wb_in.dat(7 downto 0);
+ csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
+
+ -- Wishbone out signals
+ wb_out.ack <= '1' when state = CSR else
+ wb_init_out.ack when wb_is_init = '1' else
+ user_port0_wdata_ready when state = MWRITE else
+ user_port0_rdata_valid when state = MREAD else '0';
+
+ csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r;
+ wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
+ wb_init_out.dat when wb_is_init = '1' else
+ user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+ user_port0_rdata_data(63 downto 0);
+ -- We don't do pipelining yet.
+ wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+ -- Reset ignored, the reset controller use the pll lock signal,
+ -- and alternate core reset address set when DRAM is not initialized.
+ --
+ system_reset <= '0';
+ core_alt_reset <= not init_done;
+
+ -- State machine
+ sm: process(system_clk)
+ begin
+
+ if rising_edge(system_clk) then
+ if dram_user_reset = '1' then
+ state <= CMD;
+ else
+ case state is
+ when CMD =>
+ if csr_valid = '1' then
+ state <= CSR;
+ elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+ state <= MWRITE when wb_in.we = '1' else MREAD;
+ end if;
+ when MWRITE =>
+ if user_port0_wdata_ready = '1' then
+ state <= CMD;
+ end if;
+ when MREAD =>
+ if user_port0_rdata_valid = '1' then
+ state <= CMD;
+ end if;
+ when CSR =>
+ state <= CMD;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ litedram: litedram_core
+ port map(
+ clk => clk_in,
+ rst => rst,
+ pll_locked => pll_locked,
+ ddram_a => ddram_a,
+ ddram_ba => ddram_ba,
+ ddram_ras_n => ddram_ras_n,
+ ddram_cas_n => ddram_cas_n,
+ ddram_we_n => ddram_we_n,
+ ddram_cs_n => ddram_cs_n,
+ ddram_dm => ddram_dm,
+ ddram_dq => ddram_dq,
+ ddram_dqs_p => ddram_dqs_p,
+ ddram_dqs_n => ddram_dqs_n,
+ ddram_clk_p => ddram_clk_p,
+ ddram_clk_n => ddram_clk_n,
+ ddram_cke => ddram_cke,
+ ddram_odt => ddram_odt,
+ ddram_reset_n => ddram_reset_n,
+ init_done => init_done,
+ init_error => init_error,
+ user_clk => system_clk,
+ user_rst => dram_user_reset,
+ csr_port0_adr => csr_port0_adr,
+ csr_port0_we => csr_port0_we,
+ csr_port0_dat_w => csr_port0_dat_w,
+ csr_port0_dat_r => csr_port0_dat_r,
+ user_port0_cmd_valid => user_port0_cmd_valid,
+ user_port0_cmd_ready => user_port0_cmd_ready,
+ user_port0_cmd_we => user_port0_cmd_we,
+ user_port0_cmd_addr => user_port0_cmd_addr,
+ user_port0_wdata_valid => user_port0_wdata_valid,
+ user_port0_wdata_ready => user_port0_wdata_ready,
+ user_port0_wdata_we => user_port0_wdata_we,
+ user_port0_wdata_data => user_port0_wdata_data,
+ user_port0_rdata_valid => user_port0_rdata_valid,
+ user_port0_rdata_ready => user_port0_rdata_ready,
+ user_port0_rdata_data => user_port0_rdata_data
+ );
+
+end architecture behaviour;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.sim_console.all;
+
+entity litedram_wrapper is
+ generic (
+ DRAM_ABITS : positive;
+ DRAM_ALINES : positive
+ );
+ port(
+ -- LiteDRAM generates the system clock and reset
+ -- from the input clkin
+ clk_in : in std_ulogic;
+ rst : in std_ulogic;
+ system_clk : out std_ulogic;
+ system_reset : out std_ulogic;
+ core_alt_reset : out std_ulogic;
+ pll_locked : out std_ulogic;
+
+ -- Wishbone ports:
+ wb_in : in wishbone_master_out;
+ wb_out : out wishbone_slave_out;
+ wb_is_csr : in std_ulogic;
+ wb_is_init : in std_ulogic;
+
+ -- Init core serial debug
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+
+ -- Misc
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+
+ -- DRAM wires
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic
+ );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+ component litedram_core port (
+ clk : in std_ulogic;
+ rst : in std_ulogic;
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+ pll_locked : out std_ulogic;
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic;
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+ user_clk : out std_ulogic;
+ user_rst : out std_ulogic;
+ user_port_native_0_cmd_valid : in std_ulogic;
+ user_port_native_0_cmd_ready : out std_ulogic;
+ user_port_native_0_cmd_we : in std_ulogic;
+ user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ user_port_native_0_wdata_valid : in std_ulogic;
+ user_port_native_0_wdata_ready : out std_ulogic;
+ user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
+ user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
+ user_port_native_0_rdata_valid : out std_ulogic;
+ user_port_native_0_rdata_ready : in std_ulogic;
+ user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
+ );
+ end component;
+
+ signal user_port0_cmd_valid : std_ulogic;
+ signal user_port0_cmd_ready : std_ulogic;
+ signal user_port0_cmd_we : std_ulogic;
+ signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ signal user_port0_wdata_valid : std_ulogic;
+ signal user_port0_wdata_ready : std_ulogic;
+ signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
+ signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
+ signal user_port0_rdata_valid : std_ulogic;
+ signal user_port0_rdata_ready : std_ulogic;
+ signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
+
+ signal ad3 : std_ulogic;
+
+ signal dram_user_reset : std_ulogic;
+
+ type state_t is (CMD, MWRITE, MREAD);
+ signal state : state_t;
+
+begin
+
+ -- Address bit 3 selects the top or bottom half of the data
+ -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+ --
+ ad3 <= wb_in.adr(3);
+
+ -- DRAM interface signals
+ user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
+ when state = CMD else '0';
+ user_port0_cmd_we <= wb_in.we when state = CMD else '0';
+ user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+ user_port0_rdata_ready <= '1' when state = MREAD else '0';
+ user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
+ user_port0_wdata_data <= wb_in.dat & wb_in.dat;
+ user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
+ "00000000" & wb_in.sel;
+
+ -- Wishbone out signals. CSR and init memory do nothing, just ack
+ wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_wdata_ready when state = MWRITE else
+ user_port0_rdata_valid when state = MREAD else '0';
+ wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+ user_port0_rdata_data(63 downto 0);
+ wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+ -- Reset, lift it when init done, no alt core reset
+ system_reset <= dram_user_reset or not init_done;
+ core_alt_reset <= '0';
+
+ -- State machine
+ sm: process(system_clk)
+ begin
+
+ if rising_edge(system_clk) then
+ if dram_user_reset = '1' then
+ state <= CMD;
+ else
+ case state is
+ when CMD =>
+ if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+ state <= MWRITE when wb_in.we = '1' else MREAD;
+ end if;
+ when MWRITE =>
+ if user_port0_wdata_ready = '1' then
+ state <= CMD;
+ end if;
+ when MREAD =>
+ if user_port0_rdata_valid = '1' then
+ state <= CMD;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ litedram: litedram_core
+ port map(
+ clk => clk_in,
+ rst => rst,
+ serial_tx => serial_tx,
+ serial_rx => serial_rx,
+ pll_locked => pll_locked,
+ ddram_a => ddram_a,
+ ddram_ba => ddram_ba,
+ ddram_ras_n => ddram_ras_n,
+ ddram_cas_n => ddram_cas_n,
+ ddram_we_n => ddram_we_n,
+ ddram_cs_n => ddram_cs_n,
+ ddram_dm => ddram_dm,
+ ddram_dq => ddram_dq,
+ ddram_dqs_p => ddram_dqs_p,
+ ddram_dqs_n => ddram_dqs_n,
+ ddram_clk_p => ddram_clk_p,
+ ddram_clk_n => ddram_clk_n,
+ ddram_cke => ddram_cke,
+ ddram_odt => ddram_odt,
+ ddram_reset_n => ddram_reset_n,
+ init_done => init_done,
+ init_error => init_error,
+ user_clk => system_clk,
+ user_rst => dram_user_reset,
+ user_port_native_0_cmd_valid => user_port0_cmd_valid,
+ user_port_native_0_cmd_ready => user_port0_cmd_ready,
+ user_port_native_0_cmd_we => user_port0_cmd_we,
+ user_port_native_0_cmd_addr => user_port0_cmd_addr,
+ user_port_native_0_wdata_valid => user_port0_wdata_valid,
+ user_port_native_0_wdata_ready => user_port0_wdata_ready,
+ user_port_native_0_wdata_we => user_port0_wdata_we,
+ user_port_native_0_wdata_data => user_port0_wdata_data,
+ user_port_native_0_rdata_valid => user_port0_rdata_valid,
+ user_port_native_0_rdata_ready => user_port0_rdata_ready,
+ user_port_native_0_rdata_data => user_port0_rdata_data
+ );
+
+end architecture behaviour;
--- /dev/null
+vexriscv
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.sim_console.all;
+
+entity litedram_wrapper is
+ generic (
+ DRAM_ABITS : positive;
+ DRAM_ALINES : positive
+ );
+ port(
+ -- LiteDRAM generates the system clock and reset
+ -- from the input clkin
+ clk_in : in std_ulogic;
+ rst : in std_ulogic;
+ system_clk : out std_ulogic;
+ system_reset : out std_ulogic;
+ core_alt_reset : out std_ulogic;
+ pll_locked : out std_ulogic;
+
+ -- Wishbone ports:
+ wb_in : in wishbone_master_out;
+ wb_out : out wishbone_slave_out;
+ wb_is_csr : in std_ulogic;
+ wb_is_init : in std_ulogic;
+
+ -- Init core serial debug
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+
+ -- Misc
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+
+ -- DRAM wires
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic
+ );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+ component litedram_core port (
+ clk : in std_ulogic;
+ rst : in std_ulogic;
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+ pll_locked : out std_ulogic;
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic;
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+ user_clk : out std_ulogic;
+ user_rst : out std_ulogic;
+ user_port_native_0_cmd_valid : in std_ulogic;
+ user_port_native_0_cmd_ready : out std_ulogic;
+ user_port_native_0_cmd_we : in std_ulogic;
+ user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ user_port_native_0_wdata_valid : in std_ulogic;
+ user_port_native_0_wdata_ready : out std_ulogic;
+ user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
+ user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
+ user_port_native_0_rdata_valid : out std_ulogic;
+ user_port_native_0_rdata_ready : in std_ulogic;
+ user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
+ );
+ end component;
+
+ signal user_port0_cmd_valid : std_ulogic;
+ signal user_port0_cmd_ready : std_ulogic;
+ signal user_port0_cmd_we : std_ulogic;
+ signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ signal user_port0_wdata_valid : std_ulogic;
+ signal user_port0_wdata_ready : std_ulogic;
+ signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
+ signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
+ signal user_port0_rdata_valid : std_ulogic;
+ signal user_port0_rdata_ready : std_ulogic;
+ signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
+
+ signal ad3 : std_ulogic;
+
+ signal dram_user_reset : std_ulogic;
+
+ type state_t is (CMD, MWRITE, MREAD);
+ signal state : state_t;
+
+begin
+
+ -- Address bit 3 selects the top or bottom half of the data
+ -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+ --
+ ad3 <= wb_in.adr(3);
+
+ -- DRAM interface signals
+ user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
+ when state = CMD else '0';
+ user_port0_cmd_we <= wb_in.we when state = CMD else '0';
+ user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+ user_port0_rdata_ready <= '1' when state = MREAD else '0';
+ user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
+ user_port0_wdata_data <= wb_in.dat & wb_in.dat;
+ user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
+ "00000000" & wb_in.sel;
+
+ -- Wishbone out signals. CSR and init memory do nothing, just ack
+ wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_wdata_ready when state = MWRITE else
+ user_port0_rdata_valid when state = MREAD else '0';
+ wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+ user_port0_rdata_data(63 downto 0);
+ wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+ -- Reset, lift it when init done, no alt core reset
+ system_reset <= dram_user_reset or not init_done;
+ core_alt_reset <= '0';
+
+ -- State machine
+ sm: process(system_clk)
+ begin
+
+ if rising_edge(system_clk) then
+ if dram_user_reset = '1' then
+ state <= CMD;
+ else
+ case state is
+ when CMD =>
+ if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+ state <= MWRITE when wb_in.we = '1' else MREAD;
+ end if;
+ when MWRITE =>
+ if user_port0_wdata_ready = '1' then
+ state <= CMD;
+ end if;
+ when MREAD =>
+ if user_port0_rdata_valid = '1' then
+ state <= CMD;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ litedram: litedram_core
+ port map(
+ clk => clk_in,
+ rst => rst,
+ serial_tx => serial_tx,
+ serial_rx => serial_rx,
+ pll_locked => pll_locked,
+ ddram_a => ddram_a,
+ ddram_ba => ddram_ba,
+ ddram_ras_n => ddram_ras_n,
+ ddram_cas_n => ddram_cas_n,
+ ddram_we_n => ddram_we_n,
+ ddram_cs_n => ddram_cs_n,
+ ddram_dm => ddram_dm,
+ ddram_dq => ddram_dq,
+ ddram_dqs_p => ddram_dqs_p,
+ ddram_dqs_n => ddram_dqs_n,
+ ddram_clk_p => ddram_clk_p,
+ ddram_clk_n => ddram_clk_n,
+ ddram_cke => ddram_cke,
+ ddram_odt => ddram_odt,
+ ddram_reset_n => ddram_reset_n,
+ init_done => init_done,
+ init_error => init_error,
+ user_clk => system_clk,
+ user_rst => dram_user_reset,
+ user_port_native_0_cmd_valid => user_port0_cmd_valid,
+ user_port_native_0_cmd_ready => user_port0_cmd_ready,
+ user_port_native_0_cmd_we => user_port0_cmd_we,
+ user_port_native_0_cmd_addr => user_port0_cmd_addr,
+ user_port_native_0_wdata_valid => user_port0_wdata_valid,
+ user_port_native_0_wdata_ready => user_port0_wdata_ready,
+ user_port_native_0_wdata_we => user_port0_wdata_we,
+ user_port_native_0_wdata_data => user_port0_wdata_data,
+ user_port_native_0_rdata_valid => user_port0_rdata_valid,
+ user_port_native_0_rdata_ready => user_port0_rdata_ready,
+ user_port_native_0_rdata_data => user_port0_rdata_data
+ );
+
+end architecture behaviour;
--- /dev/null
+b00006f
+13
+13
+13
+13
+13
+13
+13
+fe112e23
+fe512c23
+fe612a23
+fe712823
+fea12623
+feb12423
+fec12223
+fed12023
+fce12e23
+fcf12c23
+fd012a23
+fd112823
+fdc12623
+fdd12423
+fde12223
+fdf12023
+fc010113
+94000ef
+3c12083
+3812283
+3412303
+3012383
+2c12503
+2812583
+2412603
+2012683
+1c12703
+1812783
+1412803
+1012883
+c12e03
+812e83
+412f03
+12f83
+4010113
+30200073
+1001117
+f4c10113
+517
+f6850513
+30551073
+1000517
+f3c50513
+1000597
+5bc58593
+b50863
+52023
+450513
+ff5ff06f
+1537
+88050513
+30451073
+6c010ef
+6f
+fc002773
+bc0027f3
+e7f7b3
+17f793
+78463
+1d10306f
+8067
+82002737
+2872783
+2c72503
+879793
+a7e7b3
+3072503
+879793
+a7e7b3
+3472503
+879793
+a7e533
+8067
+cc0027f3
+c79693
+147d713
+c6d693
+793
+d7e463
+8067
+78513
+7005500f
+e787b3
+fedff06f
+13
+fff50513
+fe051ce3
+8067
+100713
+820037b7
+a71533
+80a7aa23
+80e7ac23
+8007aa23
+8067
+100713
+820037b7
+a71533
+80a7aa23
+80e7ae23
+8007aa23
+8067
+793
+400693
+f58633
+64603
+279713
+a70733
+c72023
+178793
+fed794e3
+8067
+793
+400693
+279713
+a70733
+72603
+f58733
+178793
+c70023
+fed794e3
+8067
+f9010113
+6912223
+50493
+4537
+45850513
+5512a23
+6112623
+6812423
+7212023
+5312e23
+5412c23
+5612823
+5712623
+5812423
+5912223
+5a12023
+3b12e23
+7a4030ef
+2010713
+80200637
+3010593
+2a00793
+70a93
+360613
+400513
+693
+17d813
+17f793
+40f007b3
+c7f7b3
+107c7b3
+d70833
+f80023
+168693
+fea690e3
+470713
+fcb71ae3
+82003437
+42623
+42823
+900793
+42a23
+f42223
+100913
+1242423
+f00513
+eb1ff0ef
+a8593
+1840513
+eedff0ef
+2410593
+4c40513
+ee1ff0ef
+2810593
+8040513
+ed5ff0ef
+2c10593
+b440513
+ec9ff0ef
+a042423
+a042623
+a042823
+1700793
+af42023
+b242223
+6042a23
+6042c23
+6042e23
+48513
+e65ff0ef
+3010793
+100d13
+409d0b33
+4a37
+40978bb3
+913
+438a0a13
+1678c33
+3b8b93
+820037b7
+2500713
+6e7a623
+7a7a823
+f00513
+e19ff0ef
+16a89b3
+413
+100c93
+8a07b3
+7a503
+1c10593
+e6dff0ef
+9c703
+fecc4783
+f71863
+29c703
+fecbc783
+f70463
+c93
+440413
+1000793
+498993
+fcf414e3
+190413
+20c9063
+2000793
+f40a63
+48513
+de5ff0ef
+40913
+f85ff06f
+2000913
+48513
+dd1ff0ef
+3010793
+82003cb7
+40978bb3
+190413
+70c8d13
+100d93
+3b8b93
+2500793
+6fca623
+1bd2023
+f00513
+d75ff0ef
+993
+100793
+13a0733
+72503
+1c10593
+f12623
+dc9ff0ef
+13b0733
+ea8733
+74603
+fecc4703
+c12783
+1000693
+e61c63
+40998733
+ea8733
+374603
+fecbc703
+e60463
+793
+498993
+fad99ae3
+78e63
+140413
+1f00793
+87c863
+48513
+d31ff0ef
+f7dff06f
+8909b3
+2000793
+4019d993
+8f91263
+4537
+46450513
+564030ef
+48513
+cedff0ef
+413
+9344663
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+cadff0ef
+6c12083
+6812403
+6412483
+6012903
+5c12983
+5812a03
+5412a83
+5012b03
+4c12b83
+4812c03
+4412c83
+4012d03
+3c12d83
+7010113
+8067
+41240433
+1f45613
+860633
+4537
+40165613
+98593
+46850513
+4d0030ef
+f6dff06f
+48513
+c71ff0ef
+140413
+f69ff06f
+820037b7
+e00713
+4537
+e7a023
+47450513
+4a40306f
+820037b7
+100713
+4537
+e7a023
+49850513
+48c0306f
+2051663
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+be1ff06f
+1051713
+1075713
+820037b7
+875713
+1051513
+e7a623
+1055513
+a7a823
+7aa23
+900713
+fc5ff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+1412c23
+1512a23
+1612823
+8054663
+100493
+40a484b3
+200993
+4437
+43840413
+1040a13
+4ab7
+300b13
+42503
+c10593
+48913
+bcdff0ef
+c10793
+12787b3
+7c583
+4bca8513
+1390933
+3c4030ef
+ff2b54e3
+440413
+fc8a18e3
+5537
+96c50513
+3ac030ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+1812a03
+1412a83
+1012b03
+3010113
+8067
+100993
+493
+f7dff06f
+1051713
+fe010113
+1075713
+112e23
+b12623
+820037b7
+875713
+1051513
+6e7aa23
+1055513
+6a7ac23
+607ae23
+2500713
+6e7a623
+100713
+f00513
+6e7a823
+ab1ff0ef
+c12583
+1c12083
+58513
+2010113
+eedff06f
+f8010113
+6912a23
+3010493
+7412423
+6112e23
+6812c23
+7212823
+7312623
+7512223
+7612023
+5712e23
+5812c23
+5912a23
+5a12823
+5b12623
+a12423
+4010a13
+48793
+78023
+780a3
+78123
+781a3
+478793
+ff4796e3
+82003437
+49b7
+913
+6c40a93
+2500c13
+2500c93
+100b13
+43898993
+6042a23
+7242c23
+6042e23
+19aa023
+f00513
+7642823
+a01ff0ef
+2010593
+2840513
+a65ff0ef
+2410593
+5c40513
+a59ff0ef
+2810593
+9040513
+a4dff0ef
+2c10593
+c440513
+a41ff0ef
+b93
+400d13
+1000d93
+812783
+cfbc663
+890913
+8000793
+f8f91ce3
+4937
+400993
+413
+8487b3
+7c583
+4bc90513
+140413
+210030ef
+ff3416e3
+448493
+ff4490e3
+5437
+96c40513
+1f8030ef
+400913
+44b7
+100593
+4c448513
+1e4030ef
+593
+4c448513
+1d8030ef
+100593
+4c448513
+1cc030ef
+593
+4c448513
+fff90913
+1bc030ef
+fc0916e3
+96c40513
+1b0030ef
+7c12083
+7812403
+7412483
+7012903
+6c12983
+6812a03
+6412a83
+6012b03
+5c12b83
+5812c03
+5412c83
+5012d03
+4c12d83
+8010113
+8067
+18aa023
+7642823
+f00513
+8e5ff0ef
+793
+f98733
+72503
+1c10593
+f12623
+93dff0ef
+c12783
+2010713
+693
+9785b3
+f70633
+1c10713
+d70733
+74503
+64703
+5c883
+a60023
+e54733
+1176733
+e58023
+168693
+158593
+160613
+fda698e3
+478793
+fbb790e3
+1b8b93
+eb5ff06f
+fd010113
+2912223
+44b7
+2812423
+3212023
+1312e23
+2112623
+50913
+44848493
+413
+4000993
+140793
+f106a3
+4a503
+240793
+810623
+f10723
+340793
+1040413
+c10593
+ff47413
+f107a3
+448493
+85dff0ef
+fd3416e3
+1091713
+1075713
+820037b7
+875713
+1091913
+ae7a423
+1095913
+b27a623
+a07a823
+1700713
+2c12083
+2812403
+ae7a023
+100713
+ae7a223
+2412483
+2012903
+1c12983
+3010113
+8067
+ff010113
+400007b7
+aaaab737
+112623
+812423
+912223
+1212023
+aaa70713
+20078693
+e7a023
+478793
+fed79ce3
+f60ff0ef
+44030ef
+400007b7
+aaaab737
+413
+aaa70713
+20078693
+7a603
+e60463
+140413
+478793
+fed798e3
+400007b7
+55555737
+55570713
+20078693
+e7a023
+478793
+fed79ce3
+f14ff0ef
+7f9020ef
+400007b7
+55555737
+55570713
+20078693
+7a603
+e60463
+140413
+478793
+fed798e3
+40c63
+4537
+10000613
+40593
+4c850513
+781020ef
+802006b7
+40000737
+100793
+368693
+40200637
+17d593
+17f793
+40f007b3
+d7f7b3
+b7c7b3
+f72023
+470713
+fec712e3
+e9cff0ef
+781020ef
+802006b7
+40000737
+493
+100793
+368693
+40200637
+17d593
+17f793
+40f007b3
+d7f7b3
+b7c7b3
+72583
+f58463
+148493
+470713
+fcc71ee3
+48c63
+4537
+80637
+48593
+4ec50513
+6ed020ef
+400006b7
+793
+868693
+2637
+279713
+d70733
+f72023
+178793
+fec798e3
+e18ff0ef
+6fd020ef
+40000737
+106b7
+593
+793
+870713
+fff68693
+2537
+279613
+e60633
+62603
+d67633
+f60463
+158593
+178793
+fea792e3
+2058a63
+4537
+2637
+51050513
+671020ef
+593
+c12083
+812403
+412483
+12903
+58513
+1010113
+8067
+940433
+fe0410e3
+4537
+53450513
+63d020ef
+820027b7
+207a023
+7a823
+7aa23
+7ac23
+7ae23
+ff00713
+e7a023
+10737
+fff70713
+e7a223
+1000737
+fff70713
+e7a423
+fff00713
+e7a623
+100713
+2e7a023
+2e7a223
+d10ff0ef
+50913
+400006b7
+80737
+241793
+d787b3
+87a023
+140413
+fee418e3
+82002437
+100493
+2942223
+ce0ff0ef
+40a905b3
+64000537
+5f8030ef
+50913
+cfcff0ef
+5e1020ef
+2942023
+2942223
+cbcff0ef
+50413
+400007b7
+40200737
+7a683
+478793
+fee79ce3
+820027b7
+100713
+2e7a223
+c94ff0ef
+40a405b3
+64000537
+5ac030ef
+50613
+4537
+90593
+54050513
+551020ef
+100593
+ee1ff06f
+f9010113
+6112623
+6812423
+6912223
+5312e23
+5812423
+7212023
+5412c23
+5512a23
+5612823
+5712623
+5912223
+5a12023
+3b12e23
+855ff0ef
+82003437
+100493
+513
+c8cff0ef
+80942a23
+82942023
+80042a23
+100513
+c78ff0ef
+200793
+80f42a23
+82942023
+4537
+80042a23
+56850513
+4cd020ef
+47b7
+43878793
+1c10993
+413
+f12223
+5c37
+802007b7
+100913
+378793
+891933
+a93
+b93
+493
+f12023
+2c0006f
+48a93
+a0b93
+700793
+1ef48863
+820037b7
+8127aa23
+100713
+82e7a223
+8007aa23
+148493
+3010613
+2010693
+2a00793
+400593
+713
+12803
+17d513
+17f793
+40f007b3
+107f7b3
+a7c7b3
+e68533
+f50023
+170713
+fcb71ee3
+468693
+fcd618e3
+82003a37
+a2623
+a2823
+900793
+a2a23
+fa2223
+100b13
+16a2423
+f00513
+b7cff0ef
+18a0513
+2010593
+bb8ff0ef
+4ca0513
+2410593
+bacff0ef
+80a0513
+2810593
+ba0ff0ef
+b4a0513
+2c10593
+b94ff0ef
+a0a2423
+a0a2623
+a0a2823
+1700793
+afa2023
+b6a2223
+60a2a23
+60a2c23
+47b7
+60a2e23
+48613
+40593
+57878513
+395020ef
+40513
+b1cff0ef
+2000b13
+a13
+82003cb7
+100d93
+2500793
+6fca623
+820037b7
+7b7a823
+f00513
+ae4ff0ef
+2110793
+408786b3
+713
+100d13
+412783
+1c10593
+d12623
+e78633
+62503
+e12423
+b28ff0ef
+c12683
+19c603
+812703
+6c583
+1000813
+c59863
+26c583
+39c603
+c58463
+d13
+470713
+468693
+fb071ae3
+47b7
+d0593
+58478513
+2f5020ef
+40513
+fffb0b13
+1aa0a33
+a90ff0ef
+f60b14e3
+4537
+58850513
+2d5020ef
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+a2cff0ef
+40513
+abcff0ef
+96cc0513
+29d020ef
+e14bc6e3
+e11ff06f
+4537
+a8613
+40593
+58c50513
+281020ef
+820037b7
+8127aa23
+100713
+82e7a023
+8007aa23
+82003737
+793
+100693
+3579263
+40513
+a6cff0ef
+96cc0513
+24d020ef
+fff98993
+2041063
+100413
+d8dff06f
+81272a23
+82d72223
+80072a23
+178793
+fcdff06f
+6c12083
+6812403
+6412483
+6012903
+5c12983
+5812a03
+5412a83
+5012b03
+4c12b83
+4812c03
+4412c83
+4012d03
+3c12d83
+100513
+7010113
+8067
+fe010113
+4537
+1212823
+59c50513
+82004937
+112e23
+812c23
+912a23
+1312623
+1c1020ef
+80092023
+82003437
+80092223
+42623
+42823
+c00793
+42a23
+c537
+f42023
+35050513
+914ff0ef
+42623
+42823
+e00793
+42a23
+2537
+f42023
+71050513
+8f4ff0ef
+200793
+f42623
+20000713
+e42823
+f42a23
+f00793
+f42223
+100493
+942423
+42623
+42823
+300993
+1342a23
+f42223
+942423
+42623
+600713
+e42823
+942a23
+f42223
+942423
+900713
+e42623
+1737
+92070713
+e42823
+42a23
+f42223
+c800513
+942423
+878ff0ef
+400793
+f42623
+40000793
+f42823
+42a23
+1342223
+c800513
+942423
+854ff0ef
+b8dff0ef
+c2cff0ef
+88dff0ef
+80992023
+2051263
+80992223
+1c12083
+1812403
+1412483
+1012903
+c12983
+2010113
+8067
+100513
+fe1ff06f
+f7010113
+8112623
+8812423
+8912223
+9212023
+7312e23
+793
+bc079073
+30046073
+5437
+315020ef
+96c40513
+65020ef
+4537
+5b450513
+59020ef
+4537
+5dc50513
+4d020ef
+4537
+60450513
+41020ef
+4537
+62850513
+35020ef
+4537
+64c50513
+29020ef
+96c40513
+21020ef
+4537
+67850513
+15020ef
+4537
+6a050513
+9020ef
+96c40513
+1020ef
+4537
+6c450513
+7f4020ef
+684000ef
+96c40513
+7e8020ef
+4537
+6ec50513
+7dc020ef
+4537
+70850513
+7d0020ef
+96c40513
+7c8020ef
+4537
+72450513
+7bc020ef
+45b7
+4537
+6400613
+75858593
+76450513
+7a4020ef
+4537
+1800593
+78450513
+794020ef
+4537
+400593
+7a050513
+784020ef
+4537
+593
+7bc50513
+774020ef
+4537
+45b7
+7d850513
+764020ef
+96c40513
+75c020ef
+4537
+7f450513
+750020ef
+d69ff0ef
+100793
+50493
+f50863
+5537
+82850513
+734020ef
+96c40513
+72c020ef
+2048663
+5537
+84850513
+71c020ef
+a0000ef
+50863
+5537
+87c50513
+708020ef
+96c40513
+700020ef
+5537
+89450513
+6f4020ef
+1a8010ef
+5937
+54b7
+8c890593
+8dc48513
+6dc020ef
+59b7
+4000593
+3010513
+1c4010ef
+3014783
+2078c63
+96c40513
+6bc020ef
+1010613
+c10593
+3010513
+5b4000ef
+50593
+c12503
+1010613
+638000ef
+51663
+8e098513
+690020ef
+8c890593
+8dc48513
+684020ef
+fadff06f
+68067
+5537
+ec010113
+92c50513
+12112e23
+12812c23
+12912a23
+13212823
+13312623
+13412423
+13512223
+13612023
+11712e23
+11812c23
+644020ef
+5537
+5437
+94450513
+90c40493
+630020ef
+90c40413
+4c503
+8051e63
+820027b7
+207a023
+7a823
+7aa23
+7ac23
+7ae23
+100713
+e7a023
+17d00693
+d7a223
+186b7
+d7868693
+d7a423
+17d86b7
+84068693
+d7a623
+2e7a023
+2e7a223
+b13
+82002ab7
+5100493
+1b00913
+e00993
+100a13
+28aa783
+2caa703
+879793
+e7e7b3
+30aa703
+879793
+e7e7b3
+34aa703
+879793
+e7e7b3
+79e63
+5537
+9f450513
+e00006f
+7b4020ef
+148493
+f59ff06f
+78c020ef
+c050e63
+730020ef
+28950863
+29250663
+16407b3
+107c783
+aa79e63
+1b0b13
+b3b1e63
+54b7
+a93
+300993
+100913
+500413
+8f448493
+82000a37
+6f4020ef
+a10623
+6ec020ef
+a106a3
+6e4020ef
+a10723
+c10b93
+6d8020ef
+a107a3
+b8c13
+b13
+c14583
+1c0c13
+6bb4863
+f14783
+f378063
+e14783
+d14703
+158593
+879793
+e7e7b3
+879b13
+87d793
+fb67b3
+1079b13
+f10513
+10b5b13
+140020ef
+5650c63
+6d4020ef
+2051e63
+1a8a93
+28a9e63
+5537
+97050513
+4ac020ef
+580006f
+f8650513
+153b13
+34aa223
+ed9ff06f
+650020ef
+ac01a3
+1b0b13
+f7dff06f
+640020ef
+fbdff06f
+4300513
+6a4020ef
+f3dff06f
+f14783
+16f46e63
+279793
+9787b3
+7a783
+78067
+4b00513
+680020ef
+100513
+13c12083
+13812403
+13412483
+13012903
+12c12983
+12812a03
+12412a83
+12012b03
+11c12b83
+11812c03
+14010113
+8067
+1014783
+1114703
+1879793
+1071713
+e7e7b3
+1314703
+e7e7b3
+1214703
+871713
+e7e7b3
+ffc78793
+400713
+c14683
+e78633
+1b8b93
+d74c63
+f14783
+a93
+4b00513
+e9279ce3
+f55ff06f
+7bc683
+170713
+d60023
+fd1ff06f
+1014403
+1114783
+4b00513
+1841413
+1079793
+f46433
+1314783
+f46433
+1214783
+879793
+f46433
+5b8020ef
+5537
+40593
+99850513
+37c020ef
+5537
+9c050513
+370020ef
+65c020ef
+793
+bc079073
+30047073
+100f
+13
+13
+13
+13
+13
+cc0027f3
+c79693
+147d713
+c6d693
+793
+2d7e063
+368020ef
+40693
+613
+593
+513
+c9dff0ef
+6f
+78513
+7005500f
+e787b3
+fd5ff06f
+4b00513
+528020ef
+12a2023
+dbdff06f
+1a8a93
+e28a8ce3
+5500513
+e6dff06f
+5537
+a0050513
+2d8020ef
+513
+e85ff06f
+fd010113
+3212023
+50913
+5537
+a0c50513
+2912223
+1412c23
+1512a23
+1612823
+1712623
+1812423
+2112623
+2812423
+1312e23
+1912223
+58493
+60a13
+5b37
+204020ef
+5ab7
+5bb7
+5c37
+4904063
+2812403
+2c12083
+2412483
+2012903
+1c12983
+1812a03
+1412a83
+1012b03
+c12b83
+812c03
+412c83
+5537
+96c50513
+3010113
+2380206f
+1000793
+48413
+97d463
+1000413
+5537
+a0593
+a1c50513
+218020ef
+993
+5cb7
+13907b3
+7c583
+a28c8513
+198993
+1fc020ef
+ff3416e3
+40993
+1000c93
+5999a63
+a24a8513
+1e4020ef
+993
+5e00c93
+13907b3
+7c583
+fe058793
+ff7f793
+4fcf063
+a34c0513
+1c0020ef
+198993
+ff3410e3
+40993
+1000c93
+3999863
+890933
+408484b3
+8a0a33
+f29ff06f
+a30b0513
+194020ef
+198993
+fa1ff06f
+a38b8513
+184020ef
+fc5ff06f
+a24a8513
+178020ef
+198993
+fc5ff06f
+ff010113
+65b7
+812423
+793
+ae05a403
+ae058593
+40f585b3
+513
+112623
+60d010ef
+2a41063
+40593
+812403
+c12083
+5537
+a3c50513
+1010113
+1280206f
+50613
+5537
+40593
+a5850513
+114020ef
+812403
+c12083
+5537
+a8450513
+1010113
+fc0206f
+60793
+2060713
+7a023
+478793
+fef71ce3
+a5a023
+2000713
+54783
+4e78e63
+79663
+513
+8067
+150513
+fe9ff06f
+178793
+2c0006f
+78023
+68513
+178793
+7c683
+fee68ce3
+2068e63
+150693
+251513
+a60533
+f52023
+7c583
+fce58ae3
+fc0594e3
+68513
+8067
+150793
+50023
+2000713
+513
+fc1ff06f
+8067
+fd010113
+2812423
+2912223
+6437
+64b7
+3212023
+1312e23
+2112623
+50913
+58993
+94840413
+99848493
+941663
+513
+380006f
+42783
+90513
+c12623
+47a583
+2c8010ef
+c12603
+2051c63
+42783
+98513
+60593
+7a783
+780e7
+42503
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+440413
+fa1ff06f
+cc0027f3
+c79693
+147d713
+c6d693
+793
+d7e463
+8067
+78513
+7005500f
+e787b3
+fedff06f
+820007b7
+100713
+e7a023
+8067
+fe010113
+5537
+1212823
+1312623
+ab850513
+6937
+49b7
+912a23
+1412423
+1512223
+1612023
+112e23
+812c23
+493
+69d010ef
+6a37
+99890913
+5ab7
+46498993
+5b37
+713
+948a0413
+300006f
+42783
+c7a683
+2969063
+87a603
+47a583
+61463
+98613
+adca8513
+719010ef
+100713
+440413
+fd241ae3
+70663
+96cb0513
+701010ef
+148493
+a00793
+faf498e3
+1c12083
+1812403
+1412483
+1012903
+c12983
+812a03
+412a83
+12b03
+2010113
+8067
+ef010113
+10513
+10112623
+7a1010ef
+14783
+10593
+79663
+45b7
+46458593
+5537
+ae850513
+69d010ef
+10c12083
+11010113
+8067
+fe010113
+112e23
+812c23
+912a23
+100793
+2a7c263
+5537
+af450513
+66d010ef
+1c12083
+1812403
+1412483
+2010113
+8067
+58413
+42503
+613
+c10593
+410010ef
+c12783
+50493
+7c783
+78863
+5537
+b0c50513
+fbdff06f
+442503
+c10593
+613
+3e4010ef
+c12783
+50593
+7c783
+78863
+5537
+b2050513
+f91ff06f
+48513
+2b9010ef
+50593
+5537
+b3450513
+5e5010ef
+f79ff06f
+fd010113
+2812423
+2112623
+58413
+a04c63
+513
+93dfe0ef
+5537
+c2850513
+5b9010ef
+42503
+613
+1c10593
+374010ef
+1c12783
+7c783
+2078063
+5537
+c3450513
+591010ef
+2c12083
+2812403
+3010113
+8067
+a12623
+8f1fe0ef
+c12583
+5537
+c4450513
+569010ef
+fd9ff06f
+fff00513
+92dfe06f
+fe010113
+112e23
+812c23
+912a23
+1212823
+2a04463
+5537
+c5850513
+539010ef
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+58413
+50493
+42503
+613
+c10593
+2d4010ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb5ff06f
+100793
+2f48863
+442503
+c10593
+613
+2a0010ef
+c12783
+50593
+7c783
+78a63
+5537
+c6850513
+f81ff06f
+fff00593
+90513
+939fe0ef
+f75ff06f
+fe010113
+112e23
+a04e63
+5537
+c7850513
+491010ef
+1c12083
+2010113
+8067
+58793
+7a503
+613
+c10593
+23c010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+fc9ff06f
+93dfe0ef
+fc5ff06f
+fe010113
+112e23
+a04e63
+5537
+c9c50513
+439010ef
+1c12083
+2010113
+8067
+58793
+7a503
+613
+c10593
+1e4010ef
+c12783
+7c783
+78863
+5537
+b0c50513
+fc9ff06f
+b0dfe0ef
+fc5ff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+100793
+2a7c663
+5537
+dfc50513
+3cd010ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+58413
+50493
+42503
+613
+c10593
+164010ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb1ff06f
+442503
+613
+c10593
+138010ef
+c12783
+50993
+7c783
+78863
+5537
+e1c50513
+f85ff06f
+200793
+100513
+2f48663
+842503
+613
+c10593
+100010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+f51ff06f
+793
+279713
+1270733
+f4f502e3
+1372023
+178793
+fedff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+100793
+2a7c663
+5537
+e2c50513
+2d5010ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+58413
+50493
+42503
+613
+c10593
+6c010ef
+c12783
+50993
+7c783
+78863
+5537
+e4450513
+fb1ff06f
+442503
+613
+c10593
+40010ef
+c12783
+50913
+7c783
+78863
+5537
+e6450513
+f85ff06f
+200793
+100513
+2f48663
+842503
+613
+c10593
+8010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+f51ff06f
+793
+279713
+e986b3
+e90733
+f4f500e3
+72703
+178793
+e6a023
+fe5ff06f
+fe010113
+112e23
+812c23
+912a23
+1212823
+2a04463
+5537
+e8050513
+1dd010ef
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+58413
+50493
+42503
+613
+c10593
+779000ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb5ff06f
+100793
+2f48863
+442503
+c10593
+613
+745000ef
+c12783
+50593
+7c783
+78a63
+5537
+e9850513
+f81ff06f
+400593
+90613
+90513
+e80ff0ef
+f71ff06f
+fb010113
+10007b7
+4812423
+3f878413
+5212023
+3312e23
+3412c23
+3512a23
+4112623
+4912223
+3612823
+3712623
+3812423
+3912223
+3a12023
+1b12e23
+50a93
+58a13
+28040993
+3f878713
+3f878913
+70023
+4070713
+ff371ce3
+64b7
+6b37
+94848493
+998b0b13
+a00b93
+7649663
+a8513
+455000ef
+57b7
+9bc78793
+fa2023
+40793
+7c703
+1e071063
+4078793
+ff379ae3
+513
+4c12083
+4812403
+4412483
+4012903
+3c12983
+3812a03
+3412a83
+3012b03
+2c12b83
+2812c03
+2412c83
+2012d03
+1c12d83
+5010113
+8067
+4a783
+a8513
+47a583
+b12623
+3e1000ef
+c12583
+50613
+a8513
+321000ef
+2051463
+40793
+7c703
+2071263
+4a783
+651513
+4000613
+47a583
+a90533
+2a5000ef
+448493
+f45ff06f
+150513
+4078793
+fd7518e3
+fedff06f
+178793
+4070713
+14d79063
+793
+1480006f
+40793
+713
+7c683
+68463
+170713
+4078793
+ff3798e3
+100793
+1000bb7
+513
+af70c63
+a091a63
+4ba503
+a050663
+5cb7
+96cc8513
+7ac010ef
+40b13
+a93
+b4783
+78c63
+b0513
+321000ef
+450513
+aad463
+50a93
+40b0b13
+ff3b10e3
+60a8463
+1a8593
+5000513
+74020ef
+50c13
+a00b13
+5d37
+5db7
+44783
+2078263
+1b0b13
+c0593
+b0513
+90020ef
+4051c63
+40593
+ae4d8513
+738010ef
+4040413
+fd341ae3
+c0593
+b0513
+6c020ef
+50663
+96cc8513
+718010ef
+ba223
+100513
+1248933
+90023
+9a2023
+4c783
+2079263
+100793
+fba223
+e51ff06f
+40613
+a8593
+ef4d0513
+6e0010ef
+fa9ff06f
+ba223
+e35ff06f
+10004b7
+3a048c23
+40713
+793
+3b848493
+a00693
+74603
+ea060ae3
+679793
+f907b3
+913
+a78733
+74683
+ea0688e3
+40713
+74603
+60a63
+a70633
+64603
+60863
+e8d61ae3
+4070713
+ff3712e3
+1248733
+d70023
+150513
+190913
+fc1ff06f
+fe010113
+812c23
+912a23
+1212823
+112e23
+50913
+60493
+6a403
+59663
+62603
+a861e63
+fff78793
+287f063
+1812403
+1c12083
+1412483
+1012903
+700513
+2010113
+4700106f
+140413
+86a023
+8058663
+4a583
+100793
+40b40433
+287f063
+158513
+a70533
+b705b3
+fff40613
+e12623
+2a1000ef
+c12703
+4a783
+5537
+40593
+f707b3
+1278023
+4a603
+f8c50513
+c70633
+5b8010ef
+4a783
+178793
+f4a023
+fff40413
+41e63
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+800513
+3e0010ef
+fd9ff06f
+4a783
+5537
+100593
+f707b3
+1278023
+4a603
+f8c50513
+c70633
+55c010ef
+4a783
+178793
+f4a023
+fadff06f
+10007b7
+7aa23
+10007b7
+fff00713
+7a823
+10007b7
+e7a623
+10007b7
+7a423
+10007b7
+3878793
+28078713
+78023
+4078793
+fee79ce3
+8067
+fb010113
+3312e23
+3412c23
+3512a23
+3712623
+59b7
+5bb7
+5ab7
+1000a37
+4812423
+5212023
+3612823
+3812423
+4112623
+4912223
+3912223
+3a12023
+50413
+58b13
+12623
+12823
+100913
+fe498993
+efcb8c13
+9bca8a93
+38a0a13
+358010ef
+1b00793
+50713
+4f51863
+348010ef
+a10c23
+340010ef
+a10ca3
+a98533
+54783
+200493
+47f793
+a078463
+7e00d13
+500c93
+31c010ef
+1810793
+9787b3
+a78023
+148493
+9a50463
+ff9494e3
+fff00713
+ff77513
+a00793
+5af50063
+d00793
+58f50c63
+ff77793
+b00693
+38d78463
+12f6c663
+400693
+30d78863
+8f6cc63
+200693
+2ed78463
+26f6cc63
+100693
+26d78263
+1871713
+41875713
+f4074ce3
+f987b3
+7c783
+977f793
+f40784e3
+b0793
+40713
+1010693
+c10613
+90593
+d71ff0ef
+f2dff06f
+2010793
+9784b3
+fe048c23
+efcb8c93
+493
+1200d13
+ca583
+1810513
+658000ef
+51a63
+349493
+9c04b3
+44c703
+f51ff06f
+148493
+8c8c93
+fda49ce3
+f3dff06f
+600693
+22d78663
+32d7c063
+800693
+10d78063
+900693
+f6d794e3
+1012783
+1410593
+40513
+f407b3
+78023
+c12783
+f407b3
+7c483
+78023
+9fdff0ef
+c12783
+f407b3
+978023
+12051c63
+493
+1412783
+9787b3
+7c503
+e6050ee3
+b0793
+40713
+1010693
+c10613
+90593
+148493
+ca1ff0ef
+fd5ff06f
+1800693
+2ed78063
+6f6c663
+f00693
+2ad78c63
+1000693
+d78663
+e00693
+ecd79ce3
+10007b7
+1000693
+c7a703
+36d51a63
+2074a63
+fff70693
+d7a623
+fff00613
+c69863
+10006b7
+146a683
+d7a623
+10006b7
+c7a583
+106a683
+32d59263
+e7a623
+700513
+e8010ef
+de9ff06f
+8500693
+22d78463
+6f6ca63
+7f00693
+e6d79ae3
+c12583
+dc0586e3
+1012483
+fff58513
+a12623
+40b484b3
+48613
+b405b3
+a40533
+70c000ef
+800513
+a0010ef
+c12603
+5537
+48593
+c40633
+f8c50513
+22c010ef
+2000513
+80010ef
+fff00c93
+800513
+fff48493
+70010ef
+ff949ae3
+1600006f
+8900693
+22d78c63
+ff00693
+f89ff06f
+55b7
+5537
+40613
+8c858593
+f9450513
+1e4010ef
+ea048ae3
+493
+100006f
+800513
+2c010ef
+148493
+1012783
+c12703
+40e787b3
+fef4e4e3
+e8dff06f
+800513
+c010ef
+c12783
+fff78793
+f12623
+c12783
+fe0794e3
+cf9ff06f
+40023
+fff00913
+4c12083
+4812403
+90513
+4412483
+4012903
+3c12983
+3812a03
+3412a83
+3012b03
+2c12b83
+2812c03
+2412c83
+2012d03
+5010113
+8067
+c12783
+1012703
+cae7f4e3
+f407b3
+7c503
+799000ef
+c12783
+178793
+f12623
+c8dff06f
+c12783
+c80782e3
+800513
+779000ef
+c12783
+fff78793
+fe1ff06f
+c12503
+1012483
+c69572e3
+fff48493
+40a484b3
+2048863
+150593
+48613
+b405b3
+a40533
+5a4000ef
+c12603
+5537
+48593
+c40633
+f8c50513
+cc010ef
+2000513
+721000ef
+fff00c93
+800513
+fff48493
+711000ef
+ff949ae3
+1012783
+fff78793
+240006f
+c12483
+1012783
+bef4fce3
+1012783
+48c93
+f4ea63
+c12783
+197ee63
+f12823
+bddff06f
+2000513
+6d1000ef
+148493
+fd9ff06f
+800513
+6c1000ef
+fffc8c93
+fd5ff06f
+c12783
+1012583
+bab7f8e3
+f40633
+40f585b3
+5537
+f8c50513
+3c010ef
+1012783
+f05ff06f
+194913
+b8dff06f
+800513
+681000ef
+c12783
+fff78793
+f12623
+c12783
+fe0794e3
+1012783
+b60784e3
+493
+100006f
+2000513
+655000ef
+148493
+1012783
+48c93
+fef4e6e3
+c12783
+f797f0e3
+800513
+635000ef
+fffc8c93
+fedff06f
+c12503
+1012483
+b29572e3
+40a484b3
+150593
+48613
+b405b3
+a40533
+46c000ef
+c12603
+5537
+fff48593
+c40633
+f8c50513
+795000ef
+2000513
+5e9000ef
+800513
+fff48493
+5dd000ef
+fe049ae3
+ecdff06f
+659593
+ba0cb3
+c12783
+4079a63
+1012783
+8078463
+493
+680006f
+cc0742e3
+10006b7
+106a683
+cae68ce3
+1000637
+1462603
+170713
+e7a623
+e65463
+7a623
+c7a783
+a8c93
+faf68ce3
+679793
+fa0cb3
+fadff06f
+800513
+56d000ef
+c12783
+fff78793
+f12623
+f95ff06f
+2000513
+555000ef
+148493
+1012783
+48d13
+fef4e6e3
+c12783
+3a7ea63
+f12823
+c8593
+40513
+13c000ef
+40513
+254000ef
+c12583
+a12823
+a0a5fee3
+b40633
+40b505b3
+e6dff06f
+800513
+505000ef
+fffd0d13
+fbdff06f
+1012903
+10004b7
+12407b3
+78023
+44783
+6078063
+2100713
+4e78c63
+104a783
+1000537
+3850513
+679793
+f50533
+40593
+d0000ef
+104a783
+900713
+178793
+2f74e63
+f4a823
+10007b7
+104a703
+147a683
+e6d463
+e7aa23
+1000737
+872783
+178793
+f72423
+104a703
+10007b7
+e7a623
+c91ff06f
+4a823
+fc9ff06f
+ff5f593
+54783
+b79463
+8067
+78663
+150513
+fedff06f
+513
+8067
+54703
+2071263
+513
+8067
+fee68ee3
+178793
+7c683
+fe069ae3
+150513
+fddff06f
+58793
+fedff06f
+b505b3
+ff67613
+b50663
+54783
+79663
+513
+8067
+fef60ee3
+150513
+fe5ff06f
+50793
+158593
+fff5c703
+178793
+fee78fa3
+fe0718e3
+8067
+c50633
+50793
+c79463
+8067
+5c703
+e78023
+70463
+158593
+178793
+fe5ff06f
+158593
+54703
+fff5c783
+40f707b3
+1879793
+4187d793
+79663
+150513
+fe0710e3
+78513
+8067
+713
+c71863
+793
+78513
+8067
+e507b3
+7c683
+e587b3
+7c783
+40f687b3
+1879793
+4187d793
+fc079ee3
+fc068ce3
+170713
+fc9ff06f
+50793
+7c703
+178693
+71e63
+158593
+fff5c703
+178793
+fee78fa3
+fe0718e3
+8067
+68793
+fd9ff06f
+50793
+61663
+8067
+68793
+7c703
+178693
+fe071ae3
+c78633
+158593
+fff5c703
+178793
+fee78fa3
+fc070ce3
+fec796e3
+78023
+8067
+50793
+7c703
+71663
+40a78533
+8067
+178793
+fedff06f
+fe010113
+812c23
+b12623
+50413
+112e23
+fd1ff0ef
+c12583
+a40533
+ff5f593
+54783
+b78863
+fff50513
+fe857ae3
+513
+1c12083
+1812403
+2010113
+8067
+b505b3
+50793
+b78663
+7c703
+71663
+40a78533
+8067
+178793
+fe9ff06f
+793
+f50733
+74683
+68e63
+58713
+c0006f
+d60c63
+170713
+74603
+fe061ae3
+78513
+8067
+178793
+fd1ff06f
+713
+e61663
+793
+200006f
+e507b3
+e586b3
+7c783
+6c683
+170713
+40d787b3
+fc078ee3
+78513
+8067
+c50633
+50793
+c79463
+8067
+178793
+feb78fa3
+ff1ff06f
+793
+f61463
+8067
+f58733
+74683
+f50733
+178793
+d70023
+fe5ff06f
+2a5fa63
+fff64693
+793
+fff78793
+2f69663
+8067
+f58733
+74683
+f50733
+178793
+d70023
+fef616e3
+8067
+793
+ff5ff06f
+f60733
+e58833
+84803
+e50733
+1070023
+fbdff06f
+fe010113
+812c23
+50413
+58513
+1312623
+112e23
+912a23
+1212823
+1412423
+58993
+e51ff0ef
+4050063
+50913
+40513
+e41ff0ef
+50493
+a40a33
+409a0433
+124f663
+413
+1c0006f
+90613
+98593
+40513
+fff48493
+ed5ff0ef
+fc051ee3
+40513
+1c12083
+1812403
+1412483
+1012903
+c12983
+812a03
+2010113
+8067
+c50633
+ff5f593
+c51663
+513
+8067
+54703
+150793
+feb70ae3
+78513
+fe5ff06f
+fd010113
+2812423
+3212023
+1312e23
+2112623
+2912223
+5937
+50413
+58993
+54783
+fe490913
+4061e63
+3000713
+a00613
+4e79463
+154783
+150693
+f90733
+74703
+277713
+70663
+fe078793
+ff7f793
+5800713
+ce79c63
+244783
+f907b3
+7c783
+447f793
+c078263
+240413
+1000613
+513
+580006f
+1000713
+fee61ae3
+3000713
+fee796e3
+154783
+f90733
+74703
+277713
+70663
+fe078793
+ff7f793
+5800713
+fce794e3
+240413
+fc1ff06f
+60593
+c12623
+388010ef
+c12603
+950533
+140413
+44783
+f90733
+74703
+4477693
+2068463
+477693
+fd078493
+69c63
+277713
+70663
+fe078793
+ff7f793
+fc978493
+fac4eae3
+98463
+89a023
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+68413
+800613
+f41ff06f
+54683
+2d00713
+e68463
+eb1ff06f
+ff010113
+150513
+112623
+ea1ff0ef
+c12083
+40a00533
+1010113
+8067
+5737
+50613
+fe470713
+513
+62683
+6c783
+f707b3
+7c783
+47f793
+79463
+8067
+168793
+f62023
+251793
+a787b3
+6c503
+179793
+a787b3
+fd078513
+fc5ff06f
+f7010113
+7312e23
+68993
+56b7
+8812423
+9212023
+7412c23
+7612823
+60a13
+fe468693
+8112623
+8912223
+7512a23
+7712623
+7812423
+7912223
+4087613
+50413
+58913
+12868b13
+60463
+10068b13
+1087693
+68463
+ffe87813
+ffe98693
+2200613
+513
+22d66a63
+187693
+3000c13
+69463
+2000c13
+287693
+a93
+68a63
+80a5863
+41400a33
+fff70713
+2d00a93
+2087c93
+c8863
+1000693
+8d99e63
+ffe70713
+a0a1263
+3000693
+d10e23
+100493
+48693
+f4d463
+78693
+1187793
+40d70733
+10078463
+a8863
+1247463
+1540023
+140413
+c8e63
+800793
+ef99e63
+1247663
+3000793
+f40023
+140413
+1087813
+14080063
+40513
+d406b3
+3000613
+1480006f
+487693
+68863
+fff70713
+2b00a93
+f71ff06f
+887693
+f60684e3
+fff70713
+2000a93
+f5dff06f
+800693
+f6d994e3
+fff70713
+f61ff06f
+1c10b93
+493
+98593
+a0513
+1012623
+f12423
+e12223
+705000ef
+ab0533
+54683
+98593
+a0513
+db8023
+72d000ef
+148493
+1b8b93
+412703
+812783
+c12803
+f33a60e3
+50a13
+fb5ff06f
+127f463
+a78023
+178793
+40f58633
+fec048e3
+70793
+75463
+793
+fff70713
+f40433
+40f70733
+f01ff06f
+40793
+e405b3
+2000513
+fd1ff06f
+1000793
+f0f99ae3
+1247663
+3000793
+f40023
+140793
+127f663
+21b4783
+f400a3
+240413
+ef1ff06f
+127f463
+1878023
+178793
+40f58633
+fec048e3
+70793
+75463
+793
+fff70713
+f40433
+40f70733
+ec9ff06f
+40793
+e405b3
+fd5ff06f
+1257463
+c50023
+150513
+40a687b3
+fef4c8e3
+48793
+50693
+fff00613
+fff78793
+4c79e63
+950533
+50793
+e50633
+2000593
+40f606b3
+6d04063
+75463
+713
+e50533
+8c12083
+8812403
+8412483
+8012903
+7c12983
+7812a03
+7412a83
+7012b03
+6c12b83
+6812c03
+6412c83
+9010113
+8067
+126fa63
+1c10593
+f585b3
+5c583
+b68023
+168693
+f89ff06f
+127f463
+b78023
+178793
+f91ff06f
+ff010113
+812423
+112623
+58413
+65000ef
+856463
+fff40513
+c12083
+812403
+1010113
+8067
+fc010113
+2d12623
+2c10693
+112e23
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+25000ef
+1c12083
+4010113
+8067
+fc010113
+2d12623
+2c10693
+812c23
+112e23
+58413
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+7e8000ef
+856463
+fff40513
+1c12083
+1812403
+4010113
+8067
+60693
+58613
+800005b7
+fff5c593
+7bc0006f
+fc010113
+2c12423
+58613
+800005b7
+2d12623
+fff5c593
+2810693
+112e23
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+784000ef
+1c12083
+4010113
+8067
+1000737
+1872783
+779513
+f50533
+361967b7
+2e978793
+f50533
+a72c23
+8067
+10007b7
+a7ac23
+8067
+5537
+ff010113
+13450513
+112623
+42c000ef
+6f
+1851713
+1855793
+106b7
+e7e7b3
+f0068693
+855713
+d77733
+e7e7b3
+851513
+ff0737
+e57533
+a7e533
+8067
+851793
+855513
+a7e533
+1051513
+1055513
+8067
+1851713
+1855793
+106b7
+e7e7b3
+f0068693
+855713
+d77733
+e7e7b3
+851513
+ff0737
+e57533
+a7e533
+8067
+851793
+855513
+a7e533
+1051513
+1055513
+8067
+56b7
+793
+b505b3
+14068693
+40a58733
+e04663
+78513
+8067
+150513
+fff54603
+87d713
+879793
+c74733
+271713
+e68733
+75703
+1079793
+107d793
+f747b3
+fc5ff06f
+56b7
+50713
+fff00793
+b508b3
+700813
+54068693
+40e88633
+4c86a63
+35d713
+371693
+40d585b3
+d50533
+2058c63
+56b7
+b505b3
+54068693
+150513
+fff54703
+f74733
+ff77713
+271713
+e68733
+72703
+87d793
+f747b3
+fcb51ee3
+fff7c513
+8067
+74603
+870713
+f64633
+ff67613
+261613
+c68633
+62603
+87d793
+f647b3
+ff974603
+f64633
+ff67613
+261613
+c68633
+62603
+87d793
+f64633
+ffa74783
+c7c7b3
+ff7f793
+279793
+f687b3
+7a303
+ffb74783
+865613
+c34333
+67c7b3
+ff7f793
+279793
+f687b3
+7a603
+ffc74783
+835313
+664633
+c7c7b3
+ff7f793
+279793
+f687b3
+7a303
+ffd74783
+865613
+c34333
+67c7b3
+ff7f793
+279793
+f687b3
+7a783
+ffe74603
+835313
+67c7b3
+f64633
+ff67613
+261613
+c68633
+62303
+fff74603
+87d793
+f34333
+664633
+ff67613
+261613
+c68633
+62783
+835313
+67c7b3
+ea5ff06f
+10007b7
+2a7a223
+8067
+10007b7
+2a7a023
+10007b7
+b7ae23
+8067
+ff010113
+912223
+ff57493
+812423
+50413
+48513
+112623
+3b4000ef
+10007b7
+247a783
+78663
+48513
+780e7
+a00793
+f41663
+d00513
+fc1ff0ef
+40513
+c12083
+812403
+412483
+1010113
+8067
+ff010113
+812423
+112623
+1000437
+348000ef
+50a63
+812403
+c12083
+1010113
+2e00006f
+1c42783
+fe0782e3
+780e7
+fc050ee3
+812403
+10007b7
+c12083
+207a303
+1010113
+30067
+ff010113
+112623
+300000ef
+2051263
+10007b7
+1c7a783
+78663
+780e7
+a03533
+c12083
+1010113
+8067
+100513
+ff1ff06f
+ff010113
+812423
+112623
+50413
+44503
+2051063
+a00513
+f01ff0ef
+c12083
+812403
+100513
+1010113
+8067
+ee9ff0ef
+140413
+fd5ff06f
+ff010113
+812423
+112623
+50413
+44503
+51a63
+c12083
+812403
+1010113
+8067
+eb5ff0ef
+140413
+fe1ff06f
+ef010113
+58693
+50613
+10000593
+10513
+10112623
+10812423
+ac5ff0ef
+10010793
+50413
+a787b3
+10513
+f0078023
+f99ff0ef
+40513
+10c12083
+10812403
+11010113
+8067
+fc010113
+2b12223
+2410593
+112e23
+2c12423
+2d12623
+2e12823
+2f12a23
+3012c23
+3112e23
+b12623
+f89ff0ef
+1c12083
+4010113
+8067
+8067
+ff010113
+812423
+112623
+82002437
+2042023
+42823
+42a23
+42c23
+185b7
+42e23
+6a058593
+1b5000ef
+1855793
+f42023
+1055793
+f42223
+855793
+f42423
+a42623
+100793
+2f42023
+2f42223
+82002737
+100613
+2872783
+2c72683
+879793
+d7e7b3
+3072683
+879793
+d7e7b3
+3472683
+879793
+d7e7b3
+79a63
+c12083
+812403
+1010113
+8067
+2c72223
+fc1ff06f
+50023
+8067
+820027b7
+8107a703
+277793
+79863
+177713
+4071e63
+8067
+10007b7
+307a803
+10005b7
+820026b7
+1000637
+2b858593
+200893
+8086a783
+ff7f793
+fc0798e3
+3462783
+178793
+7f7f793
+f80c63
+3462503
+8006a303
+2f62a23
+a58533
+650023
+8116a823
+fcdff06f
+820027b7
+100713
+80e7a823
+10007b7
+2c7a583
+10006b7
+1000737
+82002637
+2b868693
+2872783
+b78863
+80462783
+ff7f793
+78463
+8067
+2872783
+f687b3
+807c783
+80f62023
+2872783
+178793
+7f7f793
+2f72423
+fc9ff06f
+30002673
+1000737
+867613
+3072783
+70693
+1000737
+2060663
+3472603
+fef60ee3
+1000737
+2b870713
+f70733
+178793
+7f7f793
+74503
+2f6a823
+100006f
+3472703
+513
+fcf71ce3
+8067
+1000737
+10007b7
+347a783
+3072503
+40f50533
+a03533
+8067
+10006b7
+2c6a603
+160793
+7f7f793
+300025f3
+85f593
+1000737
+4058663
+2872583
+fef58ee3
+bc0025f3
+ffe5f813
+bc081073
+2872703
+e61a63
+82002837
+80482703
+ff77713
+2070663
+1000737
+2b870713
+c70733
+8a70023
+2f6a623
+bc059073
+c0006f
+2872583
+faf59ee3
+8067
+80a82023
+fe9ff06f
+10007b7
+207aa23
+10007b7
+207a823
+10007b7
+207a623
+10007b7
+207a423
+820027b7
+8107a703
+ff77713
+80e7a823
+300713
+80e7aa23
+bc0027f3
+17e793
+bc079073
+8067
+10007b7
+2c7a783
+10006b7
+286a703
+fef71ee3
+8067
+fc010113
+2112e23
+2812c23
+2912a23
+3212823
+3312623
+3412423
+3512223
+3612023
+1712e23
+1812c23
+1912a23
+1a12823
+c12623
+4c05c063
+b509b3
+50a13
+58b13
+68493
+a9f663
+fff54b13
+fff00993
+5c37
+6cb7
+a0413
+2500b93
+2000a93
+fe4c0c13
+940c8c93
+2b40006f
+1778a63
+1347463
+f40023
+140413
+2940006f
+913
+2b00713
+2d00613
+3000593
+2300513
+c12683
+168793
+f12623
+16c783
+12e78e63
+12f76063
+13578e63
+14a78063
+fc0733
+74703
+477713
+12070c63
+c10513
+b64ff0ef
+50713
+c12683
+2e00613
+fff00793
+6c583
+2c59e63
+168793
+f12623
+16c603
+cc07b3
+7c783
+47f793
+12078463
+c10513
+e12423
+b24ff0ef
+812703
+50793
+55463
+793
+c12683
+6800593
+6c603
+2b60263
+df67593
+4c00513
+a58c63
+5a00513
+a58863
+7400593
+fff00813
+2b61663
+60813
+168613
+c12623
+6c00613
+c81c63
+16c603
+1061863
+268693
+d12623
+4c00813
+c12683
+6c603
+6e00693
+2cd60a63
+cc6ee63
+6300693
+14d60a63
+ac6ea63
+2d760a63
+5800693
+2cd60c63
+1347463
+1740023
+c12783
+140713
+7c683
+2c068663
+1377463
+d400a3
+240413
+14c0006f
+c78863
+eeb794e3
+196913
+ec1ff06f
+1096913
+eb9ff06f
+496913
+eb1ff06f
+896913
+ea9ff06f
+2096913
+ea1ff06f
+2a00613
+fff00713
+ecc798e3
+4a703
+268693
+d12623
+448493
+ea075ee3
+40e00733
+1096913
+eb1ff06f
+2a00593
+793
+eeb618e3
+268693
+4a503
+d12623
+448493
+ed1ff06f
+6400693
+d60663
+6900693
+f4d618e3
+296913
+a00693
+680006f
+7300693
+14d60863
+4c6e463
+6f00693
+22d60063
+7000693
+f2d614e3
+fff00693
+d71663
+196913
+800713
+4a603
+448d13
+90813
+1000693
+40513
+98593
+9d8ff0ef
+50413
+1640006f
+7500693
+fad602e3
+7800593
+1000693
+eeb610e3
+4c00613
+1cc81863
+748493
+ff84f493
+848d13
+4a603
+1f80006f
+1097913
+a090c63
+40793
+448693
+1347663
+4a603
+c40023
+140413
+e78733
+408707b3
+8f04e63
+68493
+c12783
+178793
+f12623
+c12783
+7c783
+d40794e3
+b0663
+1b347c63
+40023
+41440533
+3c12083
+3812403
+3412483
+3012903
+2c12983
+2812a03
+2412a83
+2012b03
+1c12b83
+1812c03
+1412c83
+1012d03
+4010113
+8067
+1347463
+1540023
+140413
+fff78793
+fef048e3
+fff70793
+e04463
+100713
+40e78733
+170713
+f51ff06f
+70793
+fddff06f
+1347463
+1540023
+140413
+f55ff06f
+448d13
+4a483
+49463
+c8493
+78593
+48513
+e12423
+1097913
+d09fe0ef
+812703
+91863
+70793
+fff70713
+2f54863
+793
+2a7cc63
+50793
+55463
+793
+f40433
+e40733
+408707b3
+2f54c63
+d0493
+efdff06f
+1347463
+1540023
+140413
+fbdff06f
+f406b3
+136f863
+f48633
+64603
+c68023
+178793
+fb1ff06f
+1347463
+1540023
+140413
+fb9ff06f
+4a783
+41440733
+448493
+e7a023
+eadff06f
+c13478e3
+1740023
+c09ff06f
+4096913
+1000693
+e49ff06f
+fff78793
+f12623
+70413
+e85ff06f
+800693
+e31ff06f
+6c00613
+448d13
+e2c80ce3
+fdf87613
+5a00593
+e2b606e3
+7400613
+e2c802e3
+6800613
+297593
+e0c81ce3
+4a603
+1061613
+59863
+1065613
+90813
+dc5ff06f
+41065613
+ff5ff06f
+fe098fa3
+e4dff06f
+513
+e49ff06f
+ff010113
+112623
+812423
+912223
+50413
+58493
+28000ef
+50593
+48513
+1f4000ef
+40a40533
+c12083
+812403
+412483
+1010113
+8067
+fe010113
+112e23
+812c23
+912a23
+a058263
+50413
+8050263
+58513
+b12623
+11c000ef
+50493
+40513
+110000ef
+40a48533
+1f00793
+6a7ec63
+4f50e63
+c12583
+150513
+2000713
+40a70733
+e41733
+793
+a45433
+fff58813
+141413
+1f75613
+866633
+40c806b3
+41f6d693
+171713
+b6f433
+fff50513
+f76733
+40860433
+16f793
+fc051ae3
+171413
+f46433
+40513
+1c12083
+1812403
+1412483
+2010113
+8067
+413
+fe5ff06f
+41f55793
+41f5d713
+f54533
+e5c5b3
+ff010113
+40e585b3
+40f50533
+812423
+112623
+e7c433
+f1dff0ef
+854533
+40850533
+c12083
+812403
+1010113
+8067
+ff010113
+112623
+812423
+912223
+50413
+58493
+fa5ff0ef
+50593
+48513
+b4000ef
+40a40533
+c12083
+812403
+412483
+1010113
+8067
+ffff0737
+e57733
+173693
+469693
+1000793
+40d787b3
+10737
+f557b3
+f0070713
+e7f733
+173713
+371713
+800513
+40e50533
+a7d7b3
+f07f513
+153513
+251513
+d70733
+400693
+40a686b3
+d7d7b3
+e50733
+c7f513
+153513
+200613
+151513
+40a606b3
+d7d7b3
+17d693
+16c693
+16f693
+40d006b3
+40f607b3
+f6f7b3
+e50533
+a78533
+8067
+50793
+513
+79463
+8067
+17f713
+70463
+b50533
+159593
+17d793
+fe5ff06f
+82003028
+8200305c
+82003090
+820030c4
+82003018
+8200304c
+82003080
+820030b4
+616c6564
+203a7379
+0
+2d
+64323025
+30252d2b
+6432
+41524453
+6f6e204d
+6e752077
+20726564
+74666f73
+65726177
+6e6f6320
+6c6f7274
+a
+41524453
+6f6e204d
+6e752077
+20726564
+64726168
+65726177
+6e6f6320
+6c6f7274
+a
+78323025
+0
+783225
+746d654d
+20747365
+20737562
+6c696166
+203a6465
+252f6425
+72652064
+73726f72
+a
+746d654d
+20747365
+61746164
+69616620
+3a64656c
+2f642520
+65206425
+726f7272
+a73
+746d654d
+20747365
+72646461
+69616620
+3a64656c
+2f642520
+65206425
+726f7272
+a73
+746d654d
+20747365
+a4b4f
+736d654d
+64656570
+69725720
+3a736574
+4d642520
+20737062
+64616552
+25203a73
+70624d64
+a73
+64616552
+76656c20
+6e696c65
+a3a67
+2c64256d
+64256220
+7c203a
+6425
+207c
+74736562
+256d203a
+62202c64
+206425
+74696e49
+696c6169
+676e697a
+52445320
+2e2e4d41
+a2e
+6d315b1b
+20202020
+20202020
+20205f5f
+5f205f20
+2020205f
+5f202020
+5f5f2020
+6d305b1b
+a
+6d315b1b
+20202020
+2f202020
+20202f20
+20295f28
+5f5f5f2f
+207c205f
+2f5f2f7c
+6d305b1b
+a
+6d315b1b
+20202020
+202f2020
+2f5f5f2f
+5f202f20
+2d202f5f
+203e295f
+5b1b3c20
+a6d30
+6d315b1b
+20202020
+5f5f2f20
+5f2f5f5f
+5f5f5c2f
+5f5f5c2f
+7c2f5f2f
+5b1b7c5f
+a6d30
+6d315b1b
+42202020
+646c6975
+756f7920
+61682072
+61776472
+202c6572
+69736165
+1b21796c
+a6d305b
+0
+29632820
+706f4320
+67697279
+32207468
+2d323130
+30323032
+6a6e4520
+442d796f
+74696769
+a6c61
+29632820
+706f4320
+67697279
+32207468
+2d373030
+35313032
+4c2d4d20
+a736261
+0
+4f494220
+75622053
+20746c69
+4d206e6f
+20207961
+30322038
+30203032
+39323a31
+a36313a
+0
+67694d20
+67206e65
+73207469
+3a316168
+39636420
+36656663
+a
+74694c20
+67205865
+73207469
+3a316168
+65393720
+35333165
+a66
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+5b1b203d
+6f536d31
+305b1b43
+3d3d206d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+52786556
+76637369
+0
+6d315b1b
+1b555043
+3a6d305b
+20202020
+25202020
+20402073
+484d6425
+a7a
+6d315b1b
+1b4d4f52
+3a6d305b
+20202020
+25202020
+a424b64
+0
+6d315b1b
+4d415253
+6d305b1b
+2020203a
+25202020
+a424b64
+0
+6d315b1b
+5b1b324c
+203a6d30
+20202020
+25202020
+a424b64
+0
+6d315b1b
+4e49414d
+4d41522d
+6d305b1b
+2520203a
+a424b64
+0
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+315b1b20
+696e496d
+6c616974
+74617a69
+1b6e6f69
+206d305b
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+6f6d654d
+69207972
+6974696e
+7a696c61
+6f697461
+6166206e
+64656c69
+a
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+315b1b20
+6f6f426d
+305b1b74
+3d3d206d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+62206f4e
+20746f6f
+6964656d
+66206d75
+646e756f
+a
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+203d3d3d
+6d315b1b
+736e6f43
+1b656c6f
+206d305b
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+32395b1b
+6c6d313b
+78657469
+6d305b1b
+203e
+73250a
+6d6d6f43
+20646e61
+20746f6e
+6e756f66
+64
+1598
+15d4
+1638
+15d4
+14b8
+16f0
+44354c73
+6d4d5364
+726b656b
+a6f
+4849367a
+59633747
+36444944
+a6f
+746f6f42
+20676e69
+6d6f7266
+72657320
+2e6c6169
+a2e2e
+73657250
+20512073
+4520726f
+74204353
+6261206f
+2074726f
+746f6f62
+6d6f6320
+74656c70
+2e796c65
+a
+206f6f54
+796e616d
+6e6f6320
+75636573
+65766974
+72726520
+2c73726f
+6f626120
+6e697472
+67
+63657845
+6e697475
+6f622067
+6465746f
+6f727020
+6d617267
+20746120
+30257830
+a0a7838
+0
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+203d3d3d
+6d315b1b
+7466694c
+2166666f
+6d305b1b
+3d3d3d20
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+656d6954
+a74756f
+0
+636e6143
+656c6c65
+a64
+6f6d654d
+64207972
+3a706d75
+0
+2578300a
+20783830
+20
+78323025
+20
+202020
+2e
+6325
+4f494220
+52432053
+61702043
+64657373
+30252820
+a297838
+0
+4f494220
+52432053
+61662043
+64656c69
+78652820
+74636570
+25206465
+2c783830
+746f6720
+38302520
+a2978
+65685420
+73797320
+206d6574
+6c6c6977
+6e6f6320
+756e6974
+62202c65
+65207475
+63657078
+72702074
+656c626f
+a2e736d
+0
+74694c0a
+42205865
+2c534f49
+61766120
+62616c69
+6320656c
+616d6d6f
+3a73646e
+a
+36312d25
+202d2073
+a7325
+6e656449
+25203a74
+73
+20637263
+6464613c
+73736572
+6c3c203e
+74676e65
+3e68
+6f636e49
+63657272
+64612074
+73657264
+73
+6f636e49
+63657272
+656c2074
+6874676e
+0
+33435243
+25203a32
+783830
+73756c66
+326c5f68
+6361635f
+6568
+73756c46
+324c2068
+63616320
+6568
+73756c66
+70635f68
+63645f75
+65686361
+0
+73756c46
+50432068
+61642055
+63206174
+65686361
+0
+637263
+706d6f43
+20657475
+33435243
+666f2032
+70206120
+20747261
+7420666f
+61206568
+65726464
+73207373
+65636170
+0
+6f626572
+746f
+65736552
+72702074
+7365636f
+726f73
+6e656469
+74
+70736944
+2079616c
+6e656469
+69666974
+7265
+706c6568
+0
+6e697250
+68742074
+68207369
+706c65
+69726573
+6f626c61
+746f
+746f6f42
+61697620
+4c465320
+0
+63657250
+67726168
+6465
+6f636e49
+63657272
+6f722074
+77
+69746341
+65746176
+6f722064
+64252077
+0
+72726473
+613c2064
+65726464
+3e7373
+6f636e49
+63657272
+51442074
+0
+72726473
+72726564
+6f633c20
+3e746e75
+0
+6f636e49
+63657272
+6f632074
+746e75
+77726473
+613c2072
+65726464
+3e7373
+746d656d
+747365
+206e7552
+656d2061
+79726f6d
+73657420
+74
+6c726473
+6c657665
+0
+66726550
+206d726f
+64616572
+6972772f
+6c206574
+6c657665
+676e69
+69726473
+74696e
+72617453
+44532074
+204d4152
+74696e69
+696c6169
+69746173
+6e6f
+77726473
+72
+74697257
+44532065
+204d4152
+74736574
+74616420
+61
+72726473
+72726564
+0
+6e697250
+44532074
+204d4152
+64616572
+72726520
+73726f
+72726473
+64
+64616552
+52445320
+64204d41
+617461
+72726473
+66756264
+0
+706d7544
+52445320
+72204d41
+20646165
+66667562
+7265
+68726473
+77
+65766947
+44532073
+204d4152
+746e6f63
+206c6f72
+48206f74
+57
+73726473
+77
+65766947
+44532073
+204d4152
+746e6f63
+206c6f72
+53206f74
+57
+72726473
+776f
+63657250
+67726168
+63412f65
+61766974
+72206574
+776f
+3c20776d
+72646461
+3e737365
+61763c20
+3e65756c
+6f635b20
+5d746e75
+0
+6f636e49
+63657272
+61762074
+65756c
+3c20636d
+3e747364
+72733c20
+5b203e63
+6e756f63
+5d74
+6f636e49
+63657272
+65642074
+6e697473
+6f697461
+6461206e
+73657264
+73
+6f636e49
+63657272
+6f732074
+65637275
+64646120
+73736572
+0
+3c20726d
+72646461
+3e737365
+656c5b20
+6874676e
+5d
+636e490a
+6572726f
+6c207463
+74676e65
+68
+636d
+79706f43
+64646120
+73736572
+61707320
+6563
+776d
+74697257
+64612065
+73657264
+70732073
+656361
+726d
+64616552
+64646120
+73736572
+61707320
+6563
+732a2d25
+0
+4f9c
+10
+4fa0
+e
+4fa4
+6
+4fa8
+2
+4fac
+1
+4fb0
+85
+4fb4
+10
+4fb8
+e
+4fbc
+6
+4fc0
+2
+4fc4
+1
+4fc8
+85
+4fcc
+1
+4fd0
+f
+4fd4
+89
+4fd8
+85
+4fdc
+87
+4fe0
+88
+732a2e25
+0
+73257325
+0
+414f
+424f
+434f
+444f
+484f
+464f
+415b
+425b
+435b
+445b
+485b
+465b
+7e315b
+7e325b
+7e335b
+7e345b
+7e355b
+7e365b
+8080808
+8080808
+28282808
+8082828
+8080808
+8080808
+8080808
+8080808
+101010a0
+10101010
+10101010
+10101010
+4040404
+4040404
+10100404
+10101010
+41414110
+1414141
+1010101
+1010101
+1010101
+1010101
+10010101
+10101010
+42424210
+2424242
+2020202
+2020202
+2020202
+2020202
+10020202
+8101010
+0
+0
+0
+0
+0
+0
+0
+0
+101010a0
+10101010
+10101010
+10101010
+10101010
+10101010
+10101010
+10101010
+1010101
+1010101
+1010101
+1010101
+1010101
+10010101
+1010101
+2010101
+2020202
+2020202
+2020202
+2020202
+2020202
+10020202
+2020202
+2020202
+33323130
+37363534
+42413938
+46454443
+4a494847
+4e4d4c4b
+5251504f
+56555453
+5a595857
+0
+33323130
+37363534
+62613938
+66656463
+6a696867
+6e6d6c6b
+7271706f
+76757473
+7a797877
+0
+726f6241
+2e646574
+0
+0
+1021
+2042
+3063
+4084
+50a5
+60c6
+70e7
+8108
+9129
+a14a
+b16b
+c18c
+d1ad
+e1ce
+f1ef
+1231
+210
+3273
+2252
+52b5
+4294
+72f7
+62d6
+9339
+8318
+b37b
+a35a
+d3bd
+c39c
+f3ff
+e3de
+2462
+3443
+420
+1401
+64e6
+74c7
+44a4
+5485
+a56a
+b54b
+8528
+9509
+e5ee
+f5cf
+c5ac
+d58d
+3653
+2672
+1611
+630
+76d7
+66f6
+5695
+46b4
+b75b
+a77a
+9719
+8738
+f7df
+e7fe
+d79d
+c7bc
+48c4
+58e5
+6886
+78a7
+840
+1861
+2802
+3823
+c9cc
+d9ed
+e98e
+f9af
+8948
+9969
+a90a
+b92b
+5af5
+4ad4
+7ab7
+6a96
+1a71
+a50
+3a33
+2a12
+dbfd
+cbdc
+fbbf
+eb9e
+9b79
+8b58
+bb3b
+ab1a
+6ca6
+7c87
+4ce4
+5cc5
+2c22
+3c03
+c60
+1c41
+edae
+fd8f
+cdec
+ddcd
+ad2a
+bd0b
+8d68
+9d49
+7e97
+6eb6
+5ed5
+4ef4
+3e13
+2e32
+1e51
+e70
+ff9f
+efbe
+dfdd
+cffc
+bf1b
+af3a
+9f59
+8f78
+9188
+81a9
+b1ca
+a1eb
+d10c
+c12d
+f14e
+e16f
+1080
+a1
+30c2
+20e3
+5004
+4025
+7046
+6067
+83b9
+9398
+a3fb
+b3da
+c33d
+d31c
+e37f
+f35e
+2b1
+1290
+22f3
+32d2
+4235
+5214
+6277
+7256
+b5ea
+a5cb
+95a8
+8589
+f56e
+e54f
+d52c
+c50d
+34e2
+24c3
+14a0
+481
+7466
+6447
+5424
+4405
+a7db
+b7fa
+8799
+97b8
+e75f
+f77e
+c71d
+d73c
+26d3
+36f2
+691
+16b0
+6657
+7676
+4615
+5634
+d94c
+c96d
+f90e
+e92f
+99c8
+89e9
+b98a
+a9ab
+5844
+4865
+7806
+6827
+18c0
+8e1
+3882
+28a3
+cb7d
+db5c
+eb3f
+fb1e
+8bf9
+9bd8
+abbb
+bb9a
+4a75
+5a54
+6a37
+7a16
+af1
+1ad0
+2ab3
+3a92
+fd2e
+ed0f
+dd6c
+cd4d
+bdaa
+ad8b
+9de8
+8dc9
+7c26
+6c07
+5c64
+4c45
+3ca2
+2c83
+1ce0
+cc1
+ef1f
+ff3e
+cf5d
+df7c
+af9b
+bfba
+8fd9
+9ff8
+6e17
+7e36
+4e55
+5e74
+2e93
+3eb2
+ed1
+1ef0
+0
+77073096
+ee0e612c
+990951ba
+76dc419
+706af48f
+e963a535
+9e6495a3
+edb8832
+79dcb8a4
+e0d5e91e
+97d2d988
+9b64c2b
+7eb17cbd
+e7b82d07
+90bf1d91
+1db71064
+6ab020f2
+f3b97148
+84be41de
+1adad47d
+6ddde4eb
+f4d4b551
+83d385c7
+136c9856
+646ba8c0
+fd62f97a
+8a65c9ec
+14015c4f
+63066cd9
+fa0f3d63
+8d080df5
+3b6e20c8
+4c69105e
+d56041e4
+a2677172
+3c03e4d1
+4b04d447
+d20d85fd
+a50ab56b
+35b5a8fa
+42b2986c
+dbbbc9d6
+acbcf940
+32d86ce3
+45df5c75
+dcd60dcf
+abd13d59
+26d930ac
+51de003a
+c8d75180
+bfd06116
+21b4f4b5
+56b3c423
+cfba9599
+b8bda50f
+2802b89e
+5f058808
+c60cd9b2
+b10be924
+2f6f7c87
+58684c11
+c1611dab
+b6662d3d
+76dc4190
+1db7106
+98d220bc
+efd5102a
+71b18589
+6b6b51f
+9fbfe4a5
+e8b8d433
+7807c9a2
+f00f934
+9609a88e
+e10e9818
+7f6a0dbb
+86d3d2d
+91646c97
+e6635c01
+6b6b51f4
+1c6c6162
+856530d8
+f262004e
+6c0695ed
+1b01a57b
+8208f4c1
+f50fc457
+65b0d9c6
+12b7e950
+8bbeb8ea
+fcb9887c
+62dd1ddf
+15da2d49
+8cd37cf3
+fbd44c65
+4db26158
+3ab551ce
+a3bc0074
+d4bb30e2
+4adfa541
+3dd895d7
+a4d1c46d
+d3d6f4fb
+4369e96a
+346ed9fc
+ad678846
+da60b8d0
+44042d73
+33031de5
+aa0a4c5f
+dd0d7cc9
+5005713c
+270241aa
+be0b1010
+c90c2086
+5768b525
+206f85b3
+b966d409
+ce61e49f
+5edef90e
+29d9c998
+b0d09822
+c7d7a8b4
+59b33d17
+2eb40d81
+b7bd5c3b
+c0ba6cad
+edb88320
+9abfb3b6
+3b6e20c
+74b1d29a
+ead54739
+9dd277af
+4db2615
+73dc1683
+e3630b12
+94643b84
+d6d6a3e
+7a6a5aa8
+e40ecf0b
+9309ff9d
+a00ae27
+7d079eb1
+f00f9344
+8708a3d2
+1e01f268
+6906c2fe
+f762575d
+806567cb
+196c3671
+6e6b06e7
+fed41b76
+89d32be0
+10da7a5a
+67dd4acc
+f9b9df6f
+8ebeeff9
+17b7be43
+60b08ed5
+d6d6a3e8
+a1d1937e
+38d8c2c4
+4fdff252
+d1bb67f1
+a6bc5767
+3fb506dd
+48b2364b
+d80d2bda
+af0a1b4c
+36034af6
+41047a60
+df60efc3
+a867df55
+316e8eef
+4669be79
+cb61b38c
+bc66831a
+256fd2a0
+5268e236
+cc0c7795
+bb0b4703
+220216b9
+5505262f
+c5ba3bbe
+b2bd0b28
+2bb45a92
+5cb36a04
+c2d7ffa7
+b5d0cf31
+2cd99e8b
+5bdeae1d
+9b64c2b0
+ec63f226
+756aa39c
+26d930a
+9c0906a9
+eb0e363f
+72076785
+5005713
+95bf4a82
+e2b87a14
+7bb12bae
+cb61b38
+92d28e9b
+e5d5be0d
+7cdcefb7
+bdbdf21
+86d3d2d4
+f1d4e242
+68ddb3f8
+1fda836e
+81be16cd
+f6b9265b
+6fb077e1
+18b74777
+88085ae6
+ff0f6a70
+66063bca
+11010b5c
+8f659eff
+f862ae69
+616bffd3
+166ccf45
+a00ae278
+d70dd2ee
+4e048354
+3903b3c2
+a7672661
+d06016f7
+4969474d
+3e6e77db
+aed16a4a
+d9d65adc
+40df0b66
+37d83bf0
+a9bcae53
+debb9ec5
+47b2cf7f
+30b5ffe9
+bdbdf21c
+cabac28a
+53b39330
+24b4a3a6
+bad03605
+cdd70693
+54de5729
+23d967bf
+b3667a2e
+c4614ab8
+5d681b02
+2a6f2b94
+b40bbe37
+c30c8ea1
+5a05df1b
+2d02ef8d
+4c554e3c
+3e4c
+5998
+59a8
+59b8
+59c8
+59d8
+59e8
+59f8
+5a08
+5a18
+5a28
+5a38
+5a48
+5a58
+5a68
+5a78
+5a88
+5a98
+5aa8
+5ab8
+5ac8
+3a2c
+4b40
+4b50
+2
+1a20
+4b60
+4b74
+2
+1b64
+4b8c
+4b90
+0
+1a4c
+4bc0
+4bc8
+1
+1b28
+4bd8
+4be0
+1
+1a5c
+4bf4
+4bfc
+0
+1378
+4c0c
+4c18
+3
+9b4
+4cac
+4cb4
+4
+cac
+4cc8
+4cd4
+4
+100c
+4cf0
+4cf8
+4
+1da4
+4d14
+4d1c
+4
+1d4c
+4d34
+4d40
+4
+1c98
+4d58
+4d60
+4
+1c90
+4d70
+4d7c
+4
+550
+4d94
+4d9c
+4
+538
+4db8
+4dc0
+4
+1c14
+4ddc
+4de4
+4
+1ef4
+4eac
+4eb0
+6
+1dfc
+4ec4
+4ec8
+6
+1ff4
+4edc
+4ee0
+6
+1
+0
+dc8f66be
--- /dev/null
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:17
+//--------------------------------------------------------------------------------
+module litedram_core(
+ output reg serial_tx,
+ input wire serial_rx,
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [13:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [23:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
+);
+
+reg soc_litedramcore_soccontroller_reset_storage = 1'd0;
+reg soc_litedramcore_soccontroller_reset_re = 1'd0;
+reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896;
+reg soc_litedramcore_soccontroller_scratch_re = 1'd0;
+wire [31:0] soc_litedramcore_soccontroller_bus_errors_status;
+wire soc_litedramcore_soccontroller_bus_errors_we;
+wire soc_litedramcore_soccontroller_reset;
+wire soc_litedramcore_soccontroller_bus_error;
+reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0;
+wire soc_litedramcore_cpu_reset;
+reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0;
+wire [29:0] soc_litedramcore_cpu_ibus_adr;
+wire [31:0] soc_litedramcore_cpu_ibus_dat_w;
+wire [31:0] soc_litedramcore_cpu_ibus_dat_r;
+wire [3:0] soc_litedramcore_cpu_ibus_sel;
+wire soc_litedramcore_cpu_ibus_cyc;
+wire soc_litedramcore_cpu_ibus_stb;
+wire soc_litedramcore_cpu_ibus_ack;
+wire soc_litedramcore_cpu_ibus_we;
+wire [2:0] soc_litedramcore_cpu_ibus_cti;
+wire [1:0] soc_litedramcore_cpu_ibus_bte;
+wire soc_litedramcore_cpu_ibus_err;
+wire [29:0] soc_litedramcore_cpu_dbus_adr;
+wire [31:0] soc_litedramcore_cpu_dbus_dat_w;
+wire [31:0] soc_litedramcore_cpu_dbus_dat_r;
+wire [3:0] soc_litedramcore_cpu_dbus_sel;
+wire soc_litedramcore_cpu_dbus_cyc;
+wire soc_litedramcore_cpu_dbus_stb;
+wire soc_litedramcore_cpu_dbus_ack;
+wire soc_litedramcore_cpu_dbus_we;
+wire [2:0] soc_litedramcore_cpu_dbus_cti;
+wire [1:0] soc_litedramcore_cpu_dbus_bte;
+wire soc_litedramcore_cpu_dbus_err;
+reg [31:0] soc_litedramcore_vexriscv = 32'd0;
+wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr;
+wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w;
+wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r;
+wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel;
+wire soc_litedramcore_litedramcore_ram_bus_cyc;
+wire soc_litedramcore_litedramcore_ram_bus_stb;
+reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0;
+wire soc_litedramcore_litedramcore_ram_bus_we;
+wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti;
+wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte;
+reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0;
+wire [12:0] soc_litedramcore_litedramcore_adr;
+wire [31:0] soc_litedramcore_litedramcore_dat_r;
+wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr;
+wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w;
+wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r;
+wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel;
+wire soc_litedramcore_ram_bus_ram_bus_cyc;
+wire soc_litedramcore_ram_bus_ram_bus_stb;
+reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0;
+wire soc_litedramcore_ram_bus_ram_bus_we;
+wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti;
+wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte;
+reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0;
+wire [9:0] soc_litedramcore_ram_adr;
+wire [31:0] soc_litedramcore_ram_dat_r;
+reg [3:0] soc_litedramcore_ram_we = 4'd0;
+wire [31:0] soc_litedramcore_ram_dat_w;
+reg [31:0] soc_litedramcore_storage = 32'd4947802;
+reg soc_litedramcore_re = 1'd0;
+wire soc_litedramcore_sink_valid;
+reg soc_litedramcore_sink_ready = 1'd0;
+wire soc_litedramcore_sink_first;
+wire soc_litedramcore_sink_last;
+wire [7:0] soc_litedramcore_sink_payload_data;
+reg soc_litedramcore_uart_clk_txen = 1'd0;
+reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0;
+reg [7:0] soc_litedramcore_tx_reg = 8'd0;
+reg [3:0] soc_litedramcore_tx_bitcount = 4'd0;
+reg soc_litedramcore_tx_busy = 1'd0;
+reg soc_litedramcore_source_valid = 1'd0;
+wire soc_litedramcore_source_ready;
+reg soc_litedramcore_source_first = 1'd0;
+reg soc_litedramcore_source_last = 1'd0;
+reg [7:0] soc_litedramcore_source_payload_data = 8'd0;
+reg soc_litedramcore_uart_clk_rxen = 1'd0;
+reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0;
+wire soc_litedramcore_rx;
+reg soc_litedramcore_rx_r = 1'd0;
+reg [7:0] soc_litedramcore_rx_reg = 8'd0;
+reg [3:0] soc_litedramcore_rx_bitcount = 4'd0;
+reg soc_litedramcore_rx_busy = 1'd0;
+wire soc_litedramcore_uart_rxtx_re;
+wire [7:0] soc_litedramcore_uart_rxtx_r;
+wire soc_litedramcore_uart_rxtx_we;
+wire [7:0] soc_litedramcore_uart_rxtx_w;
+wire soc_litedramcore_uart_txfull_status;
+wire soc_litedramcore_uart_txfull_we;
+wire soc_litedramcore_uart_rxempty_status;
+wire soc_litedramcore_uart_rxempty_we;
+wire soc_litedramcore_uart_irq;
+wire soc_litedramcore_uart_tx_status;
+reg soc_litedramcore_uart_tx_pending = 1'd0;
+wire soc_litedramcore_uart_tx_trigger;
+reg soc_litedramcore_uart_tx_clear = 1'd0;
+reg soc_litedramcore_uart_tx_old_trigger = 1'd0;
+wire soc_litedramcore_uart_rx_status;
+reg soc_litedramcore_uart_rx_pending = 1'd0;
+wire soc_litedramcore_uart_rx_trigger;
+reg soc_litedramcore_uart_rx_clear = 1'd0;
+reg soc_litedramcore_uart_rx_old_trigger = 1'd0;
+wire soc_litedramcore_uart_eventmanager_status_re;
+wire [1:0] soc_litedramcore_uart_eventmanager_status_r;
+wire soc_litedramcore_uart_eventmanager_status_we;
+reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0;
+wire soc_litedramcore_uart_eventmanager_pending_re;
+wire [1:0] soc_litedramcore_uart_eventmanager_pending_r;
+wire soc_litedramcore_uart_eventmanager_pending_we;
+reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0;
+reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0;
+reg soc_litedramcore_uart_eventmanager_re = 1'd0;
+wire soc_litedramcore_uart_uart_sink_valid;
+wire soc_litedramcore_uart_uart_sink_ready;
+wire soc_litedramcore_uart_uart_sink_first;
+wire soc_litedramcore_uart_uart_sink_last;
+wire [7:0] soc_litedramcore_uart_uart_sink_payload_data;
+wire soc_litedramcore_uart_uart_source_valid;
+wire soc_litedramcore_uart_uart_source_ready;
+wire soc_litedramcore_uart_uart_source_first;
+wire soc_litedramcore_uart_uart_source_last;
+wire [7:0] soc_litedramcore_uart_uart_source_payload_data;
+wire soc_litedramcore_uart_tx_fifo_sink_valid;
+wire soc_litedramcore_uart_tx_fifo_sink_ready;
+reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0;
+reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0;
+wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data;
+wire soc_litedramcore_uart_tx_fifo_source_valid;
+wire soc_litedramcore_uart_tx_fifo_source_ready;
+wire soc_litedramcore_uart_tx_fifo_source_first;
+wire soc_litedramcore_uart_tx_fifo_source_last;
+wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data;
+wire soc_litedramcore_uart_tx_fifo_re;
+reg soc_litedramcore_uart_tx_fifo_readable = 1'd0;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_we;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_writable;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_re;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_readable;
+wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din;
+wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0;
+reg soc_litedramcore_uart_tx_fifo_replace = 1'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0;
+wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r;
+wire soc_litedramcore_uart_tx_fifo_wrport_we;
+wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w;
+wire soc_litedramcore_uart_tx_fifo_do_read;
+wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr;
+wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r;
+wire soc_litedramcore_uart_tx_fifo_rdport_re;
+wire [4:0] soc_litedramcore_uart_tx_fifo_level1;
+wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data;
+wire soc_litedramcore_uart_tx_fifo_fifo_in_first;
+wire soc_litedramcore_uart_tx_fifo_fifo_in_last;
+wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
+wire soc_litedramcore_uart_tx_fifo_fifo_out_first;
+wire soc_litedramcore_uart_tx_fifo_fifo_out_last;
+wire soc_litedramcore_uart_rx_fifo_sink_valid;
+wire soc_litedramcore_uart_rx_fifo_sink_ready;
+wire soc_litedramcore_uart_rx_fifo_sink_first;
+wire soc_litedramcore_uart_rx_fifo_sink_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data;
+wire soc_litedramcore_uart_rx_fifo_source_valid;
+wire soc_litedramcore_uart_rx_fifo_source_ready;
+wire soc_litedramcore_uart_rx_fifo_source_first;
+wire soc_litedramcore_uart_rx_fifo_source_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data;
+wire soc_litedramcore_uart_rx_fifo_re;
+reg soc_litedramcore_uart_rx_fifo_readable = 1'd0;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_we;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_writable;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_re;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_readable;
+wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din;
+wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0;
+reg soc_litedramcore_uart_rx_fifo_replace = 1'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0;
+wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r;
+wire soc_litedramcore_uart_rx_fifo_wrport_we;
+wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w;
+wire soc_litedramcore_uart_rx_fifo_do_read;
+wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr;
+wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r;
+wire soc_litedramcore_uart_rx_fifo_rdport_re;
+wire [4:0] soc_litedramcore_uart_rx_fifo_level1;
+wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data;
+wire soc_litedramcore_uart_rx_fifo_fifo_in_first;
+wire soc_litedramcore_uart_rx_fifo_fifo_in_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
+wire soc_litedramcore_uart_rx_fifo_fifo_out_first;
+wire soc_litedramcore_uart_rx_fifo_fifo_out_last;
+reg soc_litedramcore_uart_reset = 1'd0;
+reg [31:0] soc_litedramcore_timer_load_storage = 32'd0;
+reg soc_litedramcore_timer_load_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0;
+reg soc_litedramcore_timer_reload_re = 1'd0;
+reg soc_litedramcore_timer_en_storage = 1'd0;
+reg soc_litedramcore_timer_en_re = 1'd0;
+reg soc_litedramcore_timer_update_value_storage = 1'd0;
+reg soc_litedramcore_timer_update_value_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_value_status = 32'd0;
+wire soc_litedramcore_timer_value_we;
+wire soc_litedramcore_timer_irq;
+wire soc_litedramcore_timer_zero_status;
+reg soc_litedramcore_timer_zero_pending = 1'd0;
+wire soc_litedramcore_timer_zero_trigger;
+reg soc_litedramcore_timer_zero_clear = 1'd0;
+reg soc_litedramcore_timer_zero_old_trigger = 1'd0;
+wire soc_litedramcore_timer_eventmanager_status_re;
+wire soc_litedramcore_timer_eventmanager_status_r;
+wire soc_litedramcore_timer_eventmanager_status_we;
+wire soc_litedramcore_timer_eventmanager_status_w;
+wire soc_litedramcore_timer_eventmanager_pending_re;
+wire soc_litedramcore_timer_eventmanager_pending_r;
+wire soc_litedramcore_timer_eventmanager_pending_we;
+wire soc_litedramcore_timer_eventmanager_pending_w;
+reg soc_litedramcore_timer_eventmanager_storage = 1'd0;
+reg soc_litedramcore_timer_eventmanager_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_value = 32'd0;
+reg [13:0] soc_litedramcore_interface_adr = 14'd0;
+reg soc_litedramcore_interface_we = 1'd0;
+wire [7:0] soc_litedramcore_interface_dat_w;
+wire [7:0] soc_litedramcore_interface_dat_r;
+wire [29:0] soc_litedramcore_bus_wishbone_adr;
+wire [31:0] soc_litedramcore_bus_wishbone_dat_w;
+wire [31:0] soc_litedramcore_bus_wishbone_dat_r;
+wire [3:0] soc_litedramcore_bus_wishbone_sel;
+wire soc_litedramcore_bus_wishbone_cyc;
+wire soc_litedramcore_bus_wishbone_stb;
+reg soc_litedramcore_bus_wishbone_ack = 1'd0;
+wire soc_litedramcore_bus_wishbone_we;
+wire [2:0] soc_litedramcore_bus_wishbone_cti;
+wire [1:0] soc_litedramcore_bus_wishbone_bte;
+reg soc_litedramcore_bus_wishbone_err = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire soc_sys_pll_reset;
+wire soc_sys_pll_locked;
+wire soc_s7pll0_clkin;
+wire soc_s7pll0_clkout0;
+wire soc_s7pll0_clkout_buf0;
+wire soc_s7pll0_clkout1;
+wire soc_s7pll0_clkout_buf1;
+wire soc_s7pll0_clkout2;
+wire soc_s7pll0_clkout_buf2;
+wire soc_iodelay_pll_reset;
+wire soc_iodelay_pll_locked;
+wire soc_s7pll1_clkin;
+wire soc_s7pll1_clkout;
+wire soc_s7pll1_clkout_buf;
+reg [3:0] soc_reset_counter = 4'd15;
+reg soc_ic_reset = 1'd1;
+reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
+reg soc_a7ddrphy_wlevel_en_re = 1'd0;
+wire soc_a7ddrphy_wlevel_strobe_re;
+wire soc_a7ddrphy_wlevel_strobe_r;
+wire soc_a7ddrphy_wlevel_strobe_we;
+reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
+wire soc_a7ddrphy_cdly_rst_re;
+wire soc_a7ddrphy_cdly_rst_r;
+wire soc_a7ddrphy_cdly_rst_we;
+reg soc_a7ddrphy_cdly_rst_w = 1'd0;
+wire soc_a7ddrphy_cdly_inc_re;
+wire soc_a7ddrphy_cdly_inc_r;
+wire soc_a7ddrphy_cdly_inc_we;
+reg soc_a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
+reg soc_a7ddrphy_dly_sel_re = 1'd0;
+wire soc_a7ddrphy_rdly_dq_rst_re;
+wire soc_a7ddrphy_rdly_dq_rst_r;
+wire soc_a7ddrphy_rdly_dq_rst_we;
+reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_inc_re;
+wire soc_a7ddrphy_rdly_dq_inc_r;
+wire soc_a7ddrphy_rdly_dq_inc_we;
+reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p0_address;
+wire [2:0] soc_a7ddrphy_dfi_p0_bank;
+wire soc_a7ddrphy_dfi_p0_cas_n;
+wire soc_a7ddrphy_dfi_p0_cs_n;
+wire soc_a7ddrphy_dfi_p0_ras_n;
+wire soc_a7ddrphy_dfi_p0_we_n;
+wire soc_a7ddrphy_dfi_p0_cke;
+wire soc_a7ddrphy_dfi_p0_odt;
+wire soc_a7ddrphy_dfi_p0_reset_n;
+wire soc_a7ddrphy_dfi_p0_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
+wire soc_a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
+wire soc_a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p1_address;
+wire [2:0] soc_a7ddrphy_dfi_p1_bank;
+wire soc_a7ddrphy_dfi_p1_cas_n;
+wire soc_a7ddrphy_dfi_p1_cs_n;
+wire soc_a7ddrphy_dfi_p1_ras_n;
+wire soc_a7ddrphy_dfi_p1_we_n;
+wire soc_a7ddrphy_dfi_p1_cke;
+wire soc_a7ddrphy_dfi_p1_odt;
+wire soc_a7ddrphy_dfi_p1_reset_n;
+wire soc_a7ddrphy_dfi_p1_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
+wire soc_a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
+wire soc_a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p2_address;
+wire [2:0] soc_a7ddrphy_dfi_p2_bank;
+wire soc_a7ddrphy_dfi_p2_cas_n;
+wire soc_a7ddrphy_dfi_p2_cs_n;
+wire soc_a7ddrphy_dfi_p2_ras_n;
+wire soc_a7ddrphy_dfi_p2_we_n;
+wire soc_a7ddrphy_dfi_p2_cke;
+wire soc_a7ddrphy_dfi_p2_odt;
+wire soc_a7ddrphy_dfi_p2_reset_n;
+wire soc_a7ddrphy_dfi_p2_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
+wire soc_a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
+wire soc_a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] soc_a7ddrphy_dfi_p3_address;
+wire [2:0] soc_a7ddrphy_dfi_p3_bank;
+wire soc_a7ddrphy_dfi_p3_cas_n;
+wire soc_a7ddrphy_dfi_p3_cs_n;
+wire soc_a7ddrphy_dfi_p3_ras_n;
+wire soc_a7ddrphy_dfi_p3_we_n;
+wire soc_a7ddrphy_dfi_p3_cke;
+wire soc_a7ddrphy_dfi_p3_odt;
+wire soc_a7ddrphy_dfi_p3_reset_n;
+wire soc_a7ddrphy_dfi_p3_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
+wire soc_a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
+wire soc_a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire soc_a7ddrphy_sd_clk_se_nodelay;
+reg soc_a7ddrphy_dqs_oe = 1'd0;
+reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dqspattern0;
+wire soc_a7ddrphy_dqspattern1;
+reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] soc_a7ddrphy_dqs_i;
+wire [1:0] soc_a7ddrphy_dqs_i_delayed;
+wire soc_a7ddrphy_dqs_o_no_delay0;
+wire soc_a7ddrphy_dqs_t0;
+wire soc_a7ddrphy0;
+wire soc_a7ddrphy_dqs_o_no_delay1;
+wire soc_a7ddrphy_dqs_t1;
+wire soc_a7ddrphy1;
+wire soc_a7ddrphy_dq_oe;
+reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dq_o_nodelay0;
+wire soc_a7ddrphy_dq_i_nodelay0;
+wire soc_a7ddrphy_dq_i_delayed0;
+wire soc_a7ddrphy_dq_t0;
+wire [7:0] soc_a7ddrphy_dq_i_data0;
+wire [7:0] soc_a7ddrphy_bitslip0_i;
+reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay1;
+wire soc_a7ddrphy_dq_i_nodelay1;
+wire soc_a7ddrphy_dq_i_delayed1;
+wire soc_a7ddrphy_dq_t1;
+wire [7:0] soc_a7ddrphy_dq_i_data1;
+wire [7:0] soc_a7ddrphy_bitslip1_i;
+reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay2;
+wire soc_a7ddrphy_dq_i_nodelay2;
+wire soc_a7ddrphy_dq_i_delayed2;
+wire soc_a7ddrphy_dq_t2;
+wire [7:0] soc_a7ddrphy_dq_i_data2;
+wire [7:0] soc_a7ddrphy_bitslip2_i;
+reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay3;
+wire soc_a7ddrphy_dq_i_nodelay3;
+wire soc_a7ddrphy_dq_i_delayed3;
+wire soc_a7ddrphy_dq_t3;
+wire [7:0] soc_a7ddrphy_dq_i_data3;
+wire [7:0] soc_a7ddrphy_bitslip3_i;
+reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay4;
+wire soc_a7ddrphy_dq_i_nodelay4;
+wire soc_a7ddrphy_dq_i_delayed4;
+wire soc_a7ddrphy_dq_t4;
+wire [7:0] soc_a7ddrphy_dq_i_data4;
+wire [7:0] soc_a7ddrphy_bitslip4_i;
+reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay5;
+wire soc_a7ddrphy_dq_i_nodelay5;
+wire soc_a7ddrphy_dq_i_delayed5;
+wire soc_a7ddrphy_dq_t5;
+wire [7:0] soc_a7ddrphy_dq_i_data5;
+wire [7:0] soc_a7ddrphy_bitslip5_i;
+reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay6;
+wire soc_a7ddrphy_dq_i_nodelay6;
+wire soc_a7ddrphy_dq_i_delayed6;
+wire soc_a7ddrphy_dq_t6;
+wire [7:0] soc_a7ddrphy_dq_i_data6;
+wire [7:0] soc_a7ddrphy_bitslip6_i;
+reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay7;
+wire soc_a7ddrphy_dq_i_nodelay7;
+wire soc_a7ddrphy_dq_i_delayed7;
+wire soc_a7ddrphy_dq_t7;
+wire [7:0] soc_a7ddrphy_dq_i_data7;
+wire [7:0] soc_a7ddrphy_bitslip7_i;
+reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay8;
+wire soc_a7ddrphy_dq_i_nodelay8;
+wire soc_a7ddrphy_dq_i_delayed8;
+wire soc_a7ddrphy_dq_t8;
+wire [7:0] soc_a7ddrphy_dq_i_data8;
+wire [7:0] soc_a7ddrphy_bitslip8_i;
+reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay9;
+wire soc_a7ddrphy_dq_i_nodelay9;
+wire soc_a7ddrphy_dq_i_delayed9;
+wire soc_a7ddrphy_dq_t9;
+wire [7:0] soc_a7ddrphy_dq_i_data9;
+wire [7:0] soc_a7ddrphy_bitslip9_i;
+reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay10;
+wire soc_a7ddrphy_dq_i_nodelay10;
+wire soc_a7ddrphy_dq_i_delayed10;
+wire soc_a7ddrphy_dq_t10;
+wire [7:0] soc_a7ddrphy_dq_i_data10;
+wire [7:0] soc_a7ddrphy_bitslip10_i;
+reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay11;
+wire soc_a7ddrphy_dq_i_nodelay11;
+wire soc_a7ddrphy_dq_i_delayed11;
+wire soc_a7ddrphy_dq_t11;
+wire [7:0] soc_a7ddrphy_dq_i_data11;
+wire [7:0] soc_a7ddrphy_bitslip11_i;
+reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay12;
+wire soc_a7ddrphy_dq_i_nodelay12;
+wire soc_a7ddrphy_dq_i_delayed12;
+wire soc_a7ddrphy_dq_t12;
+wire [7:0] soc_a7ddrphy_dq_i_data12;
+wire [7:0] soc_a7ddrphy_bitslip12_i;
+reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay13;
+wire soc_a7ddrphy_dq_i_nodelay13;
+wire soc_a7ddrphy_dq_i_delayed13;
+wire soc_a7ddrphy_dq_t13;
+wire [7:0] soc_a7ddrphy_dq_i_data13;
+wire [7:0] soc_a7ddrphy_bitslip13_i;
+reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay14;
+wire soc_a7ddrphy_dq_i_nodelay14;
+wire soc_a7ddrphy_dq_i_delayed14;
+wire soc_a7ddrphy_dq_t14;
+wire [7:0] soc_a7ddrphy_dq_i_data14;
+wire [7:0] soc_a7ddrphy_bitslip14_i;
+reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay15;
+wire soc_a7ddrphy_dq_i_nodelay15;
+wire soc_a7ddrphy_dq_i_delayed15;
+wire soc_a7ddrphy_dq_t15;
+wire [7:0] soc_a7ddrphy_dq_i_data15;
+wire [7:0] soc_a7ddrphy_bitslip15_i;
+reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
+wire [7:0] soc_a7ddrphy_rddata_en;
+reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] soc_a7ddrphy_wrdata_en;
+reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
+wire [13:0] soc_sdram_inti_p0_address;
+wire [2:0] soc_sdram_inti_p0_bank;
+reg soc_sdram_inti_p0_cas_n = 1'd1;
+reg soc_sdram_inti_p0_cs_n = 1'd1;
+reg soc_sdram_inti_p0_ras_n = 1'd1;
+reg soc_sdram_inti_p0_we_n = 1'd1;
+wire soc_sdram_inti_p0_cke;
+wire soc_sdram_inti_p0_odt;
+wire soc_sdram_inti_p0_reset_n;
+reg soc_sdram_inti_p0_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p0_wrdata;
+wire soc_sdram_inti_p0_wrdata_en;
+wire [3:0] soc_sdram_inti_p0_wrdata_mask;
+wire soc_sdram_inti_p0_rddata_en;
+reg [31:0] soc_sdram_inti_p0_rddata = 32'd0;
+reg soc_sdram_inti_p0_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_inti_p1_address;
+wire [2:0] soc_sdram_inti_p1_bank;
+reg soc_sdram_inti_p1_cas_n = 1'd1;
+reg soc_sdram_inti_p1_cs_n = 1'd1;
+reg soc_sdram_inti_p1_ras_n = 1'd1;
+reg soc_sdram_inti_p1_we_n = 1'd1;
+wire soc_sdram_inti_p1_cke;
+wire soc_sdram_inti_p1_odt;
+wire soc_sdram_inti_p1_reset_n;
+reg soc_sdram_inti_p1_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p1_wrdata;
+wire soc_sdram_inti_p1_wrdata_en;
+wire [3:0] soc_sdram_inti_p1_wrdata_mask;
+wire soc_sdram_inti_p1_rddata_en;
+reg [31:0] soc_sdram_inti_p1_rddata = 32'd0;
+reg soc_sdram_inti_p1_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_inti_p2_address;
+wire [2:0] soc_sdram_inti_p2_bank;
+reg soc_sdram_inti_p2_cas_n = 1'd1;
+reg soc_sdram_inti_p2_cs_n = 1'd1;
+reg soc_sdram_inti_p2_ras_n = 1'd1;
+reg soc_sdram_inti_p2_we_n = 1'd1;
+wire soc_sdram_inti_p2_cke;
+wire soc_sdram_inti_p2_odt;
+wire soc_sdram_inti_p2_reset_n;
+reg soc_sdram_inti_p2_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p2_wrdata;
+wire soc_sdram_inti_p2_wrdata_en;
+wire [3:0] soc_sdram_inti_p2_wrdata_mask;
+wire soc_sdram_inti_p2_rddata_en;
+reg [31:0] soc_sdram_inti_p2_rddata = 32'd0;
+reg soc_sdram_inti_p2_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_inti_p3_address;
+wire [2:0] soc_sdram_inti_p3_bank;
+reg soc_sdram_inti_p3_cas_n = 1'd1;
+reg soc_sdram_inti_p3_cs_n = 1'd1;
+reg soc_sdram_inti_p3_ras_n = 1'd1;
+reg soc_sdram_inti_p3_we_n = 1'd1;
+wire soc_sdram_inti_p3_cke;
+wire soc_sdram_inti_p3_odt;
+wire soc_sdram_inti_p3_reset_n;
+reg soc_sdram_inti_p3_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p3_wrdata;
+wire soc_sdram_inti_p3_wrdata_en;
+wire [3:0] soc_sdram_inti_p3_wrdata_mask;
+wire soc_sdram_inti_p3_rddata_en;
+reg [31:0] soc_sdram_inti_p3_rddata = 32'd0;
+reg soc_sdram_inti_p3_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_slave_p0_address;
+wire [2:0] soc_sdram_slave_p0_bank;
+wire soc_sdram_slave_p0_cas_n;
+wire soc_sdram_slave_p0_cs_n;
+wire soc_sdram_slave_p0_ras_n;
+wire soc_sdram_slave_p0_we_n;
+wire soc_sdram_slave_p0_cke;
+wire soc_sdram_slave_p0_odt;
+wire soc_sdram_slave_p0_reset_n;
+wire soc_sdram_slave_p0_act_n;
+wire [31:0] soc_sdram_slave_p0_wrdata;
+wire soc_sdram_slave_p0_wrdata_en;
+wire [3:0] soc_sdram_slave_p0_wrdata_mask;
+wire soc_sdram_slave_p0_rddata_en;
+reg [31:0] soc_sdram_slave_p0_rddata = 32'd0;
+reg soc_sdram_slave_p0_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_slave_p1_address;
+wire [2:0] soc_sdram_slave_p1_bank;
+wire soc_sdram_slave_p1_cas_n;
+wire soc_sdram_slave_p1_cs_n;
+wire soc_sdram_slave_p1_ras_n;
+wire soc_sdram_slave_p1_we_n;
+wire soc_sdram_slave_p1_cke;
+wire soc_sdram_slave_p1_odt;
+wire soc_sdram_slave_p1_reset_n;
+wire soc_sdram_slave_p1_act_n;
+wire [31:0] soc_sdram_slave_p1_wrdata;
+wire soc_sdram_slave_p1_wrdata_en;
+wire [3:0] soc_sdram_slave_p1_wrdata_mask;
+wire soc_sdram_slave_p1_rddata_en;
+reg [31:0] soc_sdram_slave_p1_rddata = 32'd0;
+reg soc_sdram_slave_p1_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_slave_p2_address;
+wire [2:0] soc_sdram_slave_p2_bank;
+wire soc_sdram_slave_p2_cas_n;
+wire soc_sdram_slave_p2_cs_n;
+wire soc_sdram_slave_p2_ras_n;
+wire soc_sdram_slave_p2_we_n;
+wire soc_sdram_slave_p2_cke;
+wire soc_sdram_slave_p2_odt;
+wire soc_sdram_slave_p2_reset_n;
+wire soc_sdram_slave_p2_act_n;
+wire [31:0] soc_sdram_slave_p2_wrdata;
+wire soc_sdram_slave_p2_wrdata_en;
+wire [3:0] soc_sdram_slave_p2_wrdata_mask;
+wire soc_sdram_slave_p2_rddata_en;
+reg [31:0] soc_sdram_slave_p2_rddata = 32'd0;
+reg soc_sdram_slave_p2_rddata_valid = 1'd0;
+wire [13:0] soc_sdram_slave_p3_address;
+wire [2:0] soc_sdram_slave_p3_bank;
+wire soc_sdram_slave_p3_cas_n;
+wire soc_sdram_slave_p3_cs_n;
+wire soc_sdram_slave_p3_ras_n;
+wire soc_sdram_slave_p3_we_n;
+wire soc_sdram_slave_p3_cke;
+wire soc_sdram_slave_p3_odt;
+wire soc_sdram_slave_p3_reset_n;
+wire soc_sdram_slave_p3_act_n;
+wire [31:0] soc_sdram_slave_p3_wrdata;
+wire soc_sdram_slave_p3_wrdata_en;
+wire [3:0] soc_sdram_slave_p3_wrdata_mask;
+wire soc_sdram_slave_p3_rddata_en;
+reg [31:0] soc_sdram_slave_p3_rddata = 32'd0;
+reg soc_sdram_slave_p3_rddata_valid = 1'd0;
+reg [13:0] soc_sdram_master_p0_address = 14'd0;
+reg [2:0] soc_sdram_master_p0_bank = 3'd0;
+reg soc_sdram_master_p0_cas_n = 1'd1;
+reg soc_sdram_master_p0_cs_n = 1'd1;
+reg soc_sdram_master_p0_ras_n = 1'd1;
+reg soc_sdram_master_p0_we_n = 1'd1;
+reg soc_sdram_master_p0_cke = 1'd0;
+reg soc_sdram_master_p0_odt = 1'd0;
+reg soc_sdram_master_p0_reset_n = 1'd0;
+reg soc_sdram_master_p0_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p0_wrdata = 32'd0;
+reg soc_sdram_master_p0_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0;
+reg soc_sdram_master_p0_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p0_rddata;
+wire soc_sdram_master_p0_rddata_valid;
+reg [13:0] soc_sdram_master_p1_address = 14'd0;
+reg [2:0] soc_sdram_master_p1_bank = 3'd0;
+reg soc_sdram_master_p1_cas_n = 1'd1;
+reg soc_sdram_master_p1_cs_n = 1'd1;
+reg soc_sdram_master_p1_ras_n = 1'd1;
+reg soc_sdram_master_p1_we_n = 1'd1;
+reg soc_sdram_master_p1_cke = 1'd0;
+reg soc_sdram_master_p1_odt = 1'd0;
+reg soc_sdram_master_p1_reset_n = 1'd0;
+reg soc_sdram_master_p1_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p1_wrdata = 32'd0;
+reg soc_sdram_master_p1_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0;
+reg soc_sdram_master_p1_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p1_rddata;
+wire soc_sdram_master_p1_rddata_valid;
+reg [13:0] soc_sdram_master_p2_address = 14'd0;
+reg [2:0] soc_sdram_master_p2_bank = 3'd0;
+reg soc_sdram_master_p2_cas_n = 1'd1;
+reg soc_sdram_master_p2_cs_n = 1'd1;
+reg soc_sdram_master_p2_ras_n = 1'd1;
+reg soc_sdram_master_p2_we_n = 1'd1;
+reg soc_sdram_master_p2_cke = 1'd0;
+reg soc_sdram_master_p2_odt = 1'd0;
+reg soc_sdram_master_p2_reset_n = 1'd0;
+reg soc_sdram_master_p2_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p2_wrdata = 32'd0;
+reg soc_sdram_master_p2_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0;
+reg soc_sdram_master_p2_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p2_rddata;
+wire soc_sdram_master_p2_rddata_valid;
+reg [13:0] soc_sdram_master_p3_address = 14'd0;
+reg [2:0] soc_sdram_master_p3_bank = 3'd0;
+reg soc_sdram_master_p3_cas_n = 1'd1;
+reg soc_sdram_master_p3_cs_n = 1'd1;
+reg soc_sdram_master_p3_ras_n = 1'd1;
+reg soc_sdram_master_p3_we_n = 1'd1;
+reg soc_sdram_master_p3_cke = 1'd0;
+reg soc_sdram_master_p3_odt = 1'd0;
+reg soc_sdram_master_p3_reset_n = 1'd0;
+reg soc_sdram_master_p3_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p3_wrdata = 32'd0;
+reg soc_sdram_master_p3_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0;
+reg soc_sdram_master_p3_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p3_rddata;
+wire soc_sdram_master_p3_rddata_valid;
+reg [3:0] soc_sdram_storage = 4'd0;
+reg soc_sdram_re = 1'd0;
+reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0;
+reg soc_sdram_phaseinjector0_command_re = 1'd0;
+wire soc_sdram_phaseinjector0_command_issue_re;
+wire soc_sdram_phaseinjector0_command_issue_r;
+wire soc_sdram_phaseinjector0_command_issue_we;
+reg soc_sdram_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] soc_sdram_phaseinjector0_address_storage = 14'd0;
+reg soc_sdram_phaseinjector0_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector0_status = 32'd0;
+wire soc_sdram_phaseinjector0_we;
+reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0;
+reg soc_sdram_phaseinjector1_command_re = 1'd0;
+wire soc_sdram_phaseinjector1_command_issue_re;
+wire soc_sdram_phaseinjector1_command_issue_r;
+wire soc_sdram_phaseinjector1_command_issue_we;
+reg soc_sdram_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] soc_sdram_phaseinjector1_address_storage = 14'd0;
+reg soc_sdram_phaseinjector1_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector1_status = 32'd0;
+wire soc_sdram_phaseinjector1_we;
+reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0;
+reg soc_sdram_phaseinjector2_command_re = 1'd0;
+wire soc_sdram_phaseinjector2_command_issue_re;
+wire soc_sdram_phaseinjector2_command_issue_r;
+wire soc_sdram_phaseinjector2_command_issue_we;
+reg soc_sdram_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] soc_sdram_phaseinjector2_address_storage = 14'd0;
+reg soc_sdram_phaseinjector2_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector2_status = 32'd0;
+wire soc_sdram_phaseinjector2_we;
+reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0;
+reg soc_sdram_phaseinjector3_command_re = 1'd0;
+wire soc_sdram_phaseinjector3_command_issue_re;
+wire soc_sdram_phaseinjector3_command_issue_r;
+wire soc_sdram_phaseinjector3_command_issue_we;
+reg soc_sdram_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] soc_sdram_phaseinjector3_address_storage = 14'd0;
+reg soc_sdram_phaseinjector3_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector3_status = 32'd0;
+wire soc_sdram_phaseinjector3_we;
+wire soc_sdram_interface_bank0_valid;
+wire soc_sdram_interface_bank0_ready;
+wire soc_sdram_interface_bank0_we;
+wire [20:0] soc_sdram_interface_bank0_addr;
+wire soc_sdram_interface_bank0_lock;
+wire soc_sdram_interface_bank0_wdata_ready;
+wire soc_sdram_interface_bank0_rdata_valid;
+wire soc_sdram_interface_bank1_valid;
+wire soc_sdram_interface_bank1_ready;
+wire soc_sdram_interface_bank1_we;
+wire [20:0] soc_sdram_interface_bank1_addr;
+wire soc_sdram_interface_bank1_lock;
+wire soc_sdram_interface_bank1_wdata_ready;
+wire soc_sdram_interface_bank1_rdata_valid;
+wire soc_sdram_interface_bank2_valid;
+wire soc_sdram_interface_bank2_ready;
+wire soc_sdram_interface_bank2_we;
+wire [20:0] soc_sdram_interface_bank2_addr;
+wire soc_sdram_interface_bank2_lock;
+wire soc_sdram_interface_bank2_wdata_ready;
+wire soc_sdram_interface_bank2_rdata_valid;
+wire soc_sdram_interface_bank3_valid;
+wire soc_sdram_interface_bank3_ready;
+wire soc_sdram_interface_bank3_we;
+wire [20:0] soc_sdram_interface_bank3_addr;
+wire soc_sdram_interface_bank3_lock;
+wire soc_sdram_interface_bank3_wdata_ready;
+wire soc_sdram_interface_bank3_rdata_valid;
+wire soc_sdram_interface_bank4_valid;
+wire soc_sdram_interface_bank4_ready;
+wire soc_sdram_interface_bank4_we;
+wire [20:0] soc_sdram_interface_bank4_addr;
+wire soc_sdram_interface_bank4_lock;
+wire soc_sdram_interface_bank4_wdata_ready;
+wire soc_sdram_interface_bank4_rdata_valid;
+wire soc_sdram_interface_bank5_valid;
+wire soc_sdram_interface_bank5_ready;
+wire soc_sdram_interface_bank5_we;
+wire [20:0] soc_sdram_interface_bank5_addr;
+wire soc_sdram_interface_bank5_lock;
+wire soc_sdram_interface_bank5_wdata_ready;
+wire soc_sdram_interface_bank5_rdata_valid;
+wire soc_sdram_interface_bank6_valid;
+wire soc_sdram_interface_bank6_ready;
+wire soc_sdram_interface_bank6_we;
+wire [20:0] soc_sdram_interface_bank6_addr;
+wire soc_sdram_interface_bank6_lock;
+wire soc_sdram_interface_bank6_wdata_ready;
+wire soc_sdram_interface_bank6_rdata_valid;
+wire soc_sdram_interface_bank7_valid;
+wire soc_sdram_interface_bank7_ready;
+wire soc_sdram_interface_bank7_we;
+wire [20:0] soc_sdram_interface_bank7_addr;
+wire soc_sdram_interface_bank7_lock;
+wire soc_sdram_interface_bank7_wdata_ready;
+wire soc_sdram_interface_bank7_rdata_valid;
+reg [127:0] soc_sdram_interface_wdata = 128'd0;
+reg [15:0] soc_sdram_interface_wdata_we = 16'd0;
+wire [127:0] soc_sdram_interface_rdata;
+reg [13:0] soc_sdram_dfi_p0_address = 14'd0;
+reg [2:0] soc_sdram_dfi_p0_bank = 3'd0;
+reg soc_sdram_dfi_p0_cas_n = 1'd1;
+reg soc_sdram_dfi_p0_cs_n = 1'd1;
+reg soc_sdram_dfi_p0_ras_n = 1'd1;
+reg soc_sdram_dfi_p0_we_n = 1'd1;
+wire soc_sdram_dfi_p0_cke;
+wire soc_sdram_dfi_p0_odt;
+wire soc_sdram_dfi_p0_reset_n;
+reg soc_sdram_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p0_wrdata;
+reg soc_sdram_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p0_wrdata_mask;
+reg soc_sdram_dfi_p0_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p0_rddata;
+wire soc_sdram_dfi_p0_rddata_valid;
+reg [13:0] soc_sdram_dfi_p1_address = 14'd0;
+reg [2:0] soc_sdram_dfi_p1_bank = 3'd0;
+reg soc_sdram_dfi_p1_cas_n = 1'd1;
+reg soc_sdram_dfi_p1_cs_n = 1'd1;
+reg soc_sdram_dfi_p1_ras_n = 1'd1;
+reg soc_sdram_dfi_p1_we_n = 1'd1;
+wire soc_sdram_dfi_p1_cke;
+wire soc_sdram_dfi_p1_odt;
+wire soc_sdram_dfi_p1_reset_n;
+reg soc_sdram_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p1_wrdata;
+reg soc_sdram_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p1_wrdata_mask;
+reg soc_sdram_dfi_p1_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p1_rddata;
+wire soc_sdram_dfi_p1_rddata_valid;
+reg [13:0] soc_sdram_dfi_p2_address = 14'd0;
+reg [2:0] soc_sdram_dfi_p2_bank = 3'd0;
+reg soc_sdram_dfi_p2_cas_n = 1'd1;
+reg soc_sdram_dfi_p2_cs_n = 1'd1;
+reg soc_sdram_dfi_p2_ras_n = 1'd1;
+reg soc_sdram_dfi_p2_we_n = 1'd1;
+wire soc_sdram_dfi_p2_cke;
+wire soc_sdram_dfi_p2_odt;
+wire soc_sdram_dfi_p2_reset_n;
+reg soc_sdram_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p2_wrdata;
+reg soc_sdram_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p2_wrdata_mask;
+reg soc_sdram_dfi_p2_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p2_rddata;
+wire soc_sdram_dfi_p2_rddata_valid;
+reg [13:0] soc_sdram_dfi_p3_address = 14'd0;
+reg [2:0] soc_sdram_dfi_p3_bank = 3'd0;
+reg soc_sdram_dfi_p3_cas_n = 1'd1;
+reg soc_sdram_dfi_p3_cs_n = 1'd1;
+reg soc_sdram_dfi_p3_ras_n = 1'd1;
+reg soc_sdram_dfi_p3_we_n = 1'd1;
+wire soc_sdram_dfi_p3_cke;
+wire soc_sdram_dfi_p3_odt;
+wire soc_sdram_dfi_p3_reset_n;
+reg soc_sdram_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p3_wrdata;
+reg soc_sdram_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p3_wrdata_mask;
+reg soc_sdram_dfi_p3_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p3_rddata;
+wire soc_sdram_dfi_p3_rddata_valid;
+reg soc_sdram_cmd_valid = 1'd0;
+reg soc_sdram_cmd_ready = 1'd0;
+reg soc_sdram_cmd_last = 1'd0;
+reg [13:0] soc_sdram_cmd_payload_a = 14'd0;
+reg [2:0] soc_sdram_cmd_payload_ba = 3'd0;
+reg soc_sdram_cmd_payload_cas = 1'd0;
+reg soc_sdram_cmd_payload_ras = 1'd0;
+reg soc_sdram_cmd_payload_we = 1'd0;
+reg soc_sdram_cmd_payload_is_read = 1'd0;
+reg soc_sdram_cmd_payload_is_write = 1'd0;
+wire soc_sdram_wants_refresh;
+wire soc_sdram_wants_zqcs;
+wire soc_sdram_timer_wait;
+wire soc_sdram_timer_done0;
+wire [9:0] soc_sdram_timer_count0;
+wire soc_sdram_timer_done1;
+reg [9:0] soc_sdram_timer_count1 = 10'd781;
+wire soc_sdram_postponer_req_i;
+reg soc_sdram_postponer_req_o = 1'd0;
+reg soc_sdram_postponer_count = 1'd0;
+reg soc_sdram_sequencer_start0 = 1'd0;
+wire soc_sdram_sequencer_done0;
+wire soc_sdram_sequencer_start1;
+reg soc_sdram_sequencer_done1 = 1'd0;
+reg [5:0] soc_sdram_sequencer_counter = 6'd0;
+reg soc_sdram_sequencer_count = 1'd0;
+wire soc_sdram_zqcs_timer_wait;
+wire soc_sdram_zqcs_timer_done0;
+wire [26:0] soc_sdram_zqcs_timer_count0;
+wire soc_sdram_zqcs_timer_done1;
+reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999;
+reg soc_sdram_zqcs_executer_start = 1'd0;
+reg soc_sdram_zqcs_executer_done = 1'd0;
+reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0;
+wire soc_sdram_bankmachine0_req_valid;
+wire soc_sdram_bankmachine0_req_ready;
+wire soc_sdram_bankmachine0_req_we;
+wire [20:0] soc_sdram_bankmachine0_req_addr;
+wire soc_sdram_bankmachine0_req_lock;
+reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine0_refresh_req;
+reg soc_sdram_bankmachine0_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine0_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba;
+reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine0_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine0_row = 14'd0;
+reg soc_sdram_bankmachine0_row_opened = 1'd0;
+wire soc_sdram_bankmachine0_row_hit;
+reg soc_sdram_bankmachine0_row_open = 1'd0;
+reg soc_sdram_bankmachine0_row_close = 1'd0;
+reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0;
+wire soc_sdram_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0;
+wire soc_sdram_bankmachine1_req_valid;
+wire soc_sdram_bankmachine1_req_ready;
+wire soc_sdram_bankmachine1_req_we;
+wire [20:0] soc_sdram_bankmachine1_req_addr;
+wire soc_sdram_bankmachine1_req_lock;
+reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine1_refresh_req;
+reg soc_sdram_bankmachine1_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine1_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba;
+reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine1_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine1_row = 14'd0;
+reg soc_sdram_bankmachine1_row_opened = 1'd0;
+wire soc_sdram_bankmachine1_row_hit;
+reg soc_sdram_bankmachine1_row_open = 1'd0;
+reg soc_sdram_bankmachine1_row_close = 1'd0;
+reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0;
+wire soc_sdram_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0;
+wire soc_sdram_bankmachine2_req_valid;
+wire soc_sdram_bankmachine2_req_ready;
+wire soc_sdram_bankmachine2_req_we;
+wire [20:0] soc_sdram_bankmachine2_req_addr;
+wire soc_sdram_bankmachine2_req_lock;
+reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine2_refresh_req;
+reg soc_sdram_bankmachine2_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine2_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba;
+reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine2_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine2_row = 14'd0;
+reg soc_sdram_bankmachine2_row_opened = 1'd0;
+wire soc_sdram_bankmachine2_row_hit;
+reg soc_sdram_bankmachine2_row_open = 1'd0;
+reg soc_sdram_bankmachine2_row_close = 1'd0;
+reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0;
+wire soc_sdram_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0;
+wire soc_sdram_bankmachine3_req_valid;
+wire soc_sdram_bankmachine3_req_ready;
+wire soc_sdram_bankmachine3_req_we;
+wire [20:0] soc_sdram_bankmachine3_req_addr;
+wire soc_sdram_bankmachine3_req_lock;
+reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine3_refresh_req;
+reg soc_sdram_bankmachine3_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine3_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba;
+reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine3_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine3_row = 14'd0;
+reg soc_sdram_bankmachine3_row_opened = 1'd0;
+wire soc_sdram_bankmachine3_row_hit;
+reg soc_sdram_bankmachine3_row_open = 1'd0;
+reg soc_sdram_bankmachine3_row_close = 1'd0;
+reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0;
+wire soc_sdram_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0;
+wire soc_sdram_bankmachine4_req_valid;
+wire soc_sdram_bankmachine4_req_ready;
+wire soc_sdram_bankmachine4_req_we;
+wire [20:0] soc_sdram_bankmachine4_req_addr;
+wire soc_sdram_bankmachine4_req_lock;
+reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine4_refresh_req;
+reg soc_sdram_bankmachine4_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine4_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba;
+reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine4_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine4_row = 14'd0;
+reg soc_sdram_bankmachine4_row_opened = 1'd0;
+wire soc_sdram_bankmachine4_row_hit;
+reg soc_sdram_bankmachine4_row_open = 1'd0;
+reg soc_sdram_bankmachine4_row_close = 1'd0;
+reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0;
+wire soc_sdram_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0;
+wire soc_sdram_bankmachine5_req_valid;
+wire soc_sdram_bankmachine5_req_ready;
+wire soc_sdram_bankmachine5_req_we;
+wire [20:0] soc_sdram_bankmachine5_req_addr;
+wire soc_sdram_bankmachine5_req_lock;
+reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine5_refresh_req;
+reg soc_sdram_bankmachine5_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine5_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba;
+reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine5_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine5_row = 14'd0;
+reg soc_sdram_bankmachine5_row_opened = 1'd0;
+wire soc_sdram_bankmachine5_row_hit;
+reg soc_sdram_bankmachine5_row_open = 1'd0;
+reg soc_sdram_bankmachine5_row_close = 1'd0;
+reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0;
+wire soc_sdram_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0;
+wire soc_sdram_bankmachine6_req_valid;
+wire soc_sdram_bankmachine6_req_ready;
+wire soc_sdram_bankmachine6_req_we;
+wire [20:0] soc_sdram_bankmachine6_req_addr;
+wire soc_sdram_bankmachine6_req_lock;
+reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine6_refresh_req;
+reg soc_sdram_bankmachine6_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine6_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba;
+reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine6_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine6_row = 14'd0;
+reg soc_sdram_bankmachine6_row_opened = 1'd0;
+wire soc_sdram_bankmachine6_row_hit;
+reg soc_sdram_bankmachine6_row_open = 1'd0;
+reg soc_sdram_bankmachine6_row_close = 1'd0;
+reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0;
+wire soc_sdram_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0;
+wire soc_sdram_bankmachine7_req_valid;
+wire soc_sdram_bankmachine7_req_ready;
+wire soc_sdram_bankmachine7_req_we;
+wire [20:0] soc_sdram_bankmachine7_req_addr;
+wire soc_sdram_bankmachine7_req_lock;
+reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine7_refresh_req;
+reg soc_sdram_bankmachine7_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine7_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] soc_sdram_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba;
+reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine7_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] soc_sdram_bankmachine7_row = 14'd0;
+reg soc_sdram_bankmachine7_row_opened = 1'd0;
+wire soc_sdram_bankmachine7_row_hit;
+reg soc_sdram_bankmachine7_row_open = 1'd0;
+reg soc_sdram_bankmachine7_row_close = 1'd0;
+reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0;
+wire soc_sdram_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0;
+wire soc_sdram_ras_allowed;
+wire soc_sdram_cas_allowed;
+reg soc_sdram_choose_cmd_want_reads = 1'd0;
+reg soc_sdram_choose_cmd_want_writes = 1'd0;
+reg soc_sdram_choose_cmd_want_cmds = 1'd0;
+reg soc_sdram_choose_cmd_want_activates = 1'd0;
+wire soc_sdram_choose_cmd_cmd_valid;
+reg soc_sdram_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] soc_sdram_choose_cmd_cmd_payload_a;
+wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba;
+reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
+reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
+reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0;
+wire soc_sdram_choose_cmd_cmd_payload_is_cmd;
+wire soc_sdram_choose_cmd_cmd_payload_is_read;
+wire soc_sdram_choose_cmd_cmd_payload_is_write;
+reg [7:0] soc_sdram_choose_cmd_valids = 8'd0;
+wire [7:0] soc_sdram_choose_cmd_request;
+reg [2:0] soc_sdram_choose_cmd_grant = 3'd0;
+wire soc_sdram_choose_cmd_ce;
+reg soc_sdram_choose_req_want_reads = 1'd0;
+reg soc_sdram_choose_req_want_writes = 1'd0;
+reg soc_sdram_choose_req_want_cmds = 1'd0;
+reg soc_sdram_choose_req_want_activates = 1'd0;
+wire soc_sdram_choose_req_cmd_valid;
+reg soc_sdram_choose_req_cmd_ready = 1'd0;
+wire [13:0] soc_sdram_choose_req_cmd_payload_a;
+wire [2:0] soc_sdram_choose_req_cmd_payload_ba;
+reg soc_sdram_choose_req_cmd_payload_cas = 1'd0;
+reg soc_sdram_choose_req_cmd_payload_ras = 1'd0;
+reg soc_sdram_choose_req_cmd_payload_we = 1'd0;
+wire soc_sdram_choose_req_cmd_payload_is_cmd;
+wire soc_sdram_choose_req_cmd_payload_is_read;
+wire soc_sdram_choose_req_cmd_payload_is_write;
+reg [7:0] soc_sdram_choose_req_valids = 8'd0;
+wire [7:0] soc_sdram_choose_req_request;
+reg [2:0] soc_sdram_choose_req_grant = 3'd0;
+wire soc_sdram_choose_req_ce;
+reg [13:0] soc_sdram_nop_a = 14'd0;
+reg [2:0] soc_sdram_nop_ba = 3'd0;
+reg [1:0] soc_sdram_steerer_sel0 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel1 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel2 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel3 = 2'd0;
+reg soc_sdram_steerer0 = 1'd1;
+reg soc_sdram_steerer1 = 1'd1;
+reg soc_sdram_steerer2 = 1'd1;
+reg soc_sdram_steerer3 = 1'd1;
+reg soc_sdram_steerer4 = 1'd1;
+reg soc_sdram_steerer5 = 1'd1;
+reg soc_sdram_steerer6 = 1'd1;
+reg soc_sdram_steerer7 = 1'd1;
+wire soc_sdram_trrdcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1;
+reg soc_sdram_trrdcon_count = 1'd0;
+wire soc_sdram_tfawcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1;
+wire [2:0] soc_sdram_tfawcon_count;
+reg [4:0] soc_sdram_tfawcon_window = 5'd0;
+wire soc_sdram_tccdcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1;
+reg soc_sdram_tccdcon_count = 1'd0;
+wire soc_sdram_twtrcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1;
+reg [2:0] soc_sdram_twtrcon_count = 3'd0;
+wire soc_sdram_read_available;
+wire soc_sdram_write_available;
+reg soc_sdram_en0 = 1'd0;
+wire soc_sdram_max_time0;
+reg [4:0] soc_sdram_time0 = 5'd0;
+reg soc_sdram_en1 = 1'd0;
+wire soc_sdram_max_time1;
+reg [3:0] soc_sdram_time1 = 4'd0;
+wire soc_sdram_go_to_refresh;
+reg soc_port_cmd_valid = 1'd0;
+wire soc_port_cmd_ready;
+reg soc_port_cmd_payload_we = 1'd0;
+reg [23:0] soc_port_cmd_payload_addr = 24'd0;
+wire soc_port_wdata_valid;
+wire soc_port_wdata_ready;
+wire soc_port_wdata_first;
+wire soc_port_wdata_last;
+wire [127:0] soc_port_wdata_payload_data;
+wire [15:0] soc_port_wdata_payload_we;
+wire soc_port_rdata_valid;
+wire soc_port_rdata_ready;
+reg soc_port_rdata_first = 1'd0;
+reg soc_port_rdata_last = 1'd0;
+wire [127:0] soc_port_rdata_payload_data;
+wire [29:0] soc_wb_sdram_adr;
+wire [31:0] soc_wb_sdram_dat_w;
+reg [31:0] soc_wb_sdram_dat_r = 32'd0;
+wire [3:0] soc_wb_sdram_sel;
+wire soc_wb_sdram_cyc;
+wire soc_wb_sdram_stb;
+reg soc_wb_sdram_ack = 1'd0;
+wire soc_wb_sdram_we;
+wire [2:0] soc_wb_sdram_cti;
+wire [1:0] soc_wb_sdram_bte;
+reg soc_wb_sdram_err = 1'd0;
+wire [29:0] soc_litedram_wb_adr;
+reg [127:0] soc_litedram_wb_dat_w = 128'd0;
+wire [127:0] soc_litedram_wb_dat_r;
+reg [15:0] soc_litedram_wb_sel = 16'd0;
+reg soc_litedram_wb_cyc = 1'd0;
+reg soc_litedram_wb_stb = 1'd0;
+reg soc_litedram_wb_ack = 1'd0;
+reg soc_litedram_wb_we = 1'd0;
+wire [2:0] soc_litedram_wb_cti;
+reg soc_write = 1'd0;
+reg soc_evict = 1'd0;
+reg soc_refill = 1'd0;
+reg soc_read = 1'd0;
+wire [29:0] soc_address_d;
+reg [29:0] soc_address_q = 30'd0;
+reg soc_address_ce = 1'd0;
+reg soc_address_reset = 1'd0;
+reg [1:0] soc_counter = 2'd0;
+reg soc_counter_ce = 1'd0;
+reg soc_counter_reset = 1'd0;
+wire [1:0] soc_counter_offset;
+wire soc_counter_done;
+wire [127:0] soc_cached_data;
+wire [15:0] soc_cached_sel;
+wire soc_end_of_burst;
+wire soc_need_refill_d;
+reg soc_need_refill_q = 1'd1;
+reg soc_need_refill_ce = 1'd0;
+wire soc_need_refill_reset;
+reg [31:0] soc_cached_datas_flipflop0_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop0_q = 32'd0;
+reg soc_cached_datas_ce0 = 1'd0;
+reg soc_cached_datas_reset0 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop1_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop1_q = 32'd0;
+reg soc_cached_datas_ce1 = 1'd0;
+reg soc_cached_datas_reset1 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop2_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop2_q = 32'd0;
+reg soc_cached_datas_ce2 = 1'd0;
+reg soc_cached_datas_reset2 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop3_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop3_q = 32'd0;
+reg soc_cached_datas_ce3 = 1'd0;
+reg soc_cached_datas_reset3 = 1'd0;
+wire [3:0] soc_cached_sels_flipflop0_d;
+reg [3:0] soc_cached_sels_flipflop0_q = 4'd0;
+reg soc_cached_sels_ce0 = 1'd0;
+wire soc_cached_sels_reset0;
+wire [3:0] soc_cached_sels_flipflop1_d;
+reg [3:0] soc_cached_sels_flipflop1_q = 4'd0;
+reg soc_cached_sels_ce1 = 1'd0;
+wire soc_cached_sels_reset1;
+wire [3:0] soc_cached_sels_flipflop2_d;
+reg [3:0] soc_cached_sels_flipflop2_q = 4'd0;
+reg soc_cached_sels_ce2 = 1'd0;
+wire soc_cached_sels_reset2;
+wire [3:0] soc_cached_sels_flipflop3_d;
+reg [3:0] soc_cached_sels_flipflop3_q = 4'd0;
+reg soc_cached_sels_ce3 = 1'd0;
+wire soc_cached_sels_reset3;
+reg soc_write_sel0 = 1'd0;
+reg soc_write_sel1 = 1'd0;
+reg soc_write_sel2 = 1'd0;
+reg soc_write_sel3 = 1'd0;
+wire soc_wdata_converter_sink_valid;
+wire soc_wdata_converter_sink_ready;
+reg soc_wdata_converter_sink_first = 1'd0;
+reg soc_wdata_converter_sink_last = 1'd0;
+wire [127:0] soc_wdata_converter_sink_payload_data;
+wire [15:0] soc_wdata_converter_sink_payload_we;
+wire soc_wdata_converter_source_valid;
+wire soc_wdata_converter_source_ready;
+wire soc_wdata_converter_source_first;
+wire soc_wdata_converter_source_last;
+wire [127:0] soc_wdata_converter_source_payload_data;
+wire [15:0] soc_wdata_converter_source_payload_we;
+wire soc_wdata_converter_converter_sink_valid;
+wire soc_wdata_converter_converter_sink_ready;
+wire soc_wdata_converter_converter_sink_first;
+wire soc_wdata_converter_converter_sink_last;
+wire [143:0] soc_wdata_converter_converter_sink_payload_data;
+wire soc_wdata_converter_converter_source_valid;
+wire soc_wdata_converter_converter_source_ready;
+wire soc_wdata_converter_converter_source_first;
+wire soc_wdata_converter_converter_source_last;
+wire [143:0] soc_wdata_converter_converter_source_payload_data;
+wire soc_wdata_converter_converter_source_payload_valid_token_count;
+wire soc_wdata_converter_source_source_valid;
+wire soc_wdata_converter_source_source_ready;
+wire soc_wdata_converter_source_source_first;
+wire soc_wdata_converter_source_source_last;
+wire [143:0] soc_wdata_converter_source_source_payload_data;
+wire soc_rdata_converter_sink_valid;
+wire soc_rdata_converter_sink_ready;
+wire soc_rdata_converter_sink_first;
+wire soc_rdata_converter_sink_last;
+wire [127:0] soc_rdata_converter_sink_payload_data;
+wire soc_rdata_converter_source_valid;
+wire soc_rdata_converter_source_ready;
+wire soc_rdata_converter_source_first;
+wire soc_rdata_converter_source_last;
+wire [127:0] soc_rdata_converter_source_payload_data;
+wire soc_rdata_converter_converter_sink_valid;
+wire soc_rdata_converter_converter_sink_ready;
+wire soc_rdata_converter_converter_sink_first;
+wire soc_rdata_converter_converter_sink_last;
+wire [127:0] soc_rdata_converter_converter_sink_payload_data;
+wire soc_rdata_converter_converter_source_valid;
+wire soc_rdata_converter_converter_source_ready;
+wire soc_rdata_converter_converter_source_first;
+wire soc_rdata_converter_converter_source_last;
+wire [127:0] soc_rdata_converter_converter_source_payload_data;
+wire soc_rdata_converter_converter_source_payload_valid_token_count;
+wire soc_rdata_converter_source_source_valid;
+wire soc_rdata_converter_source_source_ready;
+wire soc_rdata_converter_source_source_first;
+wire soc_rdata_converter_source_source_last;
+wire [127:0] soc_rdata_converter_source_source_payload_data;
+reg soc_count = 1'd0;
+reg soc_init_done_storage = 1'd0;
+reg soc_init_done_re = 1'd0;
+reg soc_init_error_storage = 1'd0;
+reg soc_init_error_re = 1'd0;
+wire soc_cmd_valid;
+wire soc_cmd_ready;
+wire soc_cmd_payload_we;
+wire [23:0] soc_cmd_payload_addr;
+wire soc_wdata_valid;
+wire soc_wdata_ready;
+wire [127:0] soc_wdata_payload_data;
+wire [15:0] soc_wdata_payload_we;
+wire soc_rdata_valid;
+wire soc_rdata_ready;
+wire [127:0] soc_rdata_payload_data;
+reg vns_wb2csr_state = 1'd0;
+reg vns_wb2csr_next_state = 1'd0;
+wire vns_pll_fb0;
+wire vns_pll_fb1;
+reg [1:0] vns_refresher_state = 2'd0;
+reg [1:0] vns_refresher_next_state = 2'd0;
+reg [3:0] vns_bankmachine0_state = 4'd0;
+reg [3:0] vns_bankmachine0_next_state = 4'd0;
+reg [3:0] vns_bankmachine1_state = 4'd0;
+reg [3:0] vns_bankmachine1_next_state = 4'd0;
+reg [3:0] vns_bankmachine2_state = 4'd0;
+reg [3:0] vns_bankmachine2_next_state = 4'd0;
+reg [3:0] vns_bankmachine3_state = 4'd0;
+reg [3:0] vns_bankmachine3_next_state = 4'd0;
+reg [3:0] vns_bankmachine4_state = 4'd0;
+reg [3:0] vns_bankmachine4_next_state = 4'd0;
+reg [3:0] vns_bankmachine5_state = 4'd0;
+reg [3:0] vns_bankmachine5_next_state = 4'd0;
+reg [3:0] vns_bankmachine6_state = 4'd0;
+reg [3:0] vns_bankmachine6_next_state = 4'd0;
+reg [3:0] vns_bankmachine7_state = 4'd0;
+reg [3:0] vns_bankmachine7_next_state = 4'd0;
+reg [3:0] vns_multiplexer_state = 4'd0;
+reg [3:0] vns_multiplexer_next_state = 4'd0;
+wire [1:0] vns_roundrobin0_request;
+reg vns_roundrobin0_grant = 1'd0;
+wire vns_roundrobin0_ce;
+wire [1:0] vns_roundrobin1_request;
+reg vns_roundrobin1_grant = 1'd0;
+wire vns_roundrobin1_ce;
+wire [1:0] vns_roundrobin2_request;
+reg vns_roundrobin2_grant = 1'd0;
+wire vns_roundrobin2_ce;
+wire [1:0] vns_roundrobin3_request;
+reg vns_roundrobin3_grant = 1'd0;
+wire vns_roundrobin3_ce;
+wire [1:0] vns_roundrobin4_request;
+reg vns_roundrobin4_grant = 1'd0;
+wire vns_roundrobin4_ce;
+wire [1:0] vns_roundrobin5_request;
+reg vns_roundrobin5_grant = 1'd0;
+wire vns_roundrobin5_ce;
+wire [1:0] vns_roundrobin6_request;
+reg vns_roundrobin6_grant = 1'd0;
+wire vns_roundrobin6_ce;
+wire [1:0] vns_roundrobin7_request;
+reg vns_roundrobin7_grant = 1'd0;
+wire vns_roundrobin7_ce;
+reg vns_locked0 = 1'd0;
+reg vns_locked1 = 1'd0;
+reg vns_locked2 = 1'd0;
+reg vns_locked3 = 1'd0;
+reg vns_locked4 = 1'd0;
+reg vns_locked5 = 1'd0;
+reg vns_locked6 = 1'd0;
+reg vns_locked7 = 1'd0;
+reg vns_locked8 = 1'd0;
+reg vns_locked9 = 1'd0;
+reg vns_locked10 = 1'd0;
+reg vns_locked11 = 1'd0;
+reg vns_locked12 = 1'd0;
+reg vns_locked13 = 1'd0;
+reg vns_locked14 = 1'd0;
+reg vns_locked15 = 1'd0;
+reg vns_new_master_wdata_ready0 = 1'd0;
+reg vns_new_master_wdata_ready1 = 1'd0;
+reg vns_new_master_wdata_ready2 = 1'd0;
+reg vns_new_master_wdata_ready3 = 1'd0;
+reg vns_new_master_wdata_ready4 = 1'd0;
+reg vns_new_master_wdata_ready5 = 1'd0;
+reg vns_new_master_rdata_valid0 = 1'd0;
+reg vns_new_master_rdata_valid1 = 1'd0;
+reg vns_new_master_rdata_valid2 = 1'd0;
+reg vns_new_master_rdata_valid3 = 1'd0;
+reg vns_new_master_rdata_valid4 = 1'd0;
+reg vns_new_master_rdata_valid5 = 1'd0;
+reg vns_new_master_rdata_valid6 = 1'd0;
+reg vns_new_master_rdata_valid7 = 1'd0;
+reg vns_new_master_rdata_valid8 = 1'd0;
+reg vns_new_master_rdata_valid9 = 1'd0;
+reg vns_new_master_rdata_valid10 = 1'd0;
+reg vns_new_master_rdata_valid11 = 1'd0;
+reg vns_new_master_rdata_valid12 = 1'd0;
+reg vns_new_master_rdata_valid13 = 1'd0;
+reg vns_new_master_rdata_valid14 = 1'd0;
+reg vns_new_master_rdata_valid15 = 1'd0;
+reg vns_new_master_rdata_valid16 = 1'd0;
+reg vns_new_master_rdata_valid17 = 1'd0;
+reg [2:0] vns_converter_state = 3'd0;
+reg [2:0] vns_converter_next_state = 3'd0;
+reg [1:0] vns_litedramwishbone2native_state = 2'd0;
+reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
+reg soc_count_next_value = 1'd0;
+reg soc_count_next_value_ce = 1'd0;
+wire [29:0] vns_shared_adr;
+wire [31:0] vns_shared_dat_w;
+reg [31:0] vns_shared_dat_r = 32'd0;
+wire [3:0] vns_shared_sel;
+wire vns_shared_cyc;
+wire vns_shared_stb;
+reg vns_shared_ack = 1'd0;
+wire vns_shared_we;
+wire [2:0] vns_shared_cti;
+wire [1:0] vns_shared_bte;
+wire vns_shared_err;
+wire [1:0] vns_request;
+reg vns_grant = 1'd0;
+reg [3:0] vns_slave_sel = 4'd0;
+reg [3:0] vns_slave_sel_r = 4'd0;
+reg vns_error = 1'd0;
+wire vns_wait;
+wire vns_done;
+reg [19:0] vns_count = 20'd1000000;
+wire [13:0] vns_interface0_bank_bus_adr;
+wire vns_interface0_bank_bus_we;
+wire [7:0] vns_interface0_bank_bus_dat_w;
+reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0;
+wire vns_csrbank0_reset0_re;
+wire vns_csrbank0_reset0_r;
+wire vns_csrbank0_reset0_we;
+wire vns_csrbank0_reset0_w;
+wire vns_csrbank0_scratch3_re;
+wire [7:0] vns_csrbank0_scratch3_r;
+wire vns_csrbank0_scratch3_we;
+wire [7:0] vns_csrbank0_scratch3_w;
+wire vns_csrbank0_scratch2_re;
+wire [7:0] vns_csrbank0_scratch2_r;
+wire vns_csrbank0_scratch2_we;
+wire [7:0] vns_csrbank0_scratch2_w;
+wire vns_csrbank0_scratch1_re;
+wire [7:0] vns_csrbank0_scratch1_r;
+wire vns_csrbank0_scratch1_we;
+wire [7:0] vns_csrbank0_scratch1_w;
+wire vns_csrbank0_scratch0_re;
+wire [7:0] vns_csrbank0_scratch0_r;
+wire vns_csrbank0_scratch0_we;
+wire [7:0] vns_csrbank0_scratch0_w;
+wire vns_csrbank0_bus_errors3_re;
+wire [7:0] vns_csrbank0_bus_errors3_r;
+wire vns_csrbank0_bus_errors3_we;
+wire [7:0] vns_csrbank0_bus_errors3_w;
+wire vns_csrbank0_bus_errors2_re;
+wire [7:0] vns_csrbank0_bus_errors2_r;
+wire vns_csrbank0_bus_errors2_we;
+wire [7:0] vns_csrbank0_bus_errors2_w;
+wire vns_csrbank0_bus_errors1_re;
+wire [7:0] vns_csrbank0_bus_errors1_r;
+wire vns_csrbank0_bus_errors1_we;
+wire [7:0] vns_csrbank0_bus_errors1_w;
+wire vns_csrbank0_bus_errors0_re;
+wire [7:0] vns_csrbank0_bus_errors0_r;
+wire vns_csrbank0_bus_errors0_we;
+wire [7:0] vns_csrbank0_bus_errors0_w;
+wire vns_csrbank0_sel;
+wire [13:0] vns_interface1_bank_bus_adr;
+wire vns_interface1_bank_bus_we;
+wire [7:0] vns_interface1_bank_bus_dat_w;
+reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0;
+wire vns_csrbank1_init_done0_re;
+wire vns_csrbank1_init_done0_r;
+wire vns_csrbank1_init_done0_we;
+wire vns_csrbank1_init_done0_w;
+wire vns_csrbank1_init_error0_re;
+wire vns_csrbank1_init_error0_r;
+wire vns_csrbank1_init_error0_we;
+wire vns_csrbank1_init_error0_w;
+wire vns_csrbank1_sel;
+wire [13:0] vns_interface2_bank_bus_adr;
+wire vns_interface2_bank_bus_we;
+wire [7:0] vns_interface2_bank_bus_dat_w;
+reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0;
+wire vns_csrbank2_half_sys8x_taps0_re;
+wire [4:0] vns_csrbank2_half_sys8x_taps0_r;
+wire vns_csrbank2_half_sys8x_taps0_we;
+wire [4:0] vns_csrbank2_half_sys8x_taps0_w;
+wire vns_csrbank2_wlevel_en0_re;
+wire vns_csrbank2_wlevel_en0_r;
+wire vns_csrbank2_wlevel_en0_we;
+wire vns_csrbank2_wlevel_en0_w;
+wire vns_csrbank2_dly_sel0_re;
+wire [1:0] vns_csrbank2_dly_sel0_r;
+wire vns_csrbank2_dly_sel0_we;
+wire [1:0] vns_csrbank2_dly_sel0_w;
+wire vns_csrbank2_sel;
+wire [13:0] vns_interface3_bank_bus_adr;
+wire vns_interface3_bank_bus_we;
+wire [7:0] vns_interface3_bank_bus_dat_w;
+reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0;
+wire vns_csrbank3_dfii_control0_re;
+wire [3:0] vns_csrbank3_dfii_control0_r;
+wire vns_csrbank3_dfii_control0_we;
+wire [3:0] vns_csrbank3_dfii_control0_w;
+wire vns_csrbank3_dfii_pi0_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi0_command0_r;
+wire vns_csrbank3_dfii_pi0_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi0_command0_w;
+wire vns_csrbank3_dfii_pi0_address1_re;
+wire [5:0] vns_csrbank3_dfii_pi0_address1_r;
+wire vns_csrbank3_dfii_pi0_address1_we;
+wire [5:0] vns_csrbank3_dfii_pi0_address1_w;
+wire vns_csrbank3_dfii_pi0_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_address0_r;
+wire vns_csrbank3_dfii_pi0_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_address0_w;
+wire vns_csrbank3_dfii_pi0_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r;
+wire vns_csrbank3_dfii_pi0_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w;
+wire vns_csrbank3_dfii_pi0_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r;
+wire vns_csrbank3_dfii_pi0_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w;
+wire vns_csrbank3_dfii_pi0_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r;
+wire vns_csrbank3_dfii_pi0_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w;
+wire vns_csrbank3_dfii_pi0_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r;
+wire vns_csrbank3_dfii_pi0_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w;
+wire vns_csrbank3_dfii_pi0_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r;
+wire vns_csrbank3_dfii_pi0_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w;
+wire vns_csrbank3_dfii_pi0_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r;
+wire vns_csrbank3_dfii_pi0_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w;
+wire vns_csrbank3_dfii_pi0_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r;
+wire vns_csrbank3_dfii_pi0_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w;
+wire vns_csrbank3_dfii_pi0_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r;
+wire vns_csrbank3_dfii_pi0_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w;
+wire vns_csrbank3_dfii_pi0_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r;
+wire vns_csrbank3_dfii_pi0_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w;
+wire vns_csrbank3_dfii_pi1_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi1_command0_r;
+wire vns_csrbank3_dfii_pi1_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi1_command0_w;
+wire vns_csrbank3_dfii_pi1_address1_re;
+wire [5:0] vns_csrbank3_dfii_pi1_address1_r;
+wire vns_csrbank3_dfii_pi1_address1_we;
+wire [5:0] vns_csrbank3_dfii_pi1_address1_w;
+wire vns_csrbank3_dfii_pi1_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_address0_r;
+wire vns_csrbank3_dfii_pi1_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_address0_w;
+wire vns_csrbank3_dfii_pi1_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r;
+wire vns_csrbank3_dfii_pi1_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w;
+wire vns_csrbank3_dfii_pi1_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r;
+wire vns_csrbank3_dfii_pi1_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w;
+wire vns_csrbank3_dfii_pi1_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r;
+wire vns_csrbank3_dfii_pi1_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w;
+wire vns_csrbank3_dfii_pi1_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r;
+wire vns_csrbank3_dfii_pi1_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w;
+wire vns_csrbank3_dfii_pi1_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r;
+wire vns_csrbank3_dfii_pi1_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w;
+wire vns_csrbank3_dfii_pi1_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r;
+wire vns_csrbank3_dfii_pi1_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w;
+wire vns_csrbank3_dfii_pi1_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r;
+wire vns_csrbank3_dfii_pi1_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w;
+wire vns_csrbank3_dfii_pi1_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r;
+wire vns_csrbank3_dfii_pi1_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w;
+wire vns_csrbank3_dfii_pi1_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r;
+wire vns_csrbank3_dfii_pi1_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w;
+wire vns_csrbank3_dfii_pi2_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi2_command0_r;
+wire vns_csrbank3_dfii_pi2_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi2_command0_w;
+wire vns_csrbank3_dfii_pi2_address1_re;
+wire [5:0] vns_csrbank3_dfii_pi2_address1_r;
+wire vns_csrbank3_dfii_pi2_address1_we;
+wire [5:0] vns_csrbank3_dfii_pi2_address1_w;
+wire vns_csrbank3_dfii_pi2_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_address0_r;
+wire vns_csrbank3_dfii_pi2_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_address0_w;
+wire vns_csrbank3_dfii_pi2_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r;
+wire vns_csrbank3_dfii_pi2_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w;
+wire vns_csrbank3_dfii_pi2_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r;
+wire vns_csrbank3_dfii_pi2_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w;
+wire vns_csrbank3_dfii_pi2_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r;
+wire vns_csrbank3_dfii_pi2_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w;
+wire vns_csrbank3_dfii_pi2_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r;
+wire vns_csrbank3_dfii_pi2_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w;
+wire vns_csrbank3_dfii_pi2_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r;
+wire vns_csrbank3_dfii_pi2_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w;
+wire vns_csrbank3_dfii_pi2_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r;
+wire vns_csrbank3_dfii_pi2_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w;
+wire vns_csrbank3_dfii_pi2_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r;
+wire vns_csrbank3_dfii_pi2_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w;
+wire vns_csrbank3_dfii_pi2_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r;
+wire vns_csrbank3_dfii_pi2_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w;
+wire vns_csrbank3_dfii_pi2_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r;
+wire vns_csrbank3_dfii_pi2_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w;
+wire vns_csrbank3_dfii_pi3_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi3_command0_r;
+wire vns_csrbank3_dfii_pi3_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi3_command0_w;
+wire vns_csrbank3_dfii_pi3_address1_re;
+wire [5:0] vns_csrbank3_dfii_pi3_address1_r;
+wire vns_csrbank3_dfii_pi3_address1_we;
+wire [5:0] vns_csrbank3_dfii_pi3_address1_w;
+wire vns_csrbank3_dfii_pi3_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_address0_r;
+wire vns_csrbank3_dfii_pi3_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_address0_w;
+wire vns_csrbank3_dfii_pi3_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r;
+wire vns_csrbank3_dfii_pi3_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w;
+wire vns_csrbank3_dfii_pi3_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r;
+wire vns_csrbank3_dfii_pi3_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w;
+wire vns_csrbank3_dfii_pi3_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r;
+wire vns_csrbank3_dfii_pi3_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w;
+wire vns_csrbank3_dfii_pi3_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r;
+wire vns_csrbank3_dfii_pi3_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w;
+wire vns_csrbank3_dfii_pi3_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r;
+wire vns_csrbank3_dfii_pi3_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w;
+wire vns_csrbank3_dfii_pi3_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r;
+wire vns_csrbank3_dfii_pi3_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w;
+wire vns_csrbank3_dfii_pi3_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r;
+wire vns_csrbank3_dfii_pi3_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w;
+wire vns_csrbank3_dfii_pi3_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r;
+wire vns_csrbank3_dfii_pi3_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w;
+wire vns_csrbank3_dfii_pi3_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r;
+wire vns_csrbank3_dfii_pi3_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w;
+wire vns_csrbank3_sel;
+wire [13:0] vns_interface4_bank_bus_adr;
+wire vns_interface4_bank_bus_we;
+wire [7:0] vns_interface4_bank_bus_dat_w;
+reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0;
+wire vns_csrbank4_load3_re;
+wire [7:0] vns_csrbank4_load3_r;
+wire vns_csrbank4_load3_we;
+wire [7:0] vns_csrbank4_load3_w;
+wire vns_csrbank4_load2_re;
+wire [7:0] vns_csrbank4_load2_r;
+wire vns_csrbank4_load2_we;
+wire [7:0] vns_csrbank4_load2_w;
+wire vns_csrbank4_load1_re;
+wire [7:0] vns_csrbank4_load1_r;
+wire vns_csrbank4_load1_we;
+wire [7:0] vns_csrbank4_load1_w;
+wire vns_csrbank4_load0_re;
+wire [7:0] vns_csrbank4_load0_r;
+wire vns_csrbank4_load0_we;
+wire [7:0] vns_csrbank4_load0_w;
+wire vns_csrbank4_reload3_re;
+wire [7:0] vns_csrbank4_reload3_r;
+wire vns_csrbank4_reload3_we;
+wire [7:0] vns_csrbank4_reload3_w;
+wire vns_csrbank4_reload2_re;
+wire [7:0] vns_csrbank4_reload2_r;
+wire vns_csrbank4_reload2_we;
+wire [7:0] vns_csrbank4_reload2_w;
+wire vns_csrbank4_reload1_re;
+wire [7:0] vns_csrbank4_reload1_r;
+wire vns_csrbank4_reload1_we;
+wire [7:0] vns_csrbank4_reload1_w;
+wire vns_csrbank4_reload0_re;
+wire [7:0] vns_csrbank4_reload0_r;
+wire vns_csrbank4_reload0_we;
+wire [7:0] vns_csrbank4_reload0_w;
+wire vns_csrbank4_en0_re;
+wire vns_csrbank4_en0_r;
+wire vns_csrbank4_en0_we;
+wire vns_csrbank4_en0_w;
+wire vns_csrbank4_update_value0_re;
+wire vns_csrbank4_update_value0_r;
+wire vns_csrbank4_update_value0_we;
+wire vns_csrbank4_update_value0_w;
+wire vns_csrbank4_value3_re;
+wire [7:0] vns_csrbank4_value3_r;
+wire vns_csrbank4_value3_we;
+wire [7:0] vns_csrbank4_value3_w;
+wire vns_csrbank4_value2_re;
+wire [7:0] vns_csrbank4_value2_r;
+wire vns_csrbank4_value2_we;
+wire [7:0] vns_csrbank4_value2_w;
+wire vns_csrbank4_value1_re;
+wire [7:0] vns_csrbank4_value1_r;
+wire vns_csrbank4_value1_we;
+wire [7:0] vns_csrbank4_value1_w;
+wire vns_csrbank4_value0_re;
+wire [7:0] vns_csrbank4_value0_r;
+wire vns_csrbank4_value0_we;
+wire [7:0] vns_csrbank4_value0_w;
+wire vns_csrbank4_ev_enable0_re;
+wire vns_csrbank4_ev_enable0_r;
+wire vns_csrbank4_ev_enable0_we;
+wire vns_csrbank4_ev_enable0_w;
+wire vns_csrbank4_sel;
+wire [13:0] vns_interface5_bank_bus_adr;
+wire vns_interface5_bank_bus_we;
+wire [7:0] vns_interface5_bank_bus_dat_w;
+reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0;
+wire vns_csrbank5_txfull_re;
+wire vns_csrbank5_txfull_r;
+wire vns_csrbank5_txfull_we;
+wire vns_csrbank5_txfull_w;
+wire vns_csrbank5_rxempty_re;
+wire vns_csrbank5_rxempty_r;
+wire vns_csrbank5_rxempty_we;
+wire vns_csrbank5_rxempty_w;
+wire vns_csrbank5_ev_enable0_re;
+wire [1:0] vns_csrbank5_ev_enable0_r;
+wire vns_csrbank5_ev_enable0_we;
+wire [1:0] vns_csrbank5_ev_enable0_w;
+wire vns_csrbank5_sel;
+wire [13:0] vns_interface6_bank_bus_adr;
+wire vns_interface6_bank_bus_we;
+wire [7:0] vns_interface6_bank_bus_dat_w;
+reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0;
+wire vns_csrbank6_tuning_word3_re;
+wire [7:0] vns_csrbank6_tuning_word3_r;
+wire vns_csrbank6_tuning_word3_we;
+wire [7:0] vns_csrbank6_tuning_word3_w;
+wire vns_csrbank6_tuning_word2_re;
+wire [7:0] vns_csrbank6_tuning_word2_r;
+wire vns_csrbank6_tuning_word2_we;
+wire [7:0] vns_csrbank6_tuning_word2_w;
+wire vns_csrbank6_tuning_word1_re;
+wire [7:0] vns_csrbank6_tuning_word1_r;
+wire vns_csrbank6_tuning_word1_we;
+wire [7:0] vns_csrbank6_tuning_word1_w;
+wire vns_csrbank6_tuning_word0_re;
+wire [7:0] vns_csrbank6_tuning_word0_r;
+wire vns_csrbank6_tuning_word0_we;
+wire [7:0] vns_csrbank6_tuning_word0_w;
+wire vns_csrbank6_sel;
+wire [13:0] vns_adr;
+wire vns_we;
+wire [7:0] vns_dat_w;
+wire [7:0] vns_dat_r;
+reg vns_rhs_array_muxed0 = 1'd0;
+reg [13:0] vns_rhs_array_muxed1 = 14'd0;
+reg [2:0] vns_rhs_array_muxed2 = 3'd0;
+reg vns_rhs_array_muxed3 = 1'd0;
+reg vns_rhs_array_muxed4 = 1'd0;
+reg vns_rhs_array_muxed5 = 1'd0;
+reg vns_t_array_muxed0 = 1'd0;
+reg vns_t_array_muxed1 = 1'd0;
+reg vns_t_array_muxed2 = 1'd0;
+reg vns_rhs_array_muxed6 = 1'd0;
+reg [13:0] vns_rhs_array_muxed7 = 14'd0;
+reg [2:0] vns_rhs_array_muxed8 = 3'd0;
+reg vns_rhs_array_muxed9 = 1'd0;
+reg vns_rhs_array_muxed10 = 1'd0;
+reg vns_rhs_array_muxed11 = 1'd0;
+reg vns_t_array_muxed3 = 1'd0;
+reg vns_t_array_muxed4 = 1'd0;
+reg vns_t_array_muxed5 = 1'd0;
+reg [20:0] vns_rhs_array_muxed12 = 21'd0;
+reg vns_rhs_array_muxed13 = 1'd0;
+reg vns_rhs_array_muxed14 = 1'd0;
+reg [20:0] vns_rhs_array_muxed15 = 21'd0;
+reg vns_rhs_array_muxed16 = 1'd0;
+reg vns_rhs_array_muxed17 = 1'd0;
+reg [20:0] vns_rhs_array_muxed18 = 21'd0;
+reg vns_rhs_array_muxed19 = 1'd0;
+reg vns_rhs_array_muxed20 = 1'd0;
+reg [20:0] vns_rhs_array_muxed21 = 21'd0;
+reg vns_rhs_array_muxed22 = 1'd0;
+reg vns_rhs_array_muxed23 = 1'd0;
+reg [20:0] vns_rhs_array_muxed24 = 21'd0;
+reg vns_rhs_array_muxed25 = 1'd0;
+reg vns_rhs_array_muxed26 = 1'd0;
+reg [20:0] vns_rhs_array_muxed27 = 21'd0;
+reg vns_rhs_array_muxed28 = 1'd0;
+reg vns_rhs_array_muxed29 = 1'd0;
+reg [20:0] vns_rhs_array_muxed30 = 21'd0;
+reg vns_rhs_array_muxed31 = 1'd0;
+reg vns_rhs_array_muxed32 = 1'd0;
+reg [20:0] vns_rhs_array_muxed33 = 21'd0;
+reg vns_rhs_array_muxed34 = 1'd0;
+reg vns_rhs_array_muxed35 = 1'd0;
+reg [29:0] vns_rhs_array_muxed36 = 30'd0;
+reg [31:0] vns_rhs_array_muxed37 = 32'd0;
+reg [3:0] vns_rhs_array_muxed38 = 4'd0;
+reg vns_rhs_array_muxed39 = 1'd0;
+reg vns_rhs_array_muxed40 = 1'd0;
+reg vns_rhs_array_muxed41 = 1'd0;
+reg [2:0] vns_rhs_array_muxed42 = 3'd0;
+reg [1:0] vns_rhs_array_muxed43 = 2'd0;
+reg [2:0] vns_array_muxed0 = 3'd0;
+reg [13:0] vns_array_muxed1 = 14'd0;
+reg vns_array_muxed2 = 1'd0;
+reg vns_array_muxed3 = 1'd0;
+reg vns_array_muxed4 = 1'd0;
+reg vns_array_muxed5 = 1'd0;
+reg vns_array_muxed6 = 1'd0;
+reg [2:0] vns_array_muxed7 = 3'd0;
+reg [13:0] vns_array_muxed8 = 14'd0;
+reg vns_array_muxed9 = 1'd0;
+reg vns_array_muxed10 = 1'd0;
+reg vns_array_muxed11 = 1'd0;
+reg vns_array_muxed12 = 1'd0;
+reg vns_array_muxed13 = 1'd0;
+reg [2:0] vns_array_muxed14 = 3'd0;
+reg [13:0] vns_array_muxed15 = 14'd0;
+reg vns_array_muxed16 = 1'd0;
+reg vns_array_muxed17 = 1'd0;
+reg vns_array_muxed18 = 1'd0;
+reg vns_array_muxed19 = 1'd0;
+reg vns_array_muxed20 = 1'd0;
+reg [2:0] vns_array_muxed21 = 3'd0;
+reg [13:0] vns_array_muxed22 = 14'd0;
+reg vns_array_muxed23 = 1'd0;
+reg vns_array_muxed24 = 1'd0;
+reg vns_array_muxed25 = 1'd0;
+reg vns_array_muxed26 = 1'd0;
+reg vns_array_muxed27 = 1'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0;
+wire vns_xilinxasyncresetsynchronizerimpl0;
+wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1;
+wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1_expr;
+wire vns_xilinxasyncresetsynchronizerimpl2;
+wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2_expr;
+wire vns_xilinxasyncresetsynchronizerimpl3;
+wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset;
+assign init_done = soc_init_done_storage;
+assign init_error = soc_init_error_storage;
+assign user_clk = sys_clk;
+assign user_rst = sys_rst;
+assign soc_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = soc_cmd_ready;
+assign soc_cmd_payload_we = user_port_native_0_cmd_we;
+assign soc_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign soc_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = soc_wdata_ready;
+assign soc_wdata_payload_we = user_port_native_0_wdata_we;
+assign soc_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = soc_rdata_valid;
+assign soc_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = soc_rdata_payload_data;
+assign soc_litedramcore_soccontroller_bus_error = vns_error;
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_cpu_interrupt <= 32'd0;
+ soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq;
+ soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq;
+// synthesis translate_off
+ dummy_d = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re;
+assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors;
+assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0];
+assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r;
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_ram_we <= 4'd0;
+ soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]);
+ soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]);
+ soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]);
+ soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]);
+// synthesis translate_off
+ dummy_d_1 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0];
+assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r;
+assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w;
+assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid;
+assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready;
+assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first;
+assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last;
+assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data;
+assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid;
+assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready;
+assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first;
+assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last;
+assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data;
+assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re;
+assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r;
+assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready);
+assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid;
+assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready;
+assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first;
+assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last;
+assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data;
+assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready);
+assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid;
+assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready;
+assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first;
+assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last;
+assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data;
+assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid);
+assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data;
+assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we));
+assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid);
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_eventmanager_status_w <= 2'd0;
+ soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status;
+ soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status;
+// synthesis translate_off
+ dummy_d_2 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_tx_clear <= 1'd0;
+ if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin
+ soc_litedramcore_uart_tx_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_3 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_4;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_eventmanager_pending_w <= 2'd0;
+ soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending;
+ soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending;
+// synthesis translate_off
+ dummy_d_4 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_5;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_rx_clear <= 1'd0;
+ if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin
+ soc_litedramcore_uart_rx_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_5 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1]));
+assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger;
+assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data};
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data;
+assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable;
+assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first;
+assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last;
+assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
+assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re));
+assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable);
+
+// synthesis translate_off
+reg dummy_d_6;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0;
+ if (soc_litedramcore_uart_tx_fifo_replace) begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1);
+ end else begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce;
+ end
+// synthesis translate_off
+ dummy_d_6 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din;
+assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace));
+assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re);
+assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r;
+assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16);
+assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0);
+assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data};
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data;
+assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable;
+assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first;
+assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last;
+assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
+assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re));
+assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable);
+
+// synthesis translate_off
+reg dummy_d_7;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0;
+ if (soc_litedramcore_uart_rx_fifo_replace) begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1);
+ end else begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce;
+ end
+// synthesis translate_off
+ dummy_d_7 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din;
+assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace));
+assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re);
+assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r;
+assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16);
+assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0);
+assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0);
+assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status;
+
+// synthesis translate_off
+reg dummy_d_8;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_timer_zero_clear <= 1'd0;
+ if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin
+ soc_litedramcore_timer_zero_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_8 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending;
+assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage);
+assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger;
+assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w;
+assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r;
+
+// synthesis translate_off
+reg dummy_d_9;
+// synthesis translate_on
+always @(*) begin
+ vns_wb2csr_next_state <= 1'd0;
+ vns_wb2csr_next_state <= vns_wb2csr_state;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ vns_wb2csr_next_state <= 1'd0;
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ vns_wb2csr_next_state <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_9 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_10;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_interface_we <= 1'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_10 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_11;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_bus_wishbone_ack <= 1'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ soc_litedramcore_bus_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_11 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_12;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_interface_adr <= 14'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_12 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sys_pll_reset = rst;
+assign pll_locked = soc_sys_pll_locked;
+assign soc_iodelay_pll_reset = rst;
+assign soc_s7pll0_clkin = clk;
+assign sys_clk = soc_s7pll0_clkout_buf0;
+assign sys4x_clk = soc_s7pll0_clkout_buf1;
+assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2;
+assign soc_s7pll1_clkin = clk;
+assign iodelay_clk = soc_s7pll1_clkout_buf;
+assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
+
+// synthesis translate_off
+reg dummy_d_13;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
+// synthesis translate_off
+ dummy_d_13 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_14;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
+// synthesis translate_off
+ dummy_d_14 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_15;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
+// synthesis translate_off
+ dummy_d_15 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_16;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
+// synthesis translate_off
+ dummy_d_16 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
+assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
+assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
+assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
+assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
+assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
+assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
+assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
+assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
+assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
+assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
+assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
+assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
+assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
+assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
+assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
+assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
+assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
+
+// synthesis translate_off
+reg dummy_d_17;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dqs_oe <= 1'd0;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
+ end
+// synthesis translate_off
+ dummy_d_17 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
+
+// synthesis translate_off
+reg dummy_d_18;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dqspattern_o0 <= 8'd0;
+ soc_a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (soc_a7ddrphy_dqspattern0) begin
+ soc_a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (soc_a7ddrphy_dqspattern1) begin
+ soc_a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (soc_a7ddrphy_wlevel_strobe_re) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+// synthesis translate_off
+ dummy_d_18 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_19;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip0_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip0_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_19 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_20;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip1_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip1_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_20 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_21;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip2_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip2_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_21 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_22;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip3_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip3_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_22 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_23;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip4_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip4_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_23 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_24;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip5_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip5_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_24 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_25;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip6_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip6_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_25 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_26;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip7_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip7_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_26 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_27;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip8_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip8_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_27 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_28;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip9_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip9_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_28 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_29;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip10_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip10_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_29 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_30;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip11_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip11_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_30 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_31;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip12_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip12_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_31 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_32;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip13_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip13_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_32 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_33;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip14_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip14_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_33 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_34;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip15_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip15_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_34 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address;
+assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank;
+assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n;
+assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n;
+assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n;
+assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n;
+assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke;
+assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt;
+assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n;
+assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n;
+assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata;
+assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en;
+assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask;
+assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en;
+assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
+assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
+assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address;
+assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank;
+assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n;
+assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n;
+assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n;
+assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n;
+assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke;
+assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt;
+assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n;
+assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n;
+assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata;
+assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en;
+assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask;
+assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en;
+assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
+assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
+assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address;
+assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank;
+assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n;
+assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n;
+assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n;
+assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n;
+assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke;
+assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt;
+assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n;
+assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n;
+assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata;
+assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en;
+assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask;
+assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en;
+assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
+assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
+assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address;
+assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank;
+assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n;
+assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n;
+assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n;
+assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n;
+assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke;
+assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt;
+assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n;
+assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n;
+assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata;
+assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en;
+assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask;
+assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en;
+assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
+assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
+assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address;
+assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank;
+assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n;
+assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n;
+assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n;
+assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n;
+assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke;
+assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt;
+assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n;
+assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n;
+assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata;
+assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en;
+assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask;
+assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en;
+assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata;
+assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid;
+assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address;
+assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank;
+assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n;
+assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n;
+assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n;
+assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n;
+assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke;
+assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt;
+assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n;
+assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n;
+assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata;
+assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en;
+assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask;
+assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en;
+assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata;
+assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid;
+assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address;
+assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank;
+assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n;
+assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n;
+assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n;
+assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n;
+assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke;
+assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt;
+assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n;
+assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n;
+assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata;
+assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en;
+assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask;
+assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en;
+assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata;
+assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid;
+assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address;
+assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank;
+assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n;
+assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n;
+assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n;
+assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n;
+assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke;
+assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt;
+assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n;
+assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n;
+assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata;
+assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en;
+assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask;
+assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en;
+assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata;
+assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid;
+
+// synthesis translate_off
+reg dummy_d_35;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank;
+ end else begin
+ soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank;
+ end
+// synthesis translate_off
+ dummy_d_35 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_36;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n;
+ end else begin
+ soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_36 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_37;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n;
+ end else begin
+ soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_37 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_38;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n;
+ end else begin
+ soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_38 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_39;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p0_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_39 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_40;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n;
+ end else begin
+ soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n;
+ end
+// synthesis translate_off
+ dummy_d_40 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_41;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p0_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_41 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_42;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke;
+ end else begin
+ soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke;
+ end
+// synthesis translate_off
+ dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt;
+ end else begin
+ soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt;
+ end
+// synthesis translate_off
+ dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n;
+ end else begin
+ soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_44 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_45;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n;
+ end else begin
+ soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n;
+ end
+// synthesis translate_off
+ dummy_d_45 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_46;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata;
+ end else begin
+ soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_46 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_47;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata;
+ end
+// synthesis translate_off
+ dummy_d_47 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_48;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en;
+ end else begin
+ soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_48 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_49;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_49 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_50;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask;
+ end else begin
+ soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_50 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_51;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en;
+ end else begin
+ soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_51 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_52;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_address <= 14'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_address <= soc_sdram_slave_p1_address;
+ end else begin
+ soc_sdram_master_p1_address <= soc_sdram_inti_p1_address;
+ end
+// synthesis translate_off
+ dummy_d_52 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_53;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank;
+ end else begin
+ soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank;
+ end
+// synthesis translate_off
+ dummy_d_53 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_54;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n;
+ end else begin
+ soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_54 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_55;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n;
+ end else begin
+ soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_55 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_56;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n;
+ end else begin
+ soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_56 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_57;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p1_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_57 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_58;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n;
+ end else begin
+ soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n;
+ end
+// synthesis translate_off
+ dummy_d_58 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_59;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p1_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_59 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_60;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke;
+ end else begin
+ soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke;
+ end
+// synthesis translate_off
+ dummy_d_60 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_61;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt;
+ end else begin
+ soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt;
+ end
+// synthesis translate_off
+ dummy_d_61 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_62;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n;
+ end else begin
+ soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_62 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_63;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n;
+ end else begin
+ soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n;
+ end
+// synthesis translate_off
+ dummy_d_63 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_64;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata;
+ end else begin
+ soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_64 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_65;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata;
+ end
+// synthesis translate_off
+ dummy_d_65 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_66;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en;
+ end else begin
+ soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_66 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_67;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_67 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_68;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask;
+ end else begin
+ soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_68 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_69;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en;
+ end else begin
+ soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_69 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_70;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_address <= 14'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_address <= soc_sdram_slave_p2_address;
+ end else begin
+ soc_sdram_master_p2_address <= soc_sdram_inti_p2_address;
+ end
+// synthesis translate_off
+ dummy_d_70 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_71;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank;
+ end else begin
+ soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank;
+ end
+// synthesis translate_off
+ dummy_d_71 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_72;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n;
+ end else begin
+ soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_72 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_73;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n;
+ end else begin
+ soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_73 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_74;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n;
+ end else begin
+ soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_74 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_75;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p2_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_75 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_76;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n;
+ end else begin
+ soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n;
+ end
+// synthesis translate_off
+ dummy_d_76 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_77;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p2_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_77 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_78;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke;
+ end else begin
+ soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke;
+ end
+// synthesis translate_off
+ dummy_d_78 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_79;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt;
+ end else begin
+ soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt;
+ end
+// synthesis translate_off
+ dummy_d_79 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_80;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n;
+ end else begin
+ soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_80 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_81;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n;
+ end else begin
+ soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n;
+ end
+// synthesis translate_off
+ dummy_d_81 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_82;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata;
+ end else begin
+ soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_82 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_83;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata;
+ end
+// synthesis translate_off
+ dummy_d_83 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_84;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en;
+ end else begin
+ soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_84 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_85;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_85 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_86;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask;
+ end else begin
+ soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_86 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_87;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en;
+ end else begin
+ soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_87 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_88;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_address <= 14'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_address <= soc_sdram_slave_p3_address;
+ end else begin
+ soc_sdram_master_p3_address <= soc_sdram_inti_p3_address;
+ end
+// synthesis translate_off
+ dummy_d_88 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_89;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank;
+ end else begin
+ soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank;
+ end
+// synthesis translate_off
+ dummy_d_89 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_90;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n;
+ end else begin
+ soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_90 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_91;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n;
+ end else begin
+ soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_91 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_92;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n;
+ end else begin
+ soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_92 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_93;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p3_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_93 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n;
+ end else begin
+ soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n;
+ end
+// synthesis translate_off
+ dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p3_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke;
+ end else begin
+ soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke;
+ end
+// synthesis translate_off
+ dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt;
+ end else begin
+ soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt;
+ end
+// synthesis translate_off
+ dummy_d_97 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_98;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n;
+ end else begin
+ soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_98 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_99;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n;
+ end else begin
+ soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n;
+ end
+// synthesis translate_off
+ dummy_d_99 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_100;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata;
+ end else begin
+ soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_100 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_101;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata;
+ end
+// synthesis translate_off
+ dummy_d_101 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_102;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en;
+ end else begin
+ soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_102 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_103;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_103 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_104;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask;
+ end else begin
+ soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_104 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_105;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en;
+ end else begin
+ soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_105 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_106;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_address <= 14'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_address <= soc_sdram_slave_p0_address;
+ end else begin
+ soc_sdram_master_p0_address <= soc_sdram_inti_p0_address;
+ end
+// synthesis translate_off
+ dummy_d_106 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p0_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p1_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p2_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p3_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p0_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p1_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p2_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p3_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3];
+
+// synthesis translate_off
+reg dummy_d_107;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p0_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_107 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_108;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p0_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_108 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_109;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p0_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_109 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_110;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p0_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_110 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage;
+assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage;
+assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]);
+assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]);
+assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage;
+assign soc_sdram_inti_p0_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_111;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p1_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_111 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_112;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p1_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_112 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_113;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p1_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_113 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_114;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p1_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_114 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage;
+assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage;
+assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]);
+assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]);
+assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage;
+assign soc_sdram_inti_p1_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_115;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p2_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_115 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_116;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p2_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_116 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_117;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p2_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_117 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_118;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p2_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_118 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage;
+assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage;
+assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]);
+assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]);
+assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage;
+assign soc_sdram_inti_p2_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_119;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p3_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_119 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_120;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p3_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_120 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_121;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p3_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_121 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_122;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p3_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_122 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage;
+assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage;
+assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]);
+assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]);
+assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage;
+assign soc_sdram_inti_p3_wrdata_mask = 1'd0;
+assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid;
+assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready;
+assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we;
+assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr;
+assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock;
+assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready;
+assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid;
+assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid;
+assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready;
+assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we;
+assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr;
+assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock;
+assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready;
+assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid;
+assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid;
+assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready;
+assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we;
+assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr;
+assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock;
+assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready;
+assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid;
+assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid;
+assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready;
+assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we;
+assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr;
+assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock;
+assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready;
+assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid;
+assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid;
+assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready;
+assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we;
+assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr;
+assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock;
+assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready;
+assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid;
+assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid;
+assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready;
+assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we;
+assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr;
+assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock;
+assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready;
+assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid;
+assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid;
+assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready;
+assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we;
+assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr;
+assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock;
+assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready;
+assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid;
+assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid;
+assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready;
+assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we;
+assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr;
+assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock;
+assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready;
+assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid;
+assign soc_sdram_timer_wait = (~soc_sdram_timer_done0);
+assign soc_sdram_postponer_req_i = soc_sdram_timer_done0;
+assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o;
+assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0;
+assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done);
+assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0);
+assign soc_sdram_timer_done0 = soc_sdram_timer_done1;
+assign soc_sdram_timer_count0 = soc_sdram_timer_count1;
+assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0));
+assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0));
+assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0);
+assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1;
+assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1;
+
+// synthesis translate_off
+reg dummy_d_123;
+// synthesis translate_on
+always @(*) begin
+ vns_refresher_next_state <= 2'd0;
+ vns_refresher_next_state <= vns_refresher_state;
+ case (vns_refresher_state)
+ 1'd1: begin
+ if (soc_sdram_cmd_ready) begin
+ vns_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ vns_refresher_next_state <= 2'd3;
+ end else begin
+ vns_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_zqcs_executer_done) begin
+ vns_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (soc_sdram_wants_refresh) begin
+ vns_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_123 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_124;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_sequencer_start0 <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ if (soc_sdram_cmd_ready) begin
+ soc_sdram_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_124 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_125;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_valid <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ end else begin
+ soc_sdram_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ if (soc_sdram_zqcs_executer_done) begin
+ soc_sdram_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_125 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_126;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_zqcs_executer_start <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ soc_sdram_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_126 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_127;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_last <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ end else begin
+ soc_sdram_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_zqcs_executer_done) begin
+ soc_sdram_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_127 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid;
+assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid);
+assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_128;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_128 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write);
+assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
+assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
+
+// synthesis translate_off
+reg dummy_d_129;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_129 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_130;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_130 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_131;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine0_next_state <= 4'd0;
+ vns_bankmachine0_next_state <= vns_bankmachine0_state;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ if (soc_sdram_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ vns_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ if (soc_sdram_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine0_refresh_req)) begin
+ vns_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ vns_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin
+ vns_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_131 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_132;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_132 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_133;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_133 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_134;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_135 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_136;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_136 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_137;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_137 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_138;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_138 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_139;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_refresh_gnt <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine0_twtpcon_ready) begin
+ soc_sdram_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_139 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_140;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_140 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_141;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_open <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_141 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_142;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_close <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_142 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_143;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_143 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_144;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_144 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid;
+assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid);
+assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
+
+// synthesis translate_off
+reg dummy_d_145;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_145 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write);
+assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
+assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
+
+// synthesis translate_off
+reg dummy_d_146;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_146 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_147;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_147 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_148;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine1_next_state <= 4'd0;
+ vns_bankmachine1_next_state <= vns_bankmachine1_state;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ if (soc_sdram_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ vns_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ if (soc_sdram_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine1_refresh_req)) begin
+ vns_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ vns_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin
+ vns_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_148 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_149;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_149 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_150;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_150 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_151;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_151 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_152;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_152 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_153;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_153 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_154;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_154 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_155;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_155 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_156;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_refresh_gnt <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine1_twtpcon_ready) begin
+ soc_sdram_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_156 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_157;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_157 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_158;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_open <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_158 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_159;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_close <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_159 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_160;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_160 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_161;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_161 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid;
+assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid);
+assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
+
+// synthesis translate_off
+reg dummy_d_162;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_162 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write);
+assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
+assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
+
+// synthesis translate_off
+reg dummy_d_163;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_163 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_164;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_164 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_165;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine2_next_state <= 4'd0;
+ vns_bankmachine2_next_state <= vns_bankmachine2_state;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ if (soc_sdram_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ vns_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ if (soc_sdram_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine2_refresh_req)) begin
+ vns_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ vns_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin
+ vns_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_165 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_166;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_166 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_167;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_167 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_168;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_168 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_169;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_169 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_170;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_170 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_171;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_171 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_172;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_172 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_173;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_refresh_gnt <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine2_twtpcon_ready) begin
+ soc_sdram_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_173 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_174;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_174 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_175;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_open <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_175 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_176;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_close <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_176 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_177;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_177 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_178;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_178 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid;
+assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid);
+assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
+
+// synthesis translate_off
+reg dummy_d_179;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_179 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write);
+assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
+assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
+
+// synthesis translate_off
+reg dummy_d_180;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_180 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_181;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_181 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_182;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine3_next_state <= 4'd0;
+ vns_bankmachine3_next_state <= vns_bankmachine3_state;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ if (soc_sdram_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ vns_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ if (soc_sdram_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine3_refresh_req)) begin
+ vns_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ vns_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin
+ vns_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_182 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_183;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_183 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_184;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_184 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_185;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_185 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_186;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_186 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_187;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_187 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_188;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_188 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_189;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_189 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_190;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_refresh_gnt <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine3_twtpcon_ready) begin
+ soc_sdram_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_190 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_191;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_191 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_192;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_open <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_192 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_193;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_close <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_193 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_194;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_194 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_195;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_195 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid;
+assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid);
+assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
+
+// synthesis translate_off
+reg dummy_d_196;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_196 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write);
+assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
+assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
+
+// synthesis translate_off
+reg dummy_d_197;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_197 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_198;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_198 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_199;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine4_next_state <= 4'd0;
+ vns_bankmachine4_next_state <= vns_bankmachine4_state;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ if (soc_sdram_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ vns_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ if (soc_sdram_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine4_refresh_req)) begin
+ vns_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ vns_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin
+ vns_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_199 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_200;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_200 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_201;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_201 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_202;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_202 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_203;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_203 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_204;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_204 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_205;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_205 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_206;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_206 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_207;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_refresh_gnt <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine4_twtpcon_ready) begin
+ soc_sdram_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_207 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_208;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_208 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_209;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_open <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_209 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_210;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_close <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_210 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_211;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_211 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_212;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_212 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid;
+assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid);
+assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
+
+// synthesis translate_off
+reg dummy_d_213;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write);
+assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
+assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_214 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_215;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_215 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_216;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine5_next_state <= 4'd0;
+ vns_bankmachine5_next_state <= vns_bankmachine5_state;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ if (soc_sdram_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ vns_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ if (soc_sdram_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine5_refresh_req)) begin
+ vns_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ vns_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin
+ vns_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_216 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_217;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_217 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_218;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_218 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_219;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_219 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_220;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_220 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_221;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_221 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_222;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_222 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_223;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_223 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_224;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_refresh_gnt <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine5_twtpcon_ready) begin
+ soc_sdram_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_224 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_225;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_225 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_226;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_open <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_226 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_227;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_close <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_227 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_228;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_228 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_229;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_229 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid;
+assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid);
+assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
+
+// synthesis translate_off
+reg dummy_d_230;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_230 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write);
+assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
+assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
+
+// synthesis translate_off
+reg dummy_d_231;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_231 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_232;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_232 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_233;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine6_next_state <= 4'd0;
+ vns_bankmachine6_next_state <= vns_bankmachine6_state;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ if (soc_sdram_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ vns_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ if (soc_sdram_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine6_refresh_req)) begin
+ vns_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ vns_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin
+ vns_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_233 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_234;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_234 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_235;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_235 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_236;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_236 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_237;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_237 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_238;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_238 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_239;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_239 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_240;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_240 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_241;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_refresh_gnt <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine6_twtpcon_ready) begin
+ soc_sdram_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_241 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_242;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_242 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_243;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_open <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_243 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_244;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_close <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_244 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_245;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_245 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_246;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_246 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid;
+assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid);
+assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
+
+// synthesis translate_off
+reg dummy_d_247;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_a <= 14'd0;
+ if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+ end else begin
+ soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_247 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write);
+assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
+assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
+
+// synthesis translate_off
+reg dummy_d_248;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+ soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_248 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_249;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_249 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_250;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine7_next_state <= 4'd0;
+ vns_bankmachine7_next_state <= vns_bankmachine7_state;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ if (soc_sdram_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ vns_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ if (soc_sdram_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine7_refresh_req)) begin
+ vns_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ vns_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin
+ vns_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_250 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_251;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_251 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_252;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_252 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_253;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_253 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_254 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_255;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_255 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_256;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_256 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_257;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_257 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_258;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_refresh_gnt <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine7_twtpcon_ready) begin
+ soc_sdram_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_258 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_259;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_259 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_260;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_open <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_260 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_261;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_close <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_261 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_262;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_262 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_263;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_263 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
+assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
+assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready);
+assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read));
+assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready;
+assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read));
+assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write));
+assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0);
+assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0);
+assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt);
+assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata};
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+
+// synthesis translate_off
+reg dummy_d_264;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_valids <= 8'd0;
+ soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+// synthesis translate_off
+ dummy_d_264 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids;
+assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
+assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
+assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
+assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
+assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
+assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
+
+// synthesis translate_off
+reg dummy_d_265;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
+ end
+// synthesis translate_off
+ dummy_d_265 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_266;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
+ end
+// synthesis translate_off
+ dummy_d_266 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_267;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
+ end
+// synthesis translate_off
+ dummy_d_267 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_268;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_268 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_269;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_269 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_270;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_270 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_271;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_271 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_272;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_272 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_273;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_273 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_274;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_274 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_275;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_275 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid));
+
+// synthesis translate_off
+reg dummy_d_276;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_valids <= 8'd0;
+ soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+// synthesis translate_off
+ dummy_d_276 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids;
+assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
+assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
+assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
+assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
+assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
+assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
+
+// synthesis translate_off
+reg dummy_d_277;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_cas <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
+ end
+// synthesis translate_off
+ dummy_d_277 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_278;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_ras <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
+ end
+// synthesis translate_off
+ dummy_d_278 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_279;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_we <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
+ end
+// synthesis translate_off
+ dummy_d_279 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid));
+assign soc_sdram_dfi_p0_reset_n = 1'd1;
+assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}};
+assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}};
+assign soc_sdram_dfi_p1_reset_n = 1'd1;
+assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}};
+assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}};
+assign soc_sdram_dfi_p2_reset_n = 1'd1;
+assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}};
+assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}};
+assign soc_sdram_dfi_p3_reset_n = 1'd1;
+assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}};
+assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}};
+assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]);
+
+// synthesis translate_off
+reg dummy_d_280;
+// synthesis translate_on
+always @(*) begin
+ vns_multiplexer_next_state <= 4'd0;
+ vns_multiplexer_next_state <= vns_multiplexer_state;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (soc_sdram_read_available) begin
+ if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin
+ vns_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (soc_sdram_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_cmd_last) begin
+ vns_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_twtrcon_ready) begin
+ vns_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ vns_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ vns_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ vns_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ vns_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ vns_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (soc_sdram_write_available) begin
+ if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin
+ vns_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (soc_sdram_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_280 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_281;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel0 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel0 <= 1'd0;
+ end
+ 2'd2: begin
+ soc_sdram_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel0 <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_281 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_282;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel1 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel1 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_282 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_283;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel2 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel2 <= 2'd2;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_283 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_284;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_want_activates <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_284 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_285;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel3 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel3 <= 2'd2;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel3 <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_285 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_286;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_en0 <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_en0 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_286 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_287;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_sdram_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_287 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_288;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_288 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_289;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_want_reads <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_289 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_290;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_want_writes <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_290 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_291;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_en1 <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_291 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_292;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
+ end else begin
+ soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
+ end else begin
+ soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_292 = dummy_s;
+// synthesis translate_on
+end
+assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock));
+assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
+assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
+assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
+assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock));
+assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
+assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
+assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
+assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock));
+assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
+assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
+assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
+assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock));
+assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
+assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
+assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
+assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock));
+assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
+assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
+assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
+assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock));
+assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
+assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
+assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
+assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock));
+assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
+assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
+assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
+assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock));
+assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
+assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
+assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
+assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready));
+assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready));
+assign soc_port_wdata_ready = vns_new_master_wdata_ready2;
+assign soc_wdata_ready = vns_new_master_wdata_ready5;
+assign soc_port_rdata_valid = vns_new_master_rdata_valid8;
+assign soc_rdata_valid = vns_new_master_rdata_valid17;
+
+// synthesis translate_off
+reg dummy_d_293;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_interface_wdata <= 128'd0;
+ case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
+ 1'd1: begin
+ soc_sdram_interface_wdata <= soc_port_wdata_payload_data;
+ end
+ 2'd2: begin
+ soc_sdram_interface_wdata <= soc_wdata_payload_data;
+ end
+ default: begin
+ soc_sdram_interface_wdata <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_293 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_294;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_interface_wdata_we <= 16'd0;
+ case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
+ 1'd1: begin
+ soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we;
+ end
+ 2'd2: begin
+ soc_sdram_interface_wdata_we <= soc_wdata_payload_we;
+ end
+ default: begin
+ soc_sdram_interface_wdata_we <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_294 = dummy_s;
+// synthesis translate_on
+end
+assign soc_port_rdata_payload_data = soc_sdram_interface_rdata;
+assign soc_rdata_payload_data = soc_sdram_interface_rdata;
+assign soc_address_d = soc_wb_sdram_adr;
+assign soc_counter_offset = soc_address_q;
+assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3);
+assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done)));
+assign soc_need_refill_reset = soc_end_of_burst;
+assign soc_need_refill_d = 1'd0;
+assign soc_litedram_wb_cti = 3'd7;
+assign soc_litedram_wb_adr = soc_address_q[29:2];
+assign soc_cached_sels_reset0 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_295;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop0_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0];
+ end
+// synthesis translate_off
+ dummy_d_295 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_296;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce0 <= 1'd0;
+ if (((soc_write & soc_write_sel0) | soc_refill)) begin
+ soc_cached_datas_ce0 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_296 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_297;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce0 <= 1'd0;
+ if (((soc_write & soc_write_sel0) | soc_refill)) begin
+ soc_cached_sels_ce0 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_297 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset1 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_298;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop1_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32];
+ end
+// synthesis translate_off
+ dummy_d_298 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_299;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce1 <= 1'd0;
+ if (((soc_write & soc_write_sel1) | soc_refill)) begin
+ soc_cached_datas_ce1 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_299 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_300;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce1 <= 1'd0;
+ if (((soc_write & soc_write_sel1) | soc_refill)) begin
+ soc_cached_sels_ce1 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_300 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset2 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_301;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop2_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64];
+ end
+// synthesis translate_off
+ dummy_d_301 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_302;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce2 <= 1'd0;
+ if (((soc_write & soc_write_sel2) | soc_refill)) begin
+ soc_cached_datas_ce2 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_302 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_303;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce2 <= 1'd0;
+ if (((soc_write & soc_write_sel2) | soc_refill)) begin
+ soc_cached_sels_ce2 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_303 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset3 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_304;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop3_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96];
+ end
+// synthesis translate_off
+ dummy_d_304 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_305;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce3 <= 1'd0;
+ if (((soc_write & soc_write_sel3) | soc_refill)) begin
+ soc_cached_datas_ce3 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_305 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_306;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce3 <= 1'd0;
+ if (((soc_write & soc_write_sel3) | soc_refill)) begin
+ soc_cached_sels_ce3 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_306 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_307;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel2 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_write_sel2 <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_307 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_308;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel3 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ soc_write_sel3 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_308 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_309;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel0 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ soc_write_sel0 <= 1'd1;
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_309 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_310;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel1 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ soc_write_sel1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_310 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_311;
+// synthesis translate_on
+always @(*) begin
+ soc_wb_sdram_dat_r <= 32'd0;
+ case (soc_address_q[1:0])
+ 1'd0: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q;
+ end
+ 1'd1: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q;
+ end
+ 2'd2: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q;
+ end
+ 2'd3: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_311 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q};
+assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q};
+
+// synthesis translate_off
+reg dummy_d_312;
+// synthesis translate_on
+always @(*) begin
+ vns_converter_next_state <= 3'd0;
+ vns_converter_next_state <= vns_converter_state;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ if (soc_counter_done) begin
+ vns_converter_next_state <= 2'd2;
+ end
+ end else begin
+ if ((~soc_wb_sdram_cyc)) begin
+ vns_converter_next_state <= 2'd2;
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_litedram_wb_ack) begin
+ vns_converter_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedram_wb_ack) begin
+ vns_converter_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ vns_converter_next_state <= 1'd0;
+ end
+ default: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ if (soc_wb_sdram_we) begin
+ vns_converter_next_state <= 1'd1;
+ end else begin
+ if (soc_need_refill_q) begin
+ vns_converter_next_state <= 2'd3;
+ end else begin
+ vns_converter_next_state <= 3'd4;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_312 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_313;
+// synthesis translate_on
+always @(*) begin
+ soc_address_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_address_ce <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_313 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_314;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_dat_w <= 128'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_dat_w <= soc_cached_data;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_314 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_315;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_sel <= 16'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_sel <= soc_cached_sel;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_315 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_316;
+// synthesis translate_on
+always @(*) begin
+ soc_counter_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_counter_ce <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_316 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_317;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_cyc <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_cyc <= 1'd1;
+ end
+ 2'd3: begin
+ soc_litedram_wb_cyc <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_317 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_318;
+// synthesis translate_on
+always @(*) begin
+ soc_counter_reset <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ soc_counter_reset <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_318 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_319;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_stb <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_stb <= 1'd1;
+ end
+ 2'd3: begin
+ soc_litedram_wb_stb <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_319 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_320;
+// synthesis translate_on
+always @(*) begin
+ soc_need_refill_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedram_wb_ack) begin
+ soc_need_refill_ce <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_320 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_321;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_we <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_we <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_321 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_322;
+// synthesis translate_on
+always @(*) begin
+ soc_write <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_write <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_322 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_323;
+// synthesis translate_on
+always @(*) begin
+ soc_wb_sdram_ack <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_wb_sdram_ack <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_wb_sdram_ack <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_323 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_324;
+// synthesis translate_on
+always @(*) begin
+ soc_evict <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_evict <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_324 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_325;
+// synthesis translate_on
+always @(*) begin
+ soc_refill <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ soc_refill <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_325 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_326;
+// synthesis translate_on
+always @(*) begin
+ soc_read <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_read <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_326 = dummy_s;
+// synthesis translate_on
+end
+assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we);
+assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w;
+assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel;
+assign soc_port_wdata_valid = soc_wdata_converter_source_valid;
+assign soc_wdata_converter_source_ready = soc_port_wdata_ready;
+assign soc_port_wdata_first = soc_wdata_converter_source_first;
+assign soc_port_wdata_last = soc_wdata_converter_source_last;
+assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data;
+assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we;
+assign soc_rdata_converter_sink_valid = soc_port_rdata_valid;
+assign soc_port_rdata_ready = soc_rdata_converter_sink_ready;
+assign soc_rdata_converter_sink_first = soc_port_rdata_first;
+assign soc_rdata_converter_sink_last = soc_port_rdata_last;
+assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data;
+assign soc_rdata_converter_source_ready = 1'd1;
+assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data;
+assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid;
+assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first;
+assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last;
+assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready;
+assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data};
+assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid;
+assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first;
+assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last;
+assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready;
+assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
+assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
+assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid;
+assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready;
+assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first;
+assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last;
+assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data;
+assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid;
+assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready;
+assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first;
+assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last;
+assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data;
+assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
+assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid;
+assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first;
+assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last;
+assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready;
+assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data};
+assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid;
+assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first;
+assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last;
+assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready;
+assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data;
+assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid;
+assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready;
+assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first;
+assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last;
+assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data;
+assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid;
+assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready;
+assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first;
+assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last;
+assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data;
+assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
+
+// synthesis translate_off
+reg dummy_d_327;
+// synthesis translate_on
+always @(*) begin
+ vns_litedramwishbone2native_next_state <= 2'd0;
+ vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ if (soc_wdata_converter_sink_ready) begin
+ vns_litedramwishbone2native_next_state <= 1'd0;
+ end
+ end
+ 2'd2: begin
+ if (soc_rdata_converter_source_valid) begin
+ vns_litedramwishbone2native_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ if ((soc_count == 1'd0)) begin
+ if (soc_litedram_wb_we) begin
+ vns_litedramwishbone2native_next_state <= 1'd1;
+ end else begin
+ vns_litedramwishbone2native_next_state <= 2'd2;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_327 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_328;
+// synthesis translate_on
+always @(*) begin
+ soc_count_next_value <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ soc_count_next_value <= (soc_count + 1'd1);
+ if ((soc_count == 1'd0)) begin
+ soc_count_next_value <= 1'd0;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_328 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_329;
+// synthesis translate_on
+always @(*) begin
+ soc_count_next_value_ce <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ soc_count_next_value_ce <= 1'd1;
+ if ((soc_count == 1'd0)) begin
+ soc_count_next_value_ce <= 1'd1;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_329 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_330;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_valid <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_330 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_331;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_ack <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ if (soc_wdata_converter_sink_ready) begin
+ soc_litedram_wb_ack <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ if (soc_rdata_converter_source_valid) begin
+ soc_litedram_wb_ack <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_331 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_332;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_payload_we <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_payload_we <= soc_litedram_wb_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_332 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_333;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_payload_addr <= 24'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_333 = dummy_s;
+// synthesis translate_on
+end
+assign vns_shared_adr = vns_rhs_array_muxed36;
+assign vns_shared_dat_w = vns_rhs_array_muxed37;
+assign vns_shared_sel = vns_rhs_array_muxed38;
+assign vns_shared_cyc = vns_rhs_array_muxed39;
+assign vns_shared_stb = vns_rhs_array_muxed40;
+assign vns_shared_we = vns_rhs_array_muxed41;
+assign vns_shared_cti = vns_rhs_array_muxed42;
+assign vns_shared_bte = vns_rhs_array_muxed43;
+assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r;
+assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r;
+assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0));
+assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1));
+assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0));
+assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1));
+assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc};
+
+// synthesis translate_off
+reg dummy_d_334;
+// synthesis translate_on
+always @(*) begin
+ vns_slave_sel <= 4'd0;
+ vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0);
+ vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096);
+ vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280);
+ vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64);
+// synthesis translate_off
+ dummy_d_334 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr;
+assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel;
+assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb;
+assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we;
+assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti;
+assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte;
+assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr;
+assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel;
+assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb;
+assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we;
+assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti;
+assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte;
+assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr;
+assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel;
+assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb;
+assign soc_litedramcore_bus_wishbone_we = vns_shared_we;
+assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti;
+assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte;
+assign soc_wb_sdram_adr = vns_shared_adr;
+assign soc_wb_sdram_dat_w = vns_shared_dat_w;
+assign soc_wb_sdram_sel = vns_shared_sel;
+assign soc_wb_sdram_stb = vns_shared_stb;
+assign soc_wb_sdram_we = vns_shared_we;
+assign soc_wb_sdram_cti = vns_shared_cti;
+assign soc_wb_sdram_bte = vns_shared_bte;
+assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]);
+assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]);
+assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]);
+assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]);
+
+// synthesis translate_off
+reg dummy_d_335;
+// synthesis translate_on
+always @(*) begin
+ vns_shared_ack <= 1'd0;
+ vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack);
+ if (vns_done) begin
+ vns_shared_ack <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_335 = dummy_s;
+// synthesis translate_on
+end
+assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err);
+
+// synthesis translate_off
+reg dummy_d_336;
+// synthesis translate_on
+always @(*) begin
+ vns_shared_dat_r <= 32'd0;
+ vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r));
+ if (vns_done) begin
+ vns_shared_dat_r <= 32'd4294967295;
+ end
+// synthesis translate_off
+ dummy_d_336 = dummy_s;
+// synthesis translate_on
+end
+assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack));
+
+// synthesis translate_off
+reg dummy_d_337;
+// synthesis translate_on
+always @(*) begin
+ vns_error <= 1'd0;
+ if (vns_done) begin
+ vns_error <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_337 = dummy_s;
+// synthesis translate_on
+end
+assign vns_done = (vns_count == 1'd0);
+assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0);
+assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
+assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
+assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
+assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
+assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
+assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
+assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
+assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
+assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
+assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
+assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage;
+assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24];
+assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16];
+assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8];
+assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0];
+assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24];
+assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16];
+assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8];
+assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0];
+assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we;
+assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7);
+assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank1_init_done0_w = soc_init_done_storage;
+assign vns_csrbank1_init_error0_w = soc_init_error_storage;
+assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5);
+assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0];
+assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0];
+assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
+assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
+assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0];
+assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
+assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
+assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
+assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
+assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
+assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6);
+assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0];
+assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
+assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
+assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
+assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
+assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
+assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
+assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
+assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
+assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
+assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
+assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
+assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
+assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
+assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
+assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
+assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
+assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
+assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
+assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
+assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
+assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
+assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
+assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
+assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
+assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
+assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
+assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
+assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
+assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
+assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
+assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
+assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
+assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
+assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
+assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
+assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
+assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
+assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
+assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
+assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
+assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
+assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
+assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
+assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
+assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
+assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
+assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
+assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
+assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
+assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
+assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
+assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
+assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
+assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
+assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
+assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
+assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
+assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
+assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
+assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
+assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
+assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
+assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
+assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
+assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
+assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
+assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
+assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
+assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
+assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
+assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
+assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
+assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
+assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
+assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
+assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
+assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
+assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
+assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
+assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
+assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
+assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
+assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
+assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
+assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
+assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
+assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
+assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
+assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
+assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
+assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
+assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
+assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
+assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
+assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
+assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
+assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
+assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
+assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
+assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
+assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
+assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
+assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
+assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
+assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
+assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
+assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0];
+assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0];
+assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[13:8];
+assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0];
+assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24];
+assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16];
+assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8];
+assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0];
+assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we;
+assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0];
+assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[13:8];
+assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0];
+assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24];
+assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16];
+assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8];
+assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0];
+assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we;
+assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0];
+assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[13:8];
+assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0];
+assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24];
+assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16];
+assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8];
+assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0];
+assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we;
+assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0];
+assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[13:8];
+assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0];
+assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24];
+assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16];
+assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8];
+assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0];
+assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we;
+assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4);
+assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
+assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
+assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0];
+assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0];
+assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
+assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24];
+assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16];
+assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8];
+assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0];
+assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24];
+assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16];
+assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8];
+assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0];
+assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage;
+assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage;
+assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24];
+assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16];
+assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8];
+assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0];
+assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we;
+assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage;
+assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3);
+assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0];
+assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
+assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
+assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0];
+assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
+assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
+assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0];
+assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
+assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
+assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0];
+assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
+assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
+assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0];
+assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
+assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
+assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0];
+assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
+assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
+assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status;
+assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we;
+assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status;
+assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we;
+assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0];
+assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2);
+assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
+assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
+assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
+assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
+assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
+assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
+assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
+assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
+assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24];
+assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16];
+assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8];
+assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0];
+assign vns_adr = soc_litedramcore_interface_adr;
+assign vns_we = soc_litedramcore_interface_we;
+assign vns_dat_w = soc_litedramcore_interface_dat_w;
+assign soc_litedramcore_interface_dat_r = vns_dat_r;
+assign vns_interface0_bank_bus_adr = vns_adr;
+assign vns_interface1_bank_bus_adr = vns_adr;
+assign vns_interface2_bank_bus_adr = vns_adr;
+assign vns_interface3_bank_bus_adr = vns_adr;
+assign vns_interface4_bank_bus_adr = vns_adr;
+assign vns_interface5_bank_bus_adr = vns_adr;
+assign vns_interface6_bank_bus_adr = vns_adr;
+assign vns_interface0_bank_bus_we = vns_we;
+assign vns_interface1_bank_bus_we = vns_we;
+assign vns_interface2_bank_bus_we = vns_we;
+assign vns_interface3_bank_bus_we = vns_we;
+assign vns_interface4_bank_bus_we = vns_we;
+assign vns_interface5_bank_bus_we = vns_we;
+assign vns_interface6_bank_bus_we = vns_we;
+assign vns_interface0_bank_bus_dat_w = vns_dat_w;
+assign vns_interface1_bank_bus_dat_w = vns_dat_w;
+assign vns_interface2_bank_bus_dat_w = vns_dat_w;
+assign vns_interface3_bank_bus_dat_w = vns_dat_w;
+assign vns_interface4_bank_bus_dat_w = vns_dat_w;
+assign vns_interface5_bank_bus_dat_w = vns_dat_w;
+assign vns_interface6_bank_bus_dat_w = vns_dat_w;
+assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r);
+
+// synthesis translate_off
+reg dummy_d_338;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed0 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6];
+ end
+ default: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_338 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_339;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed1 <= 14'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_339 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_340;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed2 <= 3'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_340 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_341;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed3 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_341 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_342;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed4 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_342 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_343;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed5 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_343 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_344;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed0 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_344 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_345;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed1 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_345 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_346;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed2 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_346 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_347;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed6 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0];
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1];
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2];
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3];
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4];
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5];
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6];
+ end
+ default: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_347 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_348;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed7 <= 14'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_348 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_349;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed8 <= 3'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_349 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_350;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed9 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_350 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_351;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed10 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_351 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_352;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed11 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_352 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_353;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed3 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_353 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_354;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed4 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_354 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_355;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed5 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_355 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_356;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed12 <= 21'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_356 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_357;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed13 <= 1'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed13 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed13 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_357 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_358;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed14 <= 1'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_358 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_359;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed15 <= 21'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_359 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_360;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed16 <= 1'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed16 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed16 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_360 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_361;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed17 <= 1'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_361 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_362;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed18 <= 21'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_362 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_363;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed19 <= 1'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed19 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed19 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_363 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_364;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed20 <= 1'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_364 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_365;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed21 <= 21'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_365 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_366;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed22 <= 1'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed22 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed22 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_366 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_367;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed23 <= 1'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_367 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_368;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed24 <= 21'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_368 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_369;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed25 <= 1'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed25 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed25 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_369 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_370;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed26 <= 1'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_370 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_371;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed27 <= 21'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_371 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_372;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed28 <= 1'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed28 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed28 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_372 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_373;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed29 <= 1'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_373 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_374;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed30 <= 21'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_374 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_375;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed31 <= 1'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed31 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed31 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_375 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_376;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed32 <= 1'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_376 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_377;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed33 <= 21'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_377 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_378;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed34 <= 1'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed34 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed34 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_378 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_379;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed35 <= 1'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_379 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_380;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed36 <= 30'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr;
+ end
+ default: begin
+ vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_380 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_381;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed37 <= 32'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w;
+ end
+ default: begin
+ vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_381 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_382;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed38 <= 4'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel;
+ end
+ default: begin
+ vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_382 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_383;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed39 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc;
+ end
+ default: begin
+ vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_383 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_384;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed40 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb;
+ end
+ default: begin
+ vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_384 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_385;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed41 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we;
+ end
+ default: begin
+ vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_385 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_386;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed42 <= 3'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti;
+ end
+ default: begin
+ vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_386 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_387;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed43 <= 2'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte;
+ end
+ default: begin
+ vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_387 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_388;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed0 <= 3'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed0 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_388 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_389;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed1 <= 14'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed1 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed1 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_389 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_390;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed2 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_390 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_391;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed3 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_391 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_392;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed4 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_392 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_393;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed5 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_393 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_394;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed6 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_394 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_395;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed7 <= 3'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed7 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_395 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_396;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed8 <= 14'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed8 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed8 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_396 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_397;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed9 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_397 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_398;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed10 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_398 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_399;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed11 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_399 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_400;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed12 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_400 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_401;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed13 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_401 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_402;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed14 <= 3'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed14 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_402 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_403;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed15 <= 14'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed15 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed15 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_403 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_404;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed16 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_404 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_405;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed17 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_405 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_406;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed18 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_406 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_407;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed19 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_407 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_408;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed20 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_408 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_409;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed21 <= 3'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed21 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_409 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_410;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed22 <= 14'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed22 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed22 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_410 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_411;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed23 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_411 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_412;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed24 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_412 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_413;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed25 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_413 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_414;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed26 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_414 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_415;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed27 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_415 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_rx = vns_regs1;
+assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset);
+
+always @(posedge iodelay_clk) begin
+ if ((soc_reset_counter != 1'd0)) begin
+ soc_reset_counter <= (soc_reset_counter - 1'd1);
+ end else begin
+ soc_ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ soc_reset_counter <= 4'd15;
+ soc_ic_reset <= 1'd1;
+ end
+end
+
+always @(posedge sys_clk) begin
+ if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin
+ if (soc_litedramcore_soccontroller_bus_error) begin
+ soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1);
+ end
+ end
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
+ if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1;
+ end
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
+ if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1;
+ end
+ soc_litedramcore_sink_ready <= 1'd0;
+ if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin
+ soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data;
+ soc_litedramcore_tx_bitcount <= 1'd0;
+ soc_litedramcore_tx_busy <= 1'd1;
+ serial_tx <= 1'd0;
+ end else begin
+ if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin
+ soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1);
+ if ((soc_litedramcore_tx_bitcount == 4'd8)) begin
+ serial_tx <= 1'd1;
+ end else begin
+ if ((soc_litedramcore_tx_bitcount == 4'd9)) begin
+ serial_tx <= 1'd1;
+ soc_litedramcore_tx_busy <= 1'd0;
+ soc_litedramcore_sink_ready <= 1'd1;
+ end else begin
+ serial_tx <= soc_litedramcore_tx_reg[0];
+ soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]};
+ end
+ end
+ end
+ end
+ if (soc_litedramcore_tx_busy) begin
+ {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage);
+ end else begin
+ {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0;
+ end
+ soc_litedramcore_source_valid <= 1'd0;
+ soc_litedramcore_rx_r <= soc_litedramcore_rx;
+ if ((~soc_litedramcore_rx_busy)) begin
+ if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin
+ soc_litedramcore_rx_busy <= 1'd1;
+ soc_litedramcore_rx_bitcount <= 1'd0;
+ end
+ end else begin
+ if (soc_litedramcore_uart_clk_rxen) begin
+ soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1);
+ if ((soc_litedramcore_rx_bitcount == 1'd0)) begin
+ if (soc_litedramcore_rx) begin
+ soc_litedramcore_rx_busy <= 1'd0;
+ end
+ end else begin
+ if ((soc_litedramcore_rx_bitcount == 4'd9)) begin
+ soc_litedramcore_rx_busy <= 1'd0;
+ if (soc_litedramcore_rx) begin
+ soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg;
+ soc_litedramcore_source_valid <= 1'd1;
+ end
+ end else begin
+ soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]};
+ end
+ end
+ end
+ end
+ if (soc_litedramcore_rx_busy) begin
+ {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage);
+ end else begin
+ {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648;
+ end
+ if (soc_litedramcore_uart_tx_clear) begin
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ end
+ soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger;
+ if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin
+ soc_litedramcore_uart_tx_pending <= 1'd1;
+ end
+ if (soc_litedramcore_uart_rx_clear) begin
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ end
+ soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger;
+ if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin
+ soc_litedramcore_uart_rx_pending <= 1'd1;
+ end
+ if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd1;
+ end else begin
+ if (soc_litedramcore_uart_tx_fifo_re) begin
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ end
+ end
+ if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
+ soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1);
+ end
+ if (soc_litedramcore_uart_tx_fifo_do_read) begin
+ soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1);
+ end
+ if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
+ if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin
+ soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_uart_tx_fifo_do_read) begin
+ soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1);
+ end
+ end
+ if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd1;
+ end else begin
+ if (soc_litedramcore_uart_rx_fifo_re) begin
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ end
+ end
+ if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
+ soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1);
+ end
+ if (soc_litedramcore_uart_rx_fifo_do_read) begin
+ soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1);
+ end
+ if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
+ if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin
+ soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_uart_rx_fifo_do_read) begin
+ soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1);
+ end
+ end
+ if (soc_litedramcore_uart_reset) begin
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ soc_litedramcore_uart_tx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ soc_litedramcore_uart_rx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
+ end
+ if (soc_litedramcore_timer_en_storage) begin
+ if ((soc_litedramcore_timer_value == 1'd0)) begin
+ soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage;
+ end else begin
+ soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1);
+ end
+ end else begin
+ soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage;
+ end
+ if (soc_litedramcore_timer_update_value_re) begin
+ soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value;
+ end
+ if (soc_litedramcore_timer_zero_clear) begin
+ soc_litedramcore_timer_zero_pending <= 1'd0;
+ end
+ soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger;
+ if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin
+ soc_litedramcore_timer_zero_pending <= 1'd1;
+ end
+ vns_wb2csr_state <= vns_wb2csr_next_state;
+ soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
+ soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip0_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip1_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip2_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip3_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip4_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip5_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip6_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip7_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip8_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip9_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip10_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip11_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip12_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip13_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip14_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip15_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
+ if (soc_sdram_inti_p0_rddata_valid) begin
+ soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata;
+ end
+ if (soc_sdram_inti_p1_rddata_valid) begin
+ soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata;
+ end
+ if (soc_sdram_inti_p2_rddata_valid) begin
+ soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata;
+ end
+ if (soc_sdram_inti_p3_rddata_valid) begin
+ soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata;
+ end
+ if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin
+ soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1);
+ end else begin
+ soc_sdram_timer_count1 <= 10'd781;
+ end
+ soc_sdram_postponer_req_o <= 1'd0;
+ if (soc_sdram_postponer_req_i) begin
+ soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1);
+ if ((soc_sdram_postponer_count == 1'd0)) begin
+ soc_sdram_postponer_count <= 1'd0;
+ soc_sdram_postponer_req_o <= 1'd1;
+ end
+ end
+ if (soc_sdram_sequencer_start0) begin
+ soc_sdram_sequencer_count <= 1'd0;
+ end else begin
+ if (soc_sdram_sequencer_done1) begin
+ if ((soc_sdram_sequencer_count != 1'd0)) begin
+ soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1);
+ end
+ end
+ end
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd0;
+ if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin
+ soc_sdram_cmd_payload_a <= 11'd1024;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_sequencer_counter == 2'd3)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd1;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ end
+ if ((soc_sdram_sequencer_counter == 6'd35)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd1;
+ end
+ if ((soc_sdram_sequencer_counter == 6'd35)) begin
+ soc_sdram_sequencer_counter <= 1'd0;
+ end else begin
+ if ((soc_sdram_sequencer_counter != 1'd0)) begin
+ soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1);
+ end else begin
+ if (soc_sdram_sequencer_start1) begin
+ soc_sdram_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin
+ soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1);
+ end else begin
+ soc_sdram_zqcs_timer_count1 <= 27'd99999999;
+ end
+ soc_sdram_zqcs_executer_done <= 1'd0;
+ if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin
+ soc_sdram_cmd_payload_a <= 11'd1024;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_zqcs_executer_done <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
+ soc_sdram_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin
+ soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (soc_sdram_zqcs_executer_start) begin
+ soc_sdram_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ vns_refresher_state <= vns_refresher_next_state;
+ if (soc_sdram_bankmachine0_row_close) begin
+ soc_sdram_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine0_row_open) begin
+ soc_sdram_bankmachine0_row_opened <= 1'd1;
+ soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first;
+ soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last;
+ soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine0_twtpcon_valid) begin
+ soc_sdram_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin
+ soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine0_trccon_valid) begin
+ soc_sdram_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_trccon_ready)) begin
+ soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine0_trascon_valid) begin
+ soc_sdram_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine0_state <= vns_bankmachine0_next_state;
+ if (soc_sdram_bankmachine1_row_close) begin
+ soc_sdram_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine1_row_open) begin
+ soc_sdram_bankmachine1_row_opened <= 1'd1;
+ soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first;
+ soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last;
+ soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine1_twtpcon_valid) begin
+ soc_sdram_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin
+ soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine1_trccon_valid) begin
+ soc_sdram_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_trccon_ready)) begin
+ soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine1_trascon_valid) begin
+ soc_sdram_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine1_state <= vns_bankmachine1_next_state;
+ if (soc_sdram_bankmachine2_row_close) begin
+ soc_sdram_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine2_row_open) begin
+ soc_sdram_bankmachine2_row_opened <= 1'd1;
+ soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first;
+ soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last;
+ soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine2_twtpcon_valid) begin
+ soc_sdram_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin
+ soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine2_trccon_valid) begin
+ soc_sdram_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_trccon_ready)) begin
+ soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine2_trascon_valid) begin
+ soc_sdram_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine2_state <= vns_bankmachine2_next_state;
+ if (soc_sdram_bankmachine3_row_close) begin
+ soc_sdram_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine3_row_open) begin
+ soc_sdram_bankmachine3_row_opened <= 1'd1;
+ soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first;
+ soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last;
+ soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine3_twtpcon_valid) begin
+ soc_sdram_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin
+ soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine3_trccon_valid) begin
+ soc_sdram_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_trccon_ready)) begin
+ soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine3_trascon_valid) begin
+ soc_sdram_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine3_state <= vns_bankmachine3_next_state;
+ if (soc_sdram_bankmachine4_row_close) begin
+ soc_sdram_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine4_row_open) begin
+ soc_sdram_bankmachine4_row_opened <= 1'd1;
+ soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first;
+ soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last;
+ soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine4_twtpcon_valid) begin
+ soc_sdram_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin
+ soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine4_trccon_valid) begin
+ soc_sdram_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_trccon_ready)) begin
+ soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine4_trascon_valid) begin
+ soc_sdram_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine4_state <= vns_bankmachine4_next_state;
+ if (soc_sdram_bankmachine5_row_close) begin
+ soc_sdram_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine5_row_open) begin
+ soc_sdram_bankmachine5_row_opened <= 1'd1;
+ soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first;
+ soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last;
+ soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine5_twtpcon_valid) begin
+ soc_sdram_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin
+ soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine5_trccon_valid) begin
+ soc_sdram_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_trccon_ready)) begin
+ soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine5_trascon_valid) begin
+ soc_sdram_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine5_state <= vns_bankmachine5_next_state;
+ if (soc_sdram_bankmachine6_row_close) begin
+ soc_sdram_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine6_row_open) begin
+ soc_sdram_bankmachine6_row_opened <= 1'd1;
+ soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first;
+ soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last;
+ soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine6_twtpcon_valid) begin
+ soc_sdram_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin
+ soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine6_trccon_valid) begin
+ soc_sdram_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_trccon_ready)) begin
+ soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine6_trascon_valid) begin
+ soc_sdram_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine6_state <= vns_bankmachine6_next_state;
+ if (soc_sdram_bankmachine7_row_close) begin
+ soc_sdram_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine7_row_open) begin
+ soc_sdram_bankmachine7_row_opened <= 1'd1;
+ soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first;
+ soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last;
+ soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine7_twtpcon_valid) begin
+ soc_sdram_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin
+ soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine7_trccon_valid) begin
+ soc_sdram_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_trccon_ready)) begin
+ soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine7_trascon_valid) begin
+ soc_sdram_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine7_state <= vns_bankmachine7_next_state;
+ if ((~soc_sdram_en0)) begin
+ soc_sdram_time0 <= 5'd31;
+ end else begin
+ if ((~soc_sdram_max_time0)) begin
+ soc_sdram_time0 <= (soc_sdram_time0 - 1'd1);
+ end
+ end
+ if ((~soc_sdram_en1)) begin
+ soc_sdram_time1 <= 4'd15;
+ end else begin
+ if ((~soc_sdram_max_time1)) begin
+ soc_sdram_time1 <= (soc_sdram_time1 - 1'd1);
+ end
+ end
+ if (soc_sdram_choose_cmd_ce) begin
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (soc_sdram_choose_req_ce) begin
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ soc_sdram_dfi_p0_cs_n <= 1'd0;
+ soc_sdram_dfi_p0_bank <= vns_array_muxed0;
+ soc_sdram_dfi_p0_address <= vns_array_muxed1;
+ soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
+ soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
+ soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
+ soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
+ soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
+ soc_sdram_dfi_p1_cs_n <= 1'd0;
+ soc_sdram_dfi_p1_bank <= vns_array_muxed7;
+ soc_sdram_dfi_p1_address <= vns_array_muxed8;
+ soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
+ soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
+ soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
+ soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
+ soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
+ soc_sdram_dfi_p2_cs_n <= 1'd0;
+ soc_sdram_dfi_p2_bank <= vns_array_muxed14;
+ soc_sdram_dfi_p2_address <= vns_array_muxed15;
+ soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
+ soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
+ soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
+ soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
+ soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
+ soc_sdram_dfi_p3_cs_n <= 1'd0;
+ soc_sdram_dfi_p3_bank <= vns_array_muxed21;
+ soc_sdram_dfi_p3_address <= vns_array_muxed22;
+ soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
+ soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
+ soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
+ soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
+ soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
+ if (soc_sdram_trrdcon_valid) begin
+ soc_sdram_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ soc_sdram_trrdcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_trrdcon_ready)) begin
+ soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1);
+ if ((soc_sdram_trrdcon_count == 1'd1)) begin
+ soc_sdram_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid};
+ if ((soc_sdram_tfawcon_count < 3'd4)) begin
+ if ((soc_sdram_tfawcon_count == 2'd3)) begin
+ soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid);
+ end else begin
+ soc_sdram_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (soc_sdram_tccdcon_valid) begin
+ soc_sdram_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ soc_sdram_tccdcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_tccdcon_ready)) begin
+ soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1);
+ if ((soc_sdram_tccdcon_count == 1'd1)) begin
+ soc_sdram_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_twtrcon_valid) begin
+ soc_sdram_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_twtrcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_twtrcon_ready)) begin
+ soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1);
+ if ((soc_sdram_twtrcon_count == 1'd1)) begin
+ soc_sdram_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_multiplexer_state <= vns_multiplexer_next_state;
+ vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
+ vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
+ vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3;
+ vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4;
+ vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
+ vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
+ vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
+ vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
+ vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
+ vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
+ vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
+ vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
+ vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9;
+ vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10;
+ vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11;
+ vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12;
+ vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13;
+ vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14;
+ vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15;
+ vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16;
+ if (vns_roundrobin0_ce) begin
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ if (vns_roundrobin0_request[1]) begin
+ vns_roundrobin0_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin0_request[0]) begin
+ vns_roundrobin0_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin1_ce) begin
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ if (vns_roundrobin1_request[1]) begin
+ vns_roundrobin1_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin1_request[0]) begin
+ vns_roundrobin1_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin2_ce) begin
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ if (vns_roundrobin2_request[1]) begin
+ vns_roundrobin2_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin2_request[0]) begin
+ vns_roundrobin2_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin3_ce) begin
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ if (vns_roundrobin3_request[1]) begin
+ vns_roundrobin3_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin3_request[0]) begin
+ vns_roundrobin3_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin4_ce) begin
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ if (vns_roundrobin4_request[1]) begin
+ vns_roundrobin4_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin4_request[0]) begin
+ vns_roundrobin4_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin5_ce) begin
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ if (vns_roundrobin5_request[1]) begin
+ vns_roundrobin5_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin5_request[0]) begin
+ vns_roundrobin5_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin6_ce) begin
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ if (vns_roundrobin6_request[1]) begin
+ vns_roundrobin6_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin6_request[0]) begin
+ vns_roundrobin6_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin7_ce) begin
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ if (vns_roundrobin7_request[1]) begin
+ vns_roundrobin7_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin7_request[0]) begin
+ vns_roundrobin7_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (soc_counter_reset) begin
+ soc_counter <= 1'd0;
+ end else begin
+ if (soc_counter_ce) begin
+ soc_counter <= (soc_counter + 1'd1);
+ end
+ end
+ if (soc_address_ce) begin
+ soc_address_q <= soc_address_d;
+ end
+ if (soc_address_reset) begin
+ soc_address_q <= 30'd0;
+ end
+ if (soc_need_refill_ce) begin
+ soc_need_refill_q <= soc_need_refill_d;
+ end
+ if (soc_need_refill_reset) begin
+ soc_need_refill_q <= 1'd1;
+ end
+ vns_converter_state <= vns_converter_next_state;
+ if (soc_cached_datas_ce0) begin
+ soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d;
+ end
+ if (soc_cached_datas_reset0) begin
+ soc_cached_datas_flipflop0_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce1) begin
+ soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d;
+ end
+ if (soc_cached_datas_reset1) begin
+ soc_cached_datas_flipflop1_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce2) begin
+ soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d;
+ end
+ if (soc_cached_datas_reset2) begin
+ soc_cached_datas_flipflop2_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce3) begin
+ soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d;
+ end
+ if (soc_cached_datas_reset3) begin
+ soc_cached_datas_flipflop3_q <= 32'd0;
+ end
+ if (soc_cached_sels_ce0) begin
+ soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d;
+ end
+ if (soc_cached_sels_reset0) begin
+ soc_cached_sels_flipflop0_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce1) begin
+ soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d;
+ end
+ if (soc_cached_sels_reset1) begin
+ soc_cached_sels_flipflop1_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce2) begin
+ soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d;
+ end
+ if (soc_cached_sels_reset2) begin
+ soc_cached_sels_flipflop2_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce3) begin
+ soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d;
+ end
+ if (soc_cached_sels_reset3) begin
+ soc_cached_sels_flipflop3_q <= 4'd0;
+ end
+ vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
+ if (soc_count_next_value_ce) begin
+ soc_count <= soc_count_next_value;
+ end
+ case (vns_grant)
+ 1'd0: begin
+ if ((~vns_request[0])) begin
+ if (vns_request[1]) begin
+ vns_grant <= 1'd1;
+ end
+ end
+ end
+ 1'd1: begin
+ if ((~vns_request[1])) begin
+ if (vns_request[0]) begin
+ vns_grant <= 1'd0;
+ end
+ end
+ end
+ endcase
+ vns_slave_sel_r <= vns_slave_sel;
+ if (vns_wait) begin
+ if ((~vns_done)) begin
+ vns_count <= (vns_count - 1'd1);
+ end
+ end else begin
+ vns_count <= 20'd1000000;
+ end
+ vns_interface0_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank0_sel) begin
+ case (vns_interface0_bank_bus_adr[3:0])
+ 1'd0: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w;
+ end
+ 1'd1: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w;
+ end
+ 2'd2: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w;
+ end
+ 2'd3: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w;
+ end
+ 3'd4: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w;
+ end
+ 3'd5: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w;
+ end
+ 3'd6: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w;
+ end
+ 3'd7: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w;
+ end
+ 4'd8: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank0_reset0_re) begin
+ soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r;
+ end
+ soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re;
+ if (vns_csrbank0_scratch3_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r;
+ end
+ if (vns_csrbank0_scratch2_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r;
+ end
+ if (vns_csrbank0_scratch1_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r;
+ end
+ if (vns_csrbank0_scratch0_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r;
+ end
+ soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re;
+ vns_interface1_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank1_sel) begin
+ case (vns_interface1_bank_bus_adr[0])
+ 1'd0: begin
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w;
+ end
+ 1'd1: begin
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank1_init_done0_re) begin
+ soc_init_done_storage <= vns_csrbank1_init_done0_r;
+ end
+ soc_init_done_re <= vns_csrbank1_init_done0_re;
+ if (vns_csrbank1_init_error0_re) begin
+ soc_init_error_storage <= vns_csrbank1_init_error0_r;
+ end
+ soc_init_error_re <= vns_csrbank1_init_error0_re;
+ vns_interface2_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank2_sel) begin
+ case (vns_interface2_bank_bus_adr[3:0])
+ 1'd0: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w;
+ end
+ 1'd1: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w;
+ end
+ 2'd2: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
+ end
+ 2'd3: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
+ end
+ 3'd4: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
+ end
+ 3'd5: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w;
+ end
+ 3'd6: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd7: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
+ end
+ 4'd8: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd9: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
+ end
+ endcase
+ end
+ if (vns_csrbank2_half_sys8x_taps0_re) begin
+ soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r;
+ end
+ soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re;
+ if (vns_csrbank2_wlevel_en0_re) begin
+ soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r;
+ end
+ soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re;
+ if (vns_csrbank2_dly_sel0_re) begin
+ soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r;
+ end
+ soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re;
+ vns_interface3_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank3_sel) begin
+ case (vns_interface3_bank_bus_adr[5:0])
+ 1'd0: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w;
+ end
+ 1'd1: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w;
+ end
+ 3'd4: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w;
+ end
+ 3'd5: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w;
+ end
+ 3'd6: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w;
+ end
+ 3'd7: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w;
+ end
+ 4'd8: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w;
+ end
+ 4'd9: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w;
+ end
+ 4'd10: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w;
+ end
+ 4'd11: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w;
+ end
+ 4'd12: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w;
+ end
+ 4'd13: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w;
+ end
+ 4'd14: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w;
+ end
+ 4'd15: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w;
+ end
+ 5'd16: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w;
+ end
+ 5'd17: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w;
+ end
+ 5'd18: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w;
+ end
+ 5'd19: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w;
+ end
+ 5'd20: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w;
+ end
+ 5'd21: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w;
+ end
+ 5'd22: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w;
+ end
+ 5'd23: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w;
+ end
+ 5'd24: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w;
+ end
+ 5'd25: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w;
+ end
+ 5'd26: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w;
+ end
+ 5'd27: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w;
+ end
+ 5'd28: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w;
+ end
+ 5'd29: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w;
+ end
+ 5'd30: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w;
+ end
+ 5'd31: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w;
+ end
+ 6'd32: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w;
+ end
+ 6'd33: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w;
+ end
+ 6'd34: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w;
+ end
+ 6'd35: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w;
+ end
+ 6'd36: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w;
+ end
+ 6'd37: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w;
+ end
+ 6'd38: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w;
+ end
+ 6'd39: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w;
+ end
+ 6'd40: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w;
+ end
+ 6'd41: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w;
+ end
+ 6'd42: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w;
+ end
+ 6'd43: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w;
+ end
+ 6'd44: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w;
+ end
+ 6'd45: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w;
+ end
+ 6'd46: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w;
+ end
+ 6'd47: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w;
+ end
+ 6'd48: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w;
+ end
+ 6'd49: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w;
+ end
+ 6'd50: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w;
+ end
+ 6'd51: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w;
+ end
+ 6'd52: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank3_dfii_control0_re) begin
+ soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r;
+ end
+ soc_sdram_re <= vns_csrbank3_dfii_control0_re;
+ if (vns_csrbank3_dfii_pi0_command0_re) begin
+ soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r;
+ end
+ soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re;
+ if (vns_csrbank3_dfii_pi0_address1_re) begin
+ soc_sdram_phaseinjector0_address_storage[13:8] <= vns_csrbank3_dfii_pi0_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi0_address0_re) begin
+ soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r;
+ end
+ soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re;
+ if (vns_csrbank3_dfii_pi0_baddress0_re) begin
+ soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r;
+ end
+ soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re;
+ if (vns_csrbank3_dfii_pi0_wrdata3_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata2_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata1_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata0_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r;
+ end
+ soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re;
+ if (vns_csrbank3_dfii_pi1_command0_re) begin
+ soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r;
+ end
+ soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re;
+ if (vns_csrbank3_dfii_pi1_address1_re) begin
+ soc_sdram_phaseinjector1_address_storage[13:8] <= vns_csrbank3_dfii_pi1_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi1_address0_re) begin
+ soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r;
+ end
+ soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re;
+ if (vns_csrbank3_dfii_pi1_baddress0_re) begin
+ soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r;
+ end
+ soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re;
+ if (vns_csrbank3_dfii_pi1_wrdata3_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata2_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata1_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata0_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r;
+ end
+ soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re;
+ if (vns_csrbank3_dfii_pi2_command0_re) begin
+ soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r;
+ end
+ soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re;
+ if (vns_csrbank3_dfii_pi2_address1_re) begin
+ soc_sdram_phaseinjector2_address_storage[13:8] <= vns_csrbank3_dfii_pi2_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi2_address0_re) begin
+ soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r;
+ end
+ soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re;
+ if (vns_csrbank3_dfii_pi2_baddress0_re) begin
+ soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r;
+ end
+ soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re;
+ if (vns_csrbank3_dfii_pi2_wrdata3_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata2_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata1_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata0_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r;
+ end
+ soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re;
+ if (vns_csrbank3_dfii_pi3_command0_re) begin
+ soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r;
+ end
+ soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re;
+ if (vns_csrbank3_dfii_pi3_address1_re) begin
+ soc_sdram_phaseinjector3_address_storage[13:8] <= vns_csrbank3_dfii_pi3_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi3_address0_re) begin
+ soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r;
+ end
+ soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re;
+ if (vns_csrbank3_dfii_pi3_baddress0_re) begin
+ soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r;
+ end
+ soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re;
+ if (vns_csrbank3_dfii_pi3_wrdata3_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata2_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata1_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata0_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r;
+ end
+ soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re;
+ vns_interface4_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank4_sel) begin
+ case (vns_interface4_bank_bus_adr[4:0])
+ 1'd0: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w;
+ end
+ 1'd1: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w;
+ end
+ 2'd2: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w;
+ end
+ 2'd3: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w;
+ end
+ 3'd4: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w;
+ end
+ 3'd5: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w;
+ end
+ 3'd6: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w;
+ end
+ 3'd7: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w;
+ end
+ 4'd8: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w;
+ end
+ 4'd9: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w;
+ end
+ 4'd10: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w;
+ end
+ 4'd11: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w;
+ end
+ 4'd12: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w;
+ end
+ 4'd13: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w;
+ end
+ 4'd14: begin
+ vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w;
+ end
+ 4'd15: begin
+ vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w;
+ end
+ 5'd16: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank4_load3_re) begin
+ soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r;
+ end
+ if (vns_csrbank4_load2_re) begin
+ soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r;
+ end
+ if (vns_csrbank4_load1_re) begin
+ soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r;
+ end
+ if (vns_csrbank4_load0_re) begin
+ soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r;
+ end
+ soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re;
+ if (vns_csrbank4_reload3_re) begin
+ soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r;
+ end
+ if (vns_csrbank4_reload2_re) begin
+ soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r;
+ end
+ if (vns_csrbank4_reload1_re) begin
+ soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r;
+ end
+ if (vns_csrbank4_reload0_re) begin
+ soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r;
+ end
+ soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re;
+ if (vns_csrbank4_en0_re) begin
+ soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r;
+ end
+ soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re;
+ if (vns_csrbank4_update_value0_re) begin
+ soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r;
+ end
+ soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re;
+ if (vns_csrbank4_ev_enable0_re) begin
+ soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r;
+ end
+ soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re;
+ vns_interface5_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank5_sel) begin
+ case (vns_interface5_bank_bus_adr[2:0])
+ 1'd0: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w;
+ end
+ 1'd1: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w;
+ end
+ 2'd2: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w;
+ end
+ 2'd3: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w;
+ end
+ 3'd4: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w;
+ end
+ 3'd5: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank5_ev_enable0_re) begin
+ soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r;
+ end
+ soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re;
+ vns_interface6_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank6_sel) begin
+ case (vns_interface6_bank_bus_adr[1:0])
+ 1'd0: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w;
+ end
+ 1'd1: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w;
+ end
+ 2'd2: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w;
+ end
+ 2'd3: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank6_tuning_word3_re) begin
+ soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r;
+ end
+ if (vns_csrbank6_tuning_word2_re) begin
+ soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r;
+ end
+ if (vns_csrbank6_tuning_word1_re) begin
+ soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r;
+ end
+ if (vns_csrbank6_tuning_word0_re) begin
+ soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r;
+ end
+ soc_litedramcore_re <= vns_csrbank6_tuning_word0_re;
+ if (sys_rst) begin
+ soc_litedramcore_soccontroller_reset_storage <= 1'd0;
+ soc_litedramcore_soccontroller_reset_re <= 1'd0;
+ soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896;
+ soc_litedramcore_soccontroller_scratch_re <= 1'd0;
+ soc_litedramcore_soccontroller_bus_errors <= 32'd0;
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
+ serial_tx <= 1'd1;
+ soc_litedramcore_storage <= 32'd4947802;
+ soc_litedramcore_re <= 1'd0;
+ soc_litedramcore_sink_ready <= 1'd0;
+ soc_litedramcore_uart_clk_txen <= 1'd0;
+ soc_litedramcore_tx_busy <= 1'd0;
+ soc_litedramcore_source_valid <= 1'd0;
+ soc_litedramcore_uart_clk_rxen <= 1'd0;
+ soc_litedramcore_rx_r <= 1'd0;
+ soc_litedramcore_rx_busy <= 1'd0;
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ soc_litedramcore_uart_tx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ soc_litedramcore_uart_rx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_eventmanager_storage <= 2'd0;
+ soc_litedramcore_uart_eventmanager_re <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
+ soc_litedramcore_timer_load_storage <= 32'd0;
+ soc_litedramcore_timer_load_re <= 1'd0;
+ soc_litedramcore_timer_reload_storage <= 32'd0;
+ soc_litedramcore_timer_reload_re <= 1'd0;
+ soc_litedramcore_timer_en_storage <= 1'd0;
+ soc_litedramcore_timer_en_re <= 1'd0;
+ soc_litedramcore_timer_update_value_storage <= 1'd0;
+ soc_litedramcore_timer_update_value_re <= 1'd0;
+ soc_litedramcore_timer_value_status <= 32'd0;
+ soc_litedramcore_timer_zero_pending <= 1'd0;
+ soc_litedramcore_timer_zero_old_trigger <= 1'd0;
+ soc_litedramcore_timer_eventmanager_storage <= 1'd0;
+ soc_litedramcore_timer_eventmanager_re <= 1'd0;
+ soc_litedramcore_timer_value <= 32'd0;
+ soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ soc_a7ddrphy_wlevel_en_storage <= 1'd0;
+ soc_a7ddrphy_wlevel_en_re <= 1'd0;
+ soc_a7ddrphy_dly_sel_storage <= 2'd0;
+ soc_a7ddrphy_dly_sel_re <= 1'd0;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
+ soc_a7ddrphy_dqspattern_o1 <= 8'd0;
+ soc_a7ddrphy_dq_oe_delayed <= 1'd0;
+ soc_a7ddrphy_bitslip0_value <= 3'd0;
+ soc_a7ddrphy_bitslip1_value <= 3'd0;
+ soc_a7ddrphy_bitslip2_value <= 3'd0;
+ soc_a7ddrphy_bitslip3_value <= 3'd0;
+ soc_a7ddrphy_bitslip4_value <= 3'd0;
+ soc_a7ddrphy_bitslip5_value <= 3'd0;
+ soc_a7ddrphy_bitslip6_value <= 3'd0;
+ soc_a7ddrphy_bitslip7_value <= 3'd0;
+ soc_a7ddrphy_bitslip8_value <= 3'd0;
+ soc_a7ddrphy_bitslip9_value <= 3'd0;
+ soc_a7ddrphy_bitslip10_value <= 3'd0;
+ soc_a7ddrphy_bitslip11_value <= 3'd0;
+ soc_a7ddrphy_bitslip12_value <= 3'd0;
+ soc_a7ddrphy_bitslip13_value <= 3'd0;
+ soc_a7ddrphy_bitslip14_value <= 3'd0;
+ soc_a7ddrphy_bitslip15_value <= 3'd0;
+ soc_a7ddrphy_rddata_en_last <= 8'd0;
+ soc_a7ddrphy_wrdata_en_last <= 4'd0;
+ soc_sdram_storage <= 4'd0;
+ soc_sdram_re <= 1'd0;
+ soc_sdram_phaseinjector0_command_storage <= 6'd0;
+ soc_sdram_phaseinjector0_command_re <= 1'd0;
+ soc_sdram_phaseinjector0_address_re <= 1'd0;
+ soc_sdram_phaseinjector0_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector0_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector0_status <= 32'd0;
+ soc_sdram_phaseinjector1_command_storage <= 6'd0;
+ soc_sdram_phaseinjector1_command_re <= 1'd0;
+ soc_sdram_phaseinjector1_address_re <= 1'd0;
+ soc_sdram_phaseinjector1_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector1_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector1_status <= 32'd0;
+ soc_sdram_phaseinjector2_command_storage <= 6'd0;
+ soc_sdram_phaseinjector2_command_re <= 1'd0;
+ soc_sdram_phaseinjector2_address_re <= 1'd0;
+ soc_sdram_phaseinjector2_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector2_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector2_status <= 32'd0;
+ soc_sdram_phaseinjector3_command_storage <= 6'd0;
+ soc_sdram_phaseinjector3_command_re <= 1'd0;
+ soc_sdram_phaseinjector3_address_re <= 1'd0;
+ soc_sdram_phaseinjector3_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector3_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector3_status <= 32'd0;
+ soc_sdram_dfi_p0_address <= 14'd0;
+ soc_sdram_dfi_p0_bank <= 3'd0;
+ soc_sdram_dfi_p0_cas_n <= 1'd1;
+ soc_sdram_dfi_p0_cs_n <= 1'd1;
+ soc_sdram_dfi_p0_ras_n <= 1'd1;
+ soc_sdram_dfi_p0_we_n <= 1'd1;
+ soc_sdram_dfi_p0_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p0_rddata_en <= 1'd0;
+ soc_sdram_dfi_p1_address <= 14'd0;
+ soc_sdram_dfi_p1_bank <= 3'd0;
+ soc_sdram_dfi_p1_cas_n <= 1'd1;
+ soc_sdram_dfi_p1_cs_n <= 1'd1;
+ soc_sdram_dfi_p1_ras_n <= 1'd1;
+ soc_sdram_dfi_p1_we_n <= 1'd1;
+ soc_sdram_dfi_p1_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p1_rddata_en <= 1'd0;
+ soc_sdram_dfi_p2_address <= 14'd0;
+ soc_sdram_dfi_p2_bank <= 3'd0;
+ soc_sdram_dfi_p2_cas_n <= 1'd1;
+ soc_sdram_dfi_p2_cs_n <= 1'd1;
+ soc_sdram_dfi_p2_ras_n <= 1'd1;
+ soc_sdram_dfi_p2_we_n <= 1'd1;
+ soc_sdram_dfi_p2_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p2_rddata_en <= 1'd0;
+ soc_sdram_dfi_p3_address <= 14'd0;
+ soc_sdram_dfi_p3_bank <= 3'd0;
+ soc_sdram_dfi_p3_cas_n <= 1'd1;
+ soc_sdram_dfi_p3_cs_n <= 1'd1;
+ soc_sdram_dfi_p3_ras_n <= 1'd1;
+ soc_sdram_dfi_p3_we_n <= 1'd1;
+ soc_sdram_dfi_p3_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p3_rddata_en <= 1'd0;
+ soc_sdram_timer_count1 <= 10'd781;
+ soc_sdram_postponer_req_o <= 1'd0;
+ soc_sdram_postponer_count <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd0;
+ soc_sdram_sequencer_counter <= 6'd0;
+ soc_sdram_sequencer_count <= 1'd0;
+ soc_sdram_zqcs_timer_count1 <= 27'd99999999;
+ soc_sdram_zqcs_executer_done <= 1'd0;
+ soc_sdram_zqcs_executer_counter <= 5'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine0_row <= 14'd0;
+ soc_sdram_bankmachine0_row_opened <= 1'd0;
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine0_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine0_trccon_count <= 3'd0;
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine0_trascon_count <= 3'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine1_row <= 14'd0;
+ soc_sdram_bankmachine1_row_opened <= 1'd0;
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine1_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine1_trccon_count <= 3'd0;
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine1_trascon_count <= 3'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine2_row <= 14'd0;
+ soc_sdram_bankmachine2_row_opened <= 1'd0;
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine2_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine2_trccon_count <= 3'd0;
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine2_trascon_count <= 3'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine3_row <= 14'd0;
+ soc_sdram_bankmachine3_row_opened <= 1'd0;
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine3_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine3_trccon_count <= 3'd0;
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine3_trascon_count <= 3'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine4_row <= 14'd0;
+ soc_sdram_bankmachine4_row_opened <= 1'd0;
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine4_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine4_trccon_count <= 3'd0;
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine4_trascon_count <= 3'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine5_row <= 14'd0;
+ soc_sdram_bankmachine5_row_opened <= 1'd0;
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine5_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine5_trccon_count <= 3'd0;
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine5_trascon_count <= 3'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine6_row <= 14'd0;
+ soc_sdram_bankmachine6_row_opened <= 1'd0;
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine6_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine6_trccon_count <= 3'd0;
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine6_trascon_count <= 3'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine7_row <= 14'd0;
+ soc_sdram_bankmachine7_row_opened <= 1'd0;
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine7_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine7_trccon_count <= 3'd0;
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine7_trascon_count <= 3'd0;
+ soc_sdram_choose_cmd_grant <= 3'd0;
+ soc_sdram_choose_req_grant <= 3'd0;
+ soc_sdram_trrdcon_ready <= 1'd1;
+ soc_sdram_trrdcon_count <= 1'd0;
+ soc_sdram_tfawcon_ready <= 1'd1;
+ soc_sdram_tfawcon_window <= 5'd0;
+ soc_sdram_tccdcon_ready <= 1'd1;
+ soc_sdram_tccdcon_count <= 1'd0;
+ soc_sdram_twtrcon_ready <= 1'd1;
+ soc_sdram_twtrcon_count <= 3'd0;
+ soc_sdram_time0 <= 5'd0;
+ soc_sdram_time1 <= 4'd0;
+ soc_address_q <= 30'd0;
+ soc_counter <= 2'd0;
+ soc_need_refill_q <= 1'd1;
+ soc_cached_datas_flipflop0_q <= 32'd0;
+ soc_cached_datas_flipflop1_q <= 32'd0;
+ soc_cached_datas_flipflop2_q <= 32'd0;
+ soc_cached_datas_flipflop3_q <= 32'd0;
+ soc_cached_sels_flipflop0_q <= 4'd0;
+ soc_cached_sels_flipflop1_q <= 4'd0;
+ soc_cached_sels_flipflop2_q <= 4'd0;
+ soc_cached_sels_flipflop3_q <= 4'd0;
+ soc_count <= 1'd0;
+ soc_init_done_storage <= 1'd0;
+ soc_init_done_re <= 1'd0;
+ soc_init_error_storage <= 1'd0;
+ soc_init_error_re <= 1'd0;
+ vns_wb2csr_state <= 1'd0;
+ vns_refresher_state <= 2'd0;
+ vns_bankmachine0_state <= 4'd0;
+ vns_bankmachine1_state <= 4'd0;
+ vns_bankmachine2_state <= 4'd0;
+ vns_bankmachine3_state <= 4'd0;
+ vns_bankmachine4_state <= 4'd0;
+ vns_bankmachine5_state <= 4'd0;
+ vns_bankmachine6_state <= 4'd0;
+ vns_bankmachine7_state <= 4'd0;
+ vns_multiplexer_state <= 4'd0;
+ vns_roundrobin0_grant <= 1'd0;
+ vns_roundrobin1_grant <= 1'd0;
+ vns_roundrobin2_grant <= 1'd0;
+ vns_roundrobin3_grant <= 1'd0;
+ vns_roundrobin4_grant <= 1'd0;
+ vns_roundrobin5_grant <= 1'd0;
+ vns_roundrobin6_grant <= 1'd0;
+ vns_roundrobin7_grant <= 1'd0;
+ vns_new_master_wdata_ready0 <= 1'd0;
+ vns_new_master_wdata_ready1 <= 1'd0;
+ vns_new_master_wdata_ready2 <= 1'd0;
+ vns_new_master_wdata_ready3 <= 1'd0;
+ vns_new_master_wdata_ready4 <= 1'd0;
+ vns_new_master_wdata_ready5 <= 1'd0;
+ vns_new_master_rdata_valid0 <= 1'd0;
+ vns_new_master_rdata_valid1 <= 1'd0;
+ vns_new_master_rdata_valid2 <= 1'd0;
+ vns_new_master_rdata_valid3 <= 1'd0;
+ vns_new_master_rdata_valid4 <= 1'd0;
+ vns_new_master_rdata_valid5 <= 1'd0;
+ vns_new_master_rdata_valid6 <= 1'd0;
+ vns_new_master_rdata_valid7 <= 1'd0;
+ vns_new_master_rdata_valid8 <= 1'd0;
+ vns_new_master_rdata_valid9 <= 1'd0;
+ vns_new_master_rdata_valid10 <= 1'd0;
+ vns_new_master_rdata_valid11 <= 1'd0;
+ vns_new_master_rdata_valid12 <= 1'd0;
+ vns_new_master_rdata_valid13 <= 1'd0;
+ vns_new_master_rdata_valid14 <= 1'd0;
+ vns_new_master_rdata_valid15 <= 1'd0;
+ vns_new_master_rdata_valid16 <= 1'd0;
+ vns_new_master_rdata_valid17 <= 1'd0;
+ vns_converter_state <= 3'd0;
+ vns_litedramwishbone2native_state <= 2'd0;
+ vns_grant <= 1'd0;
+ vns_slave_sel_r <= 4'd0;
+ vns_count <= 20'd1000000;
+ end
+ vns_regs0 <= serial_rx;
+ vns_regs1 <= vns_regs0;
+end
+
+reg [31:0] mem[0:6143];
+reg [31:0] memdat;
+always @(posedge sys_clk) begin
+ memdat <= mem[soc_litedramcore_litedramcore_adr];
+end
+
+assign soc_litedramcore_litedramcore_dat_r = memdat;
+
+initial begin
+ $readmemh("litedram_core.init", mem);
+end
+
+reg [31:0] mem_1[0:1023];
+reg [9:0] memadr;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_ram_we[0])
+ mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0];
+ if (soc_litedramcore_ram_we[1])
+ mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8];
+ if (soc_litedramcore_ram_we[2])
+ mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16];
+ if (soc_litedramcore_ram_we[3])
+ mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24];
+ memadr <= soc_litedramcore_ram_adr;
+end
+
+assign soc_litedramcore_ram_dat_r = mem_1[memadr];
+
+initial begin
+ $readmemh("mem_1.init", mem_1);
+end
+
+reg [9:0] storage[0:15];
+reg [9:0] memdat_1;
+reg [9:0] memdat_2;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_tx_fifo_wrport_we)
+ storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w;
+ memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_tx_fifo_rdport_re)
+ memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr];
+end
+
+assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1;
+assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2;
+
+reg [9:0] storage_1[0:15];
+reg [9:0] memdat_3;
+reg [9:0] memdat_4;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_rx_fifo_wrport_we)
+ storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w;
+ memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_rx_fifo_rdport_re)
+ memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr];
+end
+
+assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3;
+assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4;
+
+BUFG BUFG(
+ .I(soc_s7pll0_clkout0),
+ .O(soc_s7pll0_clkout_buf0)
+);
+
+BUFG BUFG_1(
+ .I(soc_s7pll0_clkout1),
+ .O(soc_s7pll0_clkout_buf1)
+);
+
+BUFG BUFG_2(
+ .I(soc_s7pll0_clkout2),
+ .O(soc_s7pll0_clkout_buf2)
+);
+
+BUFG BUFG_3(
+ .I(soc_s7pll1_clkout),
+ .O(soc_s7pll1_clkout_buf)
+);
+
+IDELAYCTRL IDELAYCTRL(
+ .REFCLK(iodelay_clk),
+ .RST(soc_ic_reset)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(1'd0),
+ .D2(1'd1),
+ .D3(1'd0),
+ .D4(1'd1),
+ .D5(1'd0),
+ .D6(1'd1),
+ .D7(1'd0),
+ .D8(1'd1),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
+);
+
+OBUFDS OBUFDS(
+ .I(soc_a7ddrphy_sd_clk_se_nodelay),
+ .O(ddram_clk_p),
+ .OB(ddram_clk_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_1 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[0]),
+ .D2(soc_a7ddrphy_dfi_p0_address[0]),
+ .D3(soc_a7ddrphy_dfi_p1_address[0]),
+ .D4(soc_a7ddrphy_dfi_p1_address[0]),
+ .D5(soc_a7ddrphy_dfi_p2_address[0]),
+ .D6(soc_a7ddrphy_dfi_p2_address[0]),
+ .D7(soc_a7ddrphy_dfi_p3_address[0]),
+ .D8(soc_a7ddrphy_dfi_p3_address[0]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_2 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[1]),
+ .D2(soc_a7ddrphy_dfi_p0_address[1]),
+ .D3(soc_a7ddrphy_dfi_p1_address[1]),
+ .D4(soc_a7ddrphy_dfi_p1_address[1]),
+ .D5(soc_a7ddrphy_dfi_p2_address[1]),
+ .D6(soc_a7ddrphy_dfi_p2_address[1]),
+ .D7(soc_a7ddrphy_dfi_p3_address[1]),
+ .D8(soc_a7ddrphy_dfi_p3_address[1]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_3 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[2]),
+ .D2(soc_a7ddrphy_dfi_p0_address[2]),
+ .D3(soc_a7ddrphy_dfi_p1_address[2]),
+ .D4(soc_a7ddrphy_dfi_p1_address[2]),
+ .D5(soc_a7ddrphy_dfi_p2_address[2]),
+ .D6(soc_a7ddrphy_dfi_p2_address[2]),
+ .D7(soc_a7ddrphy_dfi_p3_address[2]),
+ .D8(soc_a7ddrphy_dfi_p3_address[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[2])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_4 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[3]),
+ .D2(soc_a7ddrphy_dfi_p0_address[3]),
+ .D3(soc_a7ddrphy_dfi_p1_address[3]),
+ .D4(soc_a7ddrphy_dfi_p1_address[3]),
+ .D5(soc_a7ddrphy_dfi_p2_address[3]),
+ .D6(soc_a7ddrphy_dfi_p2_address[3]),
+ .D7(soc_a7ddrphy_dfi_p3_address[3]),
+ .D8(soc_a7ddrphy_dfi_p3_address[3]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[3])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_5 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[4]),
+ .D2(soc_a7ddrphy_dfi_p0_address[4]),
+ .D3(soc_a7ddrphy_dfi_p1_address[4]),
+ .D4(soc_a7ddrphy_dfi_p1_address[4]),
+ .D5(soc_a7ddrphy_dfi_p2_address[4]),
+ .D6(soc_a7ddrphy_dfi_p2_address[4]),
+ .D7(soc_a7ddrphy_dfi_p3_address[4]),
+ .D8(soc_a7ddrphy_dfi_p3_address[4]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[4])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_6 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[5]),
+ .D2(soc_a7ddrphy_dfi_p0_address[5]),
+ .D3(soc_a7ddrphy_dfi_p1_address[5]),
+ .D4(soc_a7ddrphy_dfi_p1_address[5]),
+ .D5(soc_a7ddrphy_dfi_p2_address[5]),
+ .D6(soc_a7ddrphy_dfi_p2_address[5]),
+ .D7(soc_a7ddrphy_dfi_p3_address[5]),
+ .D8(soc_a7ddrphy_dfi_p3_address[5]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[5])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_7 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[6]),
+ .D2(soc_a7ddrphy_dfi_p0_address[6]),
+ .D3(soc_a7ddrphy_dfi_p1_address[6]),
+ .D4(soc_a7ddrphy_dfi_p1_address[6]),
+ .D5(soc_a7ddrphy_dfi_p2_address[6]),
+ .D6(soc_a7ddrphy_dfi_p2_address[6]),
+ .D7(soc_a7ddrphy_dfi_p3_address[6]),
+ .D8(soc_a7ddrphy_dfi_p3_address[6]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[6])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_8 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[7]),
+ .D2(soc_a7ddrphy_dfi_p0_address[7]),
+ .D3(soc_a7ddrphy_dfi_p1_address[7]),
+ .D4(soc_a7ddrphy_dfi_p1_address[7]),
+ .D5(soc_a7ddrphy_dfi_p2_address[7]),
+ .D6(soc_a7ddrphy_dfi_p2_address[7]),
+ .D7(soc_a7ddrphy_dfi_p3_address[7]),
+ .D8(soc_a7ddrphy_dfi_p3_address[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[7])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_9 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[8]),
+ .D2(soc_a7ddrphy_dfi_p0_address[8]),
+ .D3(soc_a7ddrphy_dfi_p1_address[8]),
+ .D4(soc_a7ddrphy_dfi_p1_address[8]),
+ .D5(soc_a7ddrphy_dfi_p2_address[8]),
+ .D6(soc_a7ddrphy_dfi_p2_address[8]),
+ .D7(soc_a7ddrphy_dfi_p3_address[8]),
+ .D8(soc_a7ddrphy_dfi_p3_address[8]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[8])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_10 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[9]),
+ .D2(soc_a7ddrphy_dfi_p0_address[9]),
+ .D3(soc_a7ddrphy_dfi_p1_address[9]),
+ .D4(soc_a7ddrphy_dfi_p1_address[9]),
+ .D5(soc_a7ddrphy_dfi_p2_address[9]),
+ .D6(soc_a7ddrphy_dfi_p2_address[9]),
+ .D7(soc_a7ddrphy_dfi_p3_address[9]),
+ .D8(soc_a7ddrphy_dfi_p3_address[9]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[9])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_11 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[10]),
+ .D2(soc_a7ddrphy_dfi_p0_address[10]),
+ .D3(soc_a7ddrphy_dfi_p1_address[10]),
+ .D4(soc_a7ddrphy_dfi_p1_address[10]),
+ .D5(soc_a7ddrphy_dfi_p2_address[10]),
+ .D6(soc_a7ddrphy_dfi_p2_address[10]),
+ .D7(soc_a7ddrphy_dfi_p3_address[10]),
+ .D8(soc_a7ddrphy_dfi_p3_address[10]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[10])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_12 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[11]),
+ .D2(soc_a7ddrphy_dfi_p0_address[11]),
+ .D3(soc_a7ddrphy_dfi_p1_address[11]),
+ .D4(soc_a7ddrphy_dfi_p1_address[11]),
+ .D5(soc_a7ddrphy_dfi_p2_address[11]),
+ .D6(soc_a7ddrphy_dfi_p2_address[11]),
+ .D7(soc_a7ddrphy_dfi_p3_address[11]),
+ .D8(soc_a7ddrphy_dfi_p3_address[11]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[11])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_13 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[12]),
+ .D2(soc_a7ddrphy_dfi_p0_address[12]),
+ .D3(soc_a7ddrphy_dfi_p1_address[12]),
+ .D4(soc_a7ddrphy_dfi_p1_address[12]),
+ .D5(soc_a7ddrphy_dfi_p2_address[12]),
+ .D6(soc_a7ddrphy_dfi_p2_address[12]),
+ .D7(soc_a7ddrphy_dfi_p3_address[12]),
+ .D8(soc_a7ddrphy_dfi_p3_address[12]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[12])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_14 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[13]),
+ .D2(soc_a7ddrphy_dfi_p0_address[13]),
+ .D3(soc_a7ddrphy_dfi_p1_address[13]),
+ .D4(soc_a7ddrphy_dfi_p1_address[13]),
+ .D5(soc_a7ddrphy_dfi_p2_address[13]),
+ .D6(soc_a7ddrphy_dfi_p2_address[13]),
+ .D7(soc_a7ddrphy_dfi_p3_address[13]),
+ .D8(soc_a7ddrphy_dfi_p3_address[13]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[13])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_15 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[0]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[0]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_16 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[1]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[1]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_17 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[2]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[2])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_18 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_ras_n),
+ .D2(soc_a7ddrphy_dfi_p0_ras_n),
+ .D3(soc_a7ddrphy_dfi_p1_ras_n),
+ .D4(soc_a7ddrphy_dfi_p1_ras_n),
+ .D5(soc_a7ddrphy_dfi_p2_ras_n),
+ .D6(soc_a7ddrphy_dfi_p2_ras_n),
+ .D7(soc_a7ddrphy_dfi_p3_ras_n),
+ .D8(soc_a7ddrphy_dfi_p3_ras_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ras_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_19 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cas_n),
+ .D2(soc_a7ddrphy_dfi_p0_cas_n),
+ .D3(soc_a7ddrphy_dfi_p1_cas_n),
+ .D4(soc_a7ddrphy_dfi_p1_cas_n),
+ .D5(soc_a7ddrphy_dfi_p2_cas_n),
+ .D6(soc_a7ddrphy_dfi_p2_cas_n),
+ .D7(soc_a7ddrphy_dfi_p3_cas_n),
+ .D8(soc_a7ddrphy_dfi_p3_cas_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cas_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_20 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_we_n),
+ .D2(soc_a7ddrphy_dfi_p0_we_n),
+ .D3(soc_a7ddrphy_dfi_p1_we_n),
+ .D4(soc_a7ddrphy_dfi_p1_we_n),
+ .D5(soc_a7ddrphy_dfi_p2_we_n),
+ .D6(soc_a7ddrphy_dfi_p2_we_n),
+ .D7(soc_a7ddrphy_dfi_p3_we_n),
+ .D8(soc_a7ddrphy_dfi_p3_we_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_we_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_21 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cke),
+ .D2(soc_a7ddrphy_dfi_p0_cke),
+ .D3(soc_a7ddrphy_dfi_p1_cke),
+ .D4(soc_a7ddrphy_dfi_p1_cke),
+ .D5(soc_a7ddrphy_dfi_p2_cke),
+ .D6(soc_a7ddrphy_dfi_p2_cke),
+ .D7(soc_a7ddrphy_dfi_p3_cke),
+ .D8(soc_a7ddrphy_dfi_p3_cke),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cke)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_22 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_odt),
+ .D2(soc_a7ddrphy_dfi_p0_odt),
+ .D3(soc_a7ddrphy_dfi_p1_odt),
+ .D4(soc_a7ddrphy_dfi_p1_odt),
+ .D5(soc_a7ddrphy_dfi_p2_odt),
+ .D6(soc_a7ddrphy_dfi_p2_odt),
+ .D7(soc_a7ddrphy_dfi_p3_odt),
+ .D8(soc_a7ddrphy_dfi_p3_odt),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_odt)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_23 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_reset_n),
+ .D2(soc_a7ddrphy_dfi_p0_reset_n),
+ .D3(soc_a7ddrphy_dfi_p1_reset_n),
+ .D4(soc_a7ddrphy_dfi_p1_reset_n),
+ .D5(soc_a7ddrphy_dfi_p2_reset_n),
+ .D6(soc_a7ddrphy_dfi_p2_reset_n),
+ .D7(soc_a7ddrphy_dfi_p3_reset_n),
+ .D8(soc_a7ddrphy_dfi_p3_reset_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_reset_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_24 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cs_n),
+ .D2(soc_a7ddrphy_dfi_p0_cs_n),
+ .D3(soc_a7ddrphy_dfi_p1_cs_n),
+ .D4(soc_a7ddrphy_dfi_p1_cs_n),
+ .D5(soc_a7ddrphy_dfi_p2_cs_n),
+ .D6(soc_a7ddrphy_dfi_p2_cs_n),
+ .D7(soc_a7ddrphy_dfi_p3_cs_n),
+ .D8(soc_a7ddrphy_dfi_p3_cs_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cs_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_25 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_dm[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_26 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_dm[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_27 (
+ .CLK(sys4x_dqs_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+ .TCE(1'd1),
+ .OFB(soc_a7ddrphy0),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay0),
+ .TQ(soc_a7ddrphy_dqs_t0)
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("FIXED"),
+ .IDELAY_VALUE(4'd8),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2 (
+ .IDATAIN(soc_a7ddrphy_dqs_i[0]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
+);
+
+IOBUFDS IOBUFDS(
+ .I(soc_a7ddrphy_dqs_o_no_delay0),
+ .T(soc_a7ddrphy_dqs_t0),
+ .IO(ddram_dqs_p[0]),
+ .IOB(ddram_dqs_n[0]),
+ .O(soc_a7ddrphy_dqs_i[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_28 (
+ .CLK(sys4x_dqs_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+ .TCE(1'd1),
+ .OFB(soc_a7ddrphy1),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay1),
+ .TQ(soc_a7ddrphy_dqs_t1)
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("FIXED"),
+ .IDELAY_VALUE(4'd8),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_1 (
+ .IDATAIN(soc_a7ddrphy_dqs_i[1]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
+);
+
+IOBUFDS IOBUFDS_1(
+ .I(soc_a7ddrphy_dqs_o_no_delay1),
+ .T(soc_a7ddrphy_dqs_t1),
+ .IO(ddram_dqs_p[1]),
+ .IOB(ddram_dqs_n[1]),
+ .O(soc_a7ddrphy_dqs_i[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_29 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay0),
+ .TQ(soc_a7ddrphy_dq_t0)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed0),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data0[7]),
+ .Q2(soc_a7ddrphy_dq_i_data0[6]),
+ .Q3(soc_a7ddrphy_dq_i_data0[5]),
+ .Q4(soc_a7ddrphy_dq_i_data0[4]),
+ .Q5(soc_a7ddrphy_dq_i_data0[3]),
+ .Q6(soc_a7ddrphy_dq_i_data0[2]),
+ .Q7(soc_a7ddrphy_dq_i_data0[1]),
+ .Q8(soc_a7ddrphy_dq_i_data0[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_2 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
+);
+
+IOBUF IOBUF(
+ .I(soc_a7ddrphy_dq_o_nodelay0),
+ .T(soc_a7ddrphy_dq_t0),
+ .IO(ddram_dq[0]),
+ .O(soc_a7ddrphy_dq_i_nodelay0)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_30 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay1),
+ .TQ(soc_a7ddrphy_dq_t1)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_1 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed1),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data1[7]),
+ .Q2(soc_a7ddrphy_dq_i_data1[6]),
+ .Q3(soc_a7ddrphy_dq_i_data1[5]),
+ .Q4(soc_a7ddrphy_dq_i_data1[4]),
+ .Q5(soc_a7ddrphy_dq_i_data1[3]),
+ .Q6(soc_a7ddrphy_dq_i_data1[2]),
+ .Q7(soc_a7ddrphy_dq_i_data1[1]),
+ .Q8(soc_a7ddrphy_dq_i_data1[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_3 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
+);
+
+IOBUF IOBUF_1(
+ .I(soc_a7ddrphy_dq_o_nodelay1),
+ .T(soc_a7ddrphy_dq_t1),
+ .IO(ddram_dq[1]),
+ .O(soc_a7ddrphy_dq_i_nodelay1)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_31 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay2),
+ .TQ(soc_a7ddrphy_dq_t2)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_2 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed2),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data2[7]),
+ .Q2(soc_a7ddrphy_dq_i_data2[6]),
+ .Q3(soc_a7ddrphy_dq_i_data2[5]),
+ .Q4(soc_a7ddrphy_dq_i_data2[4]),
+ .Q5(soc_a7ddrphy_dq_i_data2[3]),
+ .Q6(soc_a7ddrphy_dq_i_data2[2]),
+ .Q7(soc_a7ddrphy_dq_i_data2[1]),
+ .Q8(soc_a7ddrphy_dq_i_data2[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_4 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
+);
+
+IOBUF IOBUF_2(
+ .I(soc_a7ddrphy_dq_o_nodelay2),
+ .T(soc_a7ddrphy_dq_t2),
+ .IO(ddram_dq[2]),
+ .O(soc_a7ddrphy_dq_i_nodelay2)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_32 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay3),
+ .TQ(soc_a7ddrphy_dq_t3)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_3 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed3),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data3[7]),
+ .Q2(soc_a7ddrphy_dq_i_data3[6]),
+ .Q3(soc_a7ddrphy_dq_i_data3[5]),
+ .Q4(soc_a7ddrphy_dq_i_data3[4]),
+ .Q5(soc_a7ddrphy_dq_i_data3[3]),
+ .Q6(soc_a7ddrphy_dq_i_data3[2]),
+ .Q7(soc_a7ddrphy_dq_i_data3[1]),
+ .Q8(soc_a7ddrphy_dq_i_data3[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_5 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
+);
+
+IOBUF IOBUF_3(
+ .I(soc_a7ddrphy_dq_o_nodelay3),
+ .T(soc_a7ddrphy_dq_t3),
+ .IO(ddram_dq[3]),
+ .O(soc_a7ddrphy_dq_i_nodelay3)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_33 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay4),
+ .TQ(soc_a7ddrphy_dq_t4)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_4 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed4),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data4[7]),
+ .Q2(soc_a7ddrphy_dq_i_data4[6]),
+ .Q3(soc_a7ddrphy_dq_i_data4[5]),
+ .Q4(soc_a7ddrphy_dq_i_data4[4]),
+ .Q5(soc_a7ddrphy_dq_i_data4[3]),
+ .Q6(soc_a7ddrphy_dq_i_data4[2]),
+ .Q7(soc_a7ddrphy_dq_i_data4[1]),
+ .Q8(soc_a7ddrphy_dq_i_data4[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_6 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
+);
+
+IOBUF IOBUF_4(
+ .I(soc_a7ddrphy_dq_o_nodelay4),
+ .T(soc_a7ddrphy_dq_t4),
+ .IO(ddram_dq[4]),
+ .O(soc_a7ddrphy_dq_i_nodelay4)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_34 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay5),
+ .TQ(soc_a7ddrphy_dq_t5)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_5 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed5),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data5[7]),
+ .Q2(soc_a7ddrphy_dq_i_data5[6]),
+ .Q3(soc_a7ddrphy_dq_i_data5[5]),
+ .Q4(soc_a7ddrphy_dq_i_data5[4]),
+ .Q5(soc_a7ddrphy_dq_i_data5[3]),
+ .Q6(soc_a7ddrphy_dq_i_data5[2]),
+ .Q7(soc_a7ddrphy_dq_i_data5[1]),
+ .Q8(soc_a7ddrphy_dq_i_data5[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_7 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
+);
+
+IOBUF IOBUF_5(
+ .I(soc_a7ddrphy_dq_o_nodelay5),
+ .T(soc_a7ddrphy_dq_t5),
+ .IO(ddram_dq[5]),
+ .O(soc_a7ddrphy_dq_i_nodelay5)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_35 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay6),
+ .TQ(soc_a7ddrphy_dq_t6)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_6 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed6),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data6[7]),
+ .Q2(soc_a7ddrphy_dq_i_data6[6]),
+ .Q3(soc_a7ddrphy_dq_i_data6[5]),
+ .Q4(soc_a7ddrphy_dq_i_data6[4]),
+ .Q5(soc_a7ddrphy_dq_i_data6[3]),
+ .Q6(soc_a7ddrphy_dq_i_data6[2]),
+ .Q7(soc_a7ddrphy_dq_i_data6[1]),
+ .Q8(soc_a7ddrphy_dq_i_data6[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_8 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
+);
+
+IOBUF IOBUF_6(
+ .I(soc_a7ddrphy_dq_o_nodelay6),
+ .T(soc_a7ddrphy_dq_t6),
+ .IO(ddram_dq[6]),
+ .O(soc_a7ddrphy_dq_i_nodelay6)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_36 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay7),
+ .TQ(soc_a7ddrphy_dq_t7)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_7 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed7),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data7[7]),
+ .Q2(soc_a7ddrphy_dq_i_data7[6]),
+ .Q3(soc_a7ddrphy_dq_i_data7[5]),
+ .Q4(soc_a7ddrphy_dq_i_data7[4]),
+ .Q5(soc_a7ddrphy_dq_i_data7[3]),
+ .Q6(soc_a7ddrphy_dq_i_data7[2]),
+ .Q7(soc_a7ddrphy_dq_i_data7[1]),
+ .Q8(soc_a7ddrphy_dq_i_data7[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_9 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
+);
+
+IOBUF IOBUF_7(
+ .I(soc_a7ddrphy_dq_o_nodelay7),
+ .T(soc_a7ddrphy_dq_t7),
+ .IO(ddram_dq[7]),
+ .O(soc_a7ddrphy_dq_i_nodelay7)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_37 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay8),
+ .TQ(soc_a7ddrphy_dq_t8)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_8 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed8),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data8[7]),
+ .Q2(soc_a7ddrphy_dq_i_data8[6]),
+ .Q3(soc_a7ddrphy_dq_i_data8[5]),
+ .Q4(soc_a7ddrphy_dq_i_data8[4]),
+ .Q5(soc_a7ddrphy_dq_i_data8[3]),
+ .Q6(soc_a7ddrphy_dq_i_data8[2]),
+ .Q7(soc_a7ddrphy_dq_i_data8[1]),
+ .Q8(soc_a7ddrphy_dq_i_data8[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_10 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
+);
+
+IOBUF IOBUF_8(
+ .I(soc_a7ddrphy_dq_o_nodelay8),
+ .T(soc_a7ddrphy_dq_t8),
+ .IO(ddram_dq[8]),
+ .O(soc_a7ddrphy_dq_i_nodelay8)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_38 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay9),
+ .TQ(soc_a7ddrphy_dq_t9)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_9 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed9),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data9[7]),
+ .Q2(soc_a7ddrphy_dq_i_data9[6]),
+ .Q3(soc_a7ddrphy_dq_i_data9[5]),
+ .Q4(soc_a7ddrphy_dq_i_data9[4]),
+ .Q5(soc_a7ddrphy_dq_i_data9[3]),
+ .Q6(soc_a7ddrphy_dq_i_data9[2]),
+ .Q7(soc_a7ddrphy_dq_i_data9[1]),
+ .Q8(soc_a7ddrphy_dq_i_data9[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_11 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
+);
+
+IOBUF IOBUF_9(
+ .I(soc_a7ddrphy_dq_o_nodelay9),
+ .T(soc_a7ddrphy_dq_t9),
+ .IO(ddram_dq[9]),
+ .O(soc_a7ddrphy_dq_i_nodelay9)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_39 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay10),
+ .TQ(soc_a7ddrphy_dq_t10)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_10 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed10),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data10[7]),
+ .Q2(soc_a7ddrphy_dq_i_data10[6]),
+ .Q3(soc_a7ddrphy_dq_i_data10[5]),
+ .Q4(soc_a7ddrphy_dq_i_data10[4]),
+ .Q5(soc_a7ddrphy_dq_i_data10[3]),
+ .Q6(soc_a7ddrphy_dq_i_data10[2]),
+ .Q7(soc_a7ddrphy_dq_i_data10[1]),
+ .Q8(soc_a7ddrphy_dq_i_data10[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_12 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
+);
+
+IOBUF IOBUF_10(
+ .I(soc_a7ddrphy_dq_o_nodelay10),
+ .T(soc_a7ddrphy_dq_t10),
+ .IO(ddram_dq[10]),
+ .O(soc_a7ddrphy_dq_i_nodelay10)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_40 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay11),
+ .TQ(soc_a7ddrphy_dq_t11)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_11 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed11),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data11[7]),
+ .Q2(soc_a7ddrphy_dq_i_data11[6]),
+ .Q3(soc_a7ddrphy_dq_i_data11[5]),
+ .Q4(soc_a7ddrphy_dq_i_data11[4]),
+ .Q5(soc_a7ddrphy_dq_i_data11[3]),
+ .Q6(soc_a7ddrphy_dq_i_data11[2]),
+ .Q7(soc_a7ddrphy_dq_i_data11[1]),
+ .Q8(soc_a7ddrphy_dq_i_data11[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_13 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
+);
+
+IOBUF IOBUF_11(
+ .I(soc_a7ddrphy_dq_o_nodelay11),
+ .T(soc_a7ddrphy_dq_t11),
+ .IO(ddram_dq[11]),
+ .O(soc_a7ddrphy_dq_i_nodelay11)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_41 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay12),
+ .TQ(soc_a7ddrphy_dq_t12)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_12 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed12),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data12[7]),
+ .Q2(soc_a7ddrphy_dq_i_data12[6]),
+ .Q3(soc_a7ddrphy_dq_i_data12[5]),
+ .Q4(soc_a7ddrphy_dq_i_data12[4]),
+ .Q5(soc_a7ddrphy_dq_i_data12[3]),
+ .Q6(soc_a7ddrphy_dq_i_data12[2]),
+ .Q7(soc_a7ddrphy_dq_i_data12[1]),
+ .Q8(soc_a7ddrphy_dq_i_data12[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_14 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
+);
+
+IOBUF IOBUF_12(
+ .I(soc_a7ddrphy_dq_o_nodelay12),
+ .T(soc_a7ddrphy_dq_t12),
+ .IO(ddram_dq[12]),
+ .O(soc_a7ddrphy_dq_i_nodelay12)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_42 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay13),
+ .TQ(soc_a7ddrphy_dq_t13)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_13 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed13),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data13[7]),
+ .Q2(soc_a7ddrphy_dq_i_data13[6]),
+ .Q3(soc_a7ddrphy_dq_i_data13[5]),
+ .Q4(soc_a7ddrphy_dq_i_data13[4]),
+ .Q5(soc_a7ddrphy_dq_i_data13[3]),
+ .Q6(soc_a7ddrphy_dq_i_data13[2]),
+ .Q7(soc_a7ddrphy_dq_i_data13[1]),
+ .Q8(soc_a7ddrphy_dq_i_data13[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_15 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
+);
+
+IOBUF IOBUF_13(
+ .I(soc_a7ddrphy_dq_o_nodelay13),
+ .T(soc_a7ddrphy_dq_t13),
+ .IO(ddram_dq[13]),
+ .O(soc_a7ddrphy_dq_i_nodelay13)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_43 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay14),
+ .TQ(soc_a7ddrphy_dq_t14)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_14 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed14),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data14[7]),
+ .Q2(soc_a7ddrphy_dq_i_data14[6]),
+ .Q3(soc_a7ddrphy_dq_i_data14[5]),
+ .Q4(soc_a7ddrphy_dq_i_data14[4]),
+ .Q5(soc_a7ddrphy_dq_i_data14[3]),
+ .Q6(soc_a7ddrphy_dq_i_data14[2]),
+ .Q7(soc_a7ddrphy_dq_i_data14[1]),
+ .Q8(soc_a7ddrphy_dq_i_data14[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_16 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
+);
+
+IOBUF IOBUF_14(
+ .I(soc_a7ddrphy_dq_o_nodelay14),
+ .T(soc_a7ddrphy_dq_t14),
+ .IO(ddram_dq[14]),
+ .O(soc_a7ddrphy_dq_i_nodelay14)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_44 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay15),
+ .TQ(soc_a7ddrphy_dq_t15)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_15 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed15),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data15[7]),
+ .Q2(soc_a7ddrphy_dq_i_data15[6]),
+ .Q3(soc_a7ddrphy_dq_i_data15[5]),
+ .Q4(soc_a7ddrphy_dq_i_data15[4]),
+ .Q5(soc_a7ddrphy_dq_i_data15[3]),
+ .Q6(soc_a7ddrphy_dq_i_data15[2]),
+ .Q7(soc_a7ddrphy_dq_i_data15[1]),
+ .Q8(soc_a7ddrphy_dq_i_data15[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_17 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
+);
+
+IOBUF IOBUF_15(
+ .I(soc_a7ddrphy_dq_o_nodelay15),
+ .T(soc_a7ddrphy_dq_t15),
+ .IO(ddram_dq[15]),
+ .O(soc_a7ddrphy_dq_i_nodelay15)
+);
+
+reg [23:0] storage_2[0:15];
+reg [23:0] memdat_5;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
+ storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_3[0:15];
+reg [23:0] memdat_6;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
+ storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_4[0:15];
+reg [23:0] memdat_7;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
+ storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_5[0:15];
+reg [23:0] memdat_8;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
+ storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_6[0:15];
+reg [23:0] memdat_9;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
+ storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_7[0:15];
+reg [23:0] memdat_10;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
+ storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_8[0:15];
+reg [23:0] memdat_11;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
+ storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_9[0:15];
+reg [23:0] memdat_12;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
+ storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+
+VexRiscv VexRiscv(
+ .clk(sys_clk),
+ .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack),
+ .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r),
+ .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err),
+ .externalInterruptArray(soc_litedramcore_cpu_interrupt),
+ .externalResetVector(soc_litedramcore_vexriscv),
+ .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack),
+ .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r),
+ .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err),
+ .reset((sys_rst | soc_litedramcore_cpu_reset)),
+ .softwareInterrupt(1'd0),
+ .timerInterrupt(1'd0),
+ .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr),
+ .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte),
+ .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti),
+ .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc),
+ .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w),
+ .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel),
+ .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb),
+ .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we),
+ .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr),
+ .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte),
+ .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti),
+ .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc),
+ .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w),
+ .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel),
+ .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb),
+ .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we)
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(5'd16),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(5'd16),
+ .CLKOUT0_PHASE(1'd0),
+ .CLKOUT1_DIVIDE(3'd4),
+ .CLKOUT1_PHASE(1'd0),
+ .CLKOUT2_DIVIDE(3'd4),
+ .CLKOUT2_PHASE(7'd90),
+ .DIVCLK_DIVIDE(1'd1),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV (
+ .CLKFBIN(vns_pll_fb0),
+ .CLKIN1(soc_s7pll0_clkin),
+ .RST(soc_sys_pll_reset),
+ .CLKFBOUT(vns_pll_fb0),
+ .CLKOUT0(soc_s7pll0_clkout0),
+ .CLKOUT1(soc_s7pll0_clkout1),
+ .CLKOUT2(soc_s7pll0_clkout2),
+ .LOCKED(soc_sys_pll_locked)
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(5'd16),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(4'd8),
+ .CLKOUT0_PHASE(1'd0),
+ .DIVCLK_DIVIDE(1'd1),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV_1 (
+ .CLKFBIN(vns_pll_fb1),
+ .CLKIN1(soc_s7pll1_clkin),
+ .RST(soc_iodelay_pll_reset),
+ .CLKFBOUT(vns_pll_fb1),
+ .CLKOUT0(soc_s7pll1_clkout),
+ .LOCKED(soc_iodelay_pll_locked)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE (
+ .C(sys_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_1 (
+ .C(sys_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(sys_rst)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_2 (
+ .C(sys4x_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_3 (
+ .C(sys4x_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_expr)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_4 (
+ .C(sys4x_dqs_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_5 (
+ .C(sys4x_dqs_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_6 (
+ .C(iodelay_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_7 (
+ .C(iodelay_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(iodelay_rst)
+);
+
+endmodule
--- /dev/null
+vexriscv
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.sim_console.all;
+
+entity litedram_wrapper is
+ generic (
+ DRAM_ABITS : positive;
+ DRAM_ALINES : positive
+ );
+ port(
+ -- LiteDRAM generates the system clock and reset
+ -- from the input clkin
+ clk_in : in std_ulogic;
+ rst : in std_ulogic;
+ system_clk : out std_ulogic;
+ system_reset : out std_ulogic;
+ core_alt_reset : out std_ulogic;
+ pll_locked : out std_ulogic;
+
+ -- Wishbone ports:
+ wb_in : in wishbone_master_out;
+ wb_out : out wishbone_slave_out;
+ wb_is_csr : in std_ulogic;
+ wb_is_init : in std_ulogic;
+
+ -- Init core serial debug
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+
+ -- Misc
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+
+ -- DRAM wires
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic
+ );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+ component litedram_core port (
+ clk : in std_ulogic;
+ rst : in std_ulogic;
+ serial_tx : out std_ulogic;
+ serial_rx : in std_ulogic;
+ pll_locked : out std_ulogic;
+ ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+ ddram_ba : out std_ulogic_vector(2 downto 0);
+ ddram_ras_n : out std_ulogic;
+ ddram_cas_n : out std_ulogic;
+ ddram_we_n : out std_ulogic;
+ ddram_cs_n : out std_ulogic;
+ ddram_dm : out std_ulogic_vector(1 downto 0);
+ ddram_dq : inout std_ulogic_vector(15 downto 0);
+ ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
+ ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
+ ddram_clk_p : out std_ulogic;
+ ddram_clk_n : out std_ulogic;
+ ddram_cke : out std_ulogic;
+ ddram_odt : out std_ulogic;
+ ddram_reset_n : out std_ulogic;
+ init_done : out std_ulogic;
+ init_error : out std_ulogic;
+ user_clk : out std_ulogic;
+ user_rst : out std_ulogic;
+ user_port_native_0_cmd_valid : in std_ulogic;
+ user_port_native_0_cmd_ready : out std_ulogic;
+ user_port_native_0_cmd_we : in std_ulogic;
+ user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ user_port_native_0_wdata_valid : in std_ulogic;
+ user_port_native_0_wdata_ready : out std_ulogic;
+ user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
+ user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
+ user_port_native_0_rdata_valid : out std_ulogic;
+ user_port_native_0_rdata_ready : in std_ulogic;
+ user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
+ );
+ end component;
+
+ signal user_port0_cmd_valid : std_ulogic;
+ signal user_port0_cmd_ready : std_ulogic;
+ signal user_port0_cmd_we : std_ulogic;
+ signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+ signal user_port0_wdata_valid : std_ulogic;
+ signal user_port0_wdata_ready : std_ulogic;
+ signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
+ signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
+ signal user_port0_rdata_valid : std_ulogic;
+ signal user_port0_rdata_ready : std_ulogic;
+ signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
+
+ signal ad3 : std_ulogic;
+
+ signal dram_user_reset : std_ulogic;
+
+ type state_t is (CMD, MWRITE, MREAD);
+ signal state : state_t;
+
+begin
+
+ -- Address bit 3 selects the top or bottom half of the data
+ -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+ --
+ ad3 <= wb_in.adr(3);
+
+ -- DRAM interface signals
+ user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
+ when state = CMD else '0';
+ user_port0_cmd_we <= wb_in.we when state = CMD else '0';
+ user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+ user_port0_rdata_ready <= '1' when state = MREAD else '0';
+ user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
+ user_port0_wdata_data <= wb_in.dat & wb_in.dat;
+ user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
+ "00000000" & wb_in.sel;
+
+ -- Wishbone out signals. CSR and init memory do nothing, just ack
+ wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_wdata_ready when state = MWRITE else
+ user_port0_rdata_valid when state = MREAD else '0';
+ wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
+ user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+ user_port0_rdata_data(63 downto 0);
+ wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+ -- Reset, lift it when init done, no alt core reset
+ system_reset <= dram_user_reset or not init_done;
+ core_alt_reset <= '0';
+
+ -- State machine
+ sm: process(system_clk)
+ begin
+
+ if rising_edge(system_clk) then
+ if dram_user_reset = '1' then
+ state <= CMD;
+ else
+ case state is
+ when CMD =>
+ if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+ state <= MWRITE when wb_in.we = '1' else MREAD;
+ end if;
+ when MWRITE =>
+ if user_port0_wdata_ready = '1' then
+ state <= CMD;
+ end if;
+ when MREAD =>
+ if user_port0_rdata_valid = '1' then
+ state <= CMD;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ litedram: litedram_core
+ port map(
+ clk => clk_in,
+ rst => rst,
+ serial_tx => serial_tx,
+ serial_rx => serial_rx,
+ pll_locked => pll_locked,
+ ddram_a => ddram_a,
+ ddram_ba => ddram_ba,
+ ddram_ras_n => ddram_ras_n,
+ ddram_cas_n => ddram_cas_n,
+ ddram_we_n => ddram_we_n,
+ ddram_cs_n => ddram_cs_n,
+ ddram_dm => ddram_dm,
+ ddram_dq => ddram_dq,
+ ddram_dqs_p => ddram_dqs_p,
+ ddram_dqs_n => ddram_dqs_n,
+ ddram_clk_p => ddram_clk_p,
+ ddram_clk_n => ddram_clk_n,
+ ddram_cke => ddram_cke,
+ ddram_odt => ddram_odt,
+ ddram_reset_n => ddram_reset_n,
+ init_done => init_done,
+ init_error => init_error,
+ user_clk => system_clk,
+ user_rst => dram_user_reset,
+ user_port_native_0_cmd_valid => user_port0_cmd_valid,
+ user_port_native_0_cmd_ready => user_port0_cmd_ready,
+ user_port_native_0_cmd_we => user_port0_cmd_we,
+ user_port_native_0_cmd_addr => user_port0_cmd_addr,
+ user_port_native_0_wdata_valid => user_port0_wdata_valid,
+ user_port_native_0_wdata_ready => user_port0_wdata_ready,
+ user_port_native_0_wdata_we => user_port0_wdata_we,
+ user_port_native_0_wdata_data => user_port0_wdata_data,
+ user_port_native_0_rdata_valid => user_port0_rdata_valid,
+ user_port_native_0_rdata_ready => user_port0_rdata_ready,
+ user_port_native_0_rdata_data => user_port0_rdata_data
+ );
+
+end architecture behaviour;
--- /dev/null
+b00006f
+13
+13
+13
+13
+13
+13
+13
+fe112e23
+fe512c23
+fe612a23
+fe712823
+fea12623
+feb12423
+fec12223
+fed12023
+fce12e23
+fcf12c23
+fd012a23
+fd112823
+fdc12623
+fdd12423
+fde12223
+fdf12023
+fc010113
+94000ef
+3c12083
+3812283
+3412303
+3012383
+2c12503
+2812583
+2412603
+2012683
+1c12703
+1812783
+1412803
+1012883
+c12e03
+812e83
+412f03
+12f83
+4010113
+30200073
+1001117
+f4c10113
+517
+f6850513
+30551073
+1000517
+f3c50513
+1000597
+5bc58593
+b50863
+52023
+450513
+ff5ff06f
+1537
+88050513
+30451073
+6c010ef
+6f
+fc002773
+bc0027f3
+e7f7b3
+17f793
+78463
+1d10306f
+8067
+82002737
+2872783
+2c72503
+879793
+a7e7b3
+3072503
+879793
+a7e7b3
+3472503
+879793
+a7e533
+8067
+cc0027f3
+c79693
+147d713
+c6d693
+793
+d7e463
+8067
+78513
+7005500f
+e787b3
+fedff06f
+13
+fff50513
+fe051ce3
+8067
+100713
+820037b7
+a71533
+80a7aa23
+80e7ac23
+8007aa23
+8067
+100713
+820037b7
+a71533
+80a7aa23
+80e7ae23
+8007aa23
+8067
+793
+400693
+f58633
+64603
+279713
+a70733
+c72023
+178793
+fed794e3
+8067
+793
+400693
+279713
+a70733
+72603
+f58733
+178793
+c70023
+fed794e3
+8067
+f9010113
+6912223
+50493
+4537
+45850513
+5512a23
+6112623
+6812423
+7212023
+5312e23
+5412c23
+5612823
+5712623
+5812423
+5912223
+5a12023
+3b12e23
+7a4030ef
+2010713
+80200637
+3010593
+2a00793
+70a93
+360613
+400513
+693
+17d813
+17f793
+40f007b3
+c7f7b3
+107c7b3
+d70833
+f80023
+168693
+fea690e3
+470713
+fcb71ae3
+82003437
+42623
+42823
+900793
+42a23
+f42223
+100913
+1242423
+f00513
+eb1ff0ef
+a8593
+1840513
+eedff0ef
+2410593
+4c40513
+ee1ff0ef
+2810593
+8040513
+ed5ff0ef
+2c10593
+b440513
+ec9ff0ef
+a042423
+a042623
+a042823
+1700793
+af42023
+b242223
+6042a23
+6042c23
+6042e23
+48513
+e65ff0ef
+3010793
+100d13
+409d0b33
+4a37
+40978bb3
+913
+438a0a13
+1678c33
+3b8b93
+820037b7
+2500713
+6e7a623
+7a7a823
+f00513
+e19ff0ef
+16a89b3
+413
+100c93
+8a07b3
+7a503
+1c10593
+e6dff0ef
+9c703
+fecc4783
+f71863
+29c703
+fecbc783
+f70463
+c93
+440413
+1000793
+498993
+fcf414e3
+190413
+20c9063
+2000793
+f40a63
+48513
+de5ff0ef
+40913
+f85ff06f
+2000913
+48513
+dd1ff0ef
+3010793
+82003cb7
+40978bb3
+190413
+70c8d13
+100d93
+3b8b93
+2500793
+6fca623
+1bd2023
+f00513
+d75ff0ef
+993
+100793
+13a0733
+72503
+1c10593
+f12623
+dc9ff0ef
+13b0733
+ea8733
+74603
+fecc4703
+c12783
+1000693
+e61c63
+40998733
+ea8733
+374603
+fecbc703
+e60463
+793
+498993
+fad99ae3
+78e63
+140413
+1f00793
+87c863
+48513
+d31ff0ef
+f7dff06f
+8909b3
+2000793
+4019d993
+8f91263
+4537
+46450513
+564030ef
+48513
+cedff0ef
+413
+9344663
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+cadff0ef
+6c12083
+6812403
+6412483
+6012903
+5c12983
+5812a03
+5412a83
+5012b03
+4c12b83
+4812c03
+4412c83
+4012d03
+3c12d83
+7010113
+8067
+41240433
+1f45613
+860633
+4537
+40165613
+98593
+46850513
+4d0030ef
+f6dff06f
+48513
+c71ff0ef
+140413
+f69ff06f
+820037b7
+e00713
+4537
+e7a023
+47450513
+4a40306f
+820037b7
+100713
+4537
+e7a023
+49850513
+48c0306f
+2051663
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+be1ff06f
+1051713
+1075713
+820037b7
+875713
+1051513
+e7a623
+1055513
+a7a823
+7aa23
+900713
+fc5ff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+1412c23
+1512a23
+1612823
+8054663
+100493
+40a484b3
+200993
+4437
+43840413
+1040a13
+4ab7
+300b13
+42503
+c10593
+48913
+bcdff0ef
+c10793
+12787b3
+7c583
+4bca8513
+1390933
+3c4030ef
+ff2b54e3
+440413
+fc8a18e3
+5537
+96c50513
+3ac030ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+1812a03
+1412a83
+1012b03
+3010113
+8067
+100993
+493
+f7dff06f
+1051713
+fe010113
+1075713
+112e23
+b12623
+820037b7
+875713
+1051513
+6e7aa23
+1055513
+6a7ac23
+607ae23
+2500713
+6e7a623
+100713
+f00513
+6e7a823
+ab1ff0ef
+c12583
+1c12083
+58513
+2010113
+eedff06f
+f8010113
+6912a23
+3010493
+7412423
+6112e23
+6812c23
+7212823
+7312623
+7512223
+7612023
+5712e23
+5812c23
+5912a23
+5a12823
+5b12623
+a12423
+4010a13
+48793
+78023
+780a3
+78123
+781a3
+478793
+ff4796e3
+82003437
+49b7
+913
+6c40a93
+2500c13
+2500c93
+100b13
+43898993
+6042a23
+7242c23
+6042e23
+19aa023
+f00513
+7642823
+a01ff0ef
+2010593
+2840513
+a65ff0ef
+2410593
+5c40513
+a59ff0ef
+2810593
+9040513
+a4dff0ef
+2c10593
+c440513
+a41ff0ef
+b93
+400d13
+1000d93
+812783
+cfbc663
+890913
+8000793
+f8f91ce3
+4937
+400993
+413
+8487b3
+7c583
+4bc90513
+140413
+210030ef
+ff3416e3
+448493
+ff4490e3
+5437
+96c40513
+1f8030ef
+400913
+44b7
+100593
+4c448513
+1e4030ef
+593
+4c448513
+1d8030ef
+100593
+4c448513
+1cc030ef
+593
+4c448513
+fff90913
+1bc030ef
+fc0916e3
+96c40513
+1b0030ef
+7c12083
+7812403
+7412483
+7012903
+6c12983
+6812a03
+6412a83
+6012b03
+5c12b83
+5812c03
+5412c83
+5012d03
+4c12d83
+8010113
+8067
+18aa023
+7642823
+f00513
+8e5ff0ef
+793
+f98733
+72503
+1c10593
+f12623
+93dff0ef
+c12783
+2010713
+693
+9785b3
+f70633
+1c10713
+d70733
+74503
+64703
+5c883
+a60023
+e54733
+1176733
+e58023
+168693
+158593
+160613
+fda698e3
+478793
+fbb790e3
+1b8b93
+eb5ff06f
+fd010113
+2912223
+44b7
+2812423
+3212023
+1312e23
+2112623
+50913
+44848493
+413
+4000993
+140793
+f106a3
+4a503
+240793
+810623
+f10723
+340793
+1040413
+c10593
+ff47413
+f107a3
+448493
+85dff0ef
+fd3416e3
+1091713
+1075713
+820037b7
+875713
+1091913
+ae7a423
+1095913
+b27a623
+a07a823
+1700713
+2c12083
+2812403
+ae7a023
+100713
+ae7a223
+2412483
+2012903
+1c12983
+3010113
+8067
+ff010113
+400007b7
+aaaab737
+112623
+812423
+912223
+1212023
+aaa70713
+20078693
+e7a023
+478793
+fed79ce3
+f60ff0ef
+44030ef
+400007b7
+aaaab737
+413
+aaa70713
+20078693
+7a603
+e60463
+140413
+478793
+fed798e3
+400007b7
+55555737
+55570713
+20078693
+e7a023
+478793
+fed79ce3
+f14ff0ef
+7f9020ef
+400007b7
+55555737
+55570713
+20078693
+7a603
+e60463
+140413
+478793
+fed798e3
+40c63
+4537
+10000613
+40593
+4c850513
+781020ef
+802006b7
+40000737
+100793
+368693
+40200637
+17d593
+17f793
+40f007b3
+d7f7b3
+b7c7b3
+f72023
+470713
+fec712e3
+e9cff0ef
+781020ef
+802006b7
+40000737
+493
+100793
+368693
+40200637
+17d593
+17f793
+40f007b3
+d7f7b3
+b7c7b3
+72583
+f58463
+148493
+470713
+fcc71ee3
+48c63
+4537
+80637
+48593
+4ec50513
+6ed020ef
+400006b7
+793
+868693
+2637
+279713
+d70733
+f72023
+178793
+fec798e3
+e18ff0ef
+6fd020ef
+40000737
+106b7
+593
+793
+870713
+fff68693
+2537
+279613
+e60633
+62603
+d67633
+f60463
+158593
+178793
+fea792e3
+2058a63
+4537
+2637
+51050513
+671020ef
+593
+c12083
+812403
+412483
+12903
+58513
+1010113
+8067
+940433
+fe0410e3
+4537
+53450513
+63d020ef
+820027b7
+207a023
+7a823
+7aa23
+7ac23
+7ae23
+ff00713
+e7a023
+10737
+fff70713
+e7a223
+1000737
+fff70713
+e7a423
+fff00713
+e7a623
+100713
+2e7a023
+2e7a223
+d10ff0ef
+50913
+400006b7
+80737
+241793
+d787b3
+87a023
+140413
+fee418e3
+82002437
+100493
+2942223
+ce0ff0ef
+40a905b3
+64000537
+5f8030ef
+50913
+cfcff0ef
+5e1020ef
+2942023
+2942223
+cbcff0ef
+50413
+400007b7
+40200737
+7a683
+478793
+fee79ce3
+820027b7
+100713
+2e7a223
+c94ff0ef
+40a405b3
+64000537
+5ac030ef
+50613
+4537
+90593
+54050513
+551020ef
+100593
+ee1ff06f
+f9010113
+6112623
+6812423
+6912223
+5312e23
+5812423
+7212023
+5412c23
+5512a23
+5612823
+5712623
+5912223
+5a12023
+3b12e23
+855ff0ef
+82003437
+100493
+513
+c8cff0ef
+80942a23
+82942023
+80042a23
+100513
+c78ff0ef
+200793
+80f42a23
+82942023
+4537
+80042a23
+56850513
+4cd020ef
+47b7
+43878793
+1c10993
+413
+f12223
+5c37
+802007b7
+100913
+378793
+891933
+a93
+b93
+493
+f12023
+2c0006f
+48a93
+a0b93
+700793
+1ef48863
+820037b7
+8127aa23
+100713
+82e7a223
+8007aa23
+148493
+3010613
+2010693
+2a00793
+400593
+713
+12803
+17d513
+17f793
+40f007b3
+107f7b3
+a7c7b3
+e68533
+f50023
+170713
+fcb71ee3
+468693
+fcd618e3
+82003a37
+a2623
+a2823
+900793
+a2a23
+fa2223
+100b13
+16a2423
+f00513
+b7cff0ef
+18a0513
+2010593
+bb8ff0ef
+4ca0513
+2410593
+bacff0ef
+80a0513
+2810593
+ba0ff0ef
+b4a0513
+2c10593
+b94ff0ef
+a0a2423
+a0a2623
+a0a2823
+1700793
+afa2023
+b6a2223
+60a2a23
+60a2c23
+47b7
+60a2e23
+48613
+40593
+57878513
+395020ef
+40513
+b1cff0ef
+2000b13
+a13
+82003cb7
+100d93
+2500793
+6fca623
+820037b7
+7b7a823
+f00513
+ae4ff0ef
+2110793
+408786b3
+713
+100d13
+412783
+1c10593
+d12623
+e78633
+62503
+e12423
+b28ff0ef
+c12683
+19c603
+812703
+6c583
+1000813
+c59863
+26c583
+39c603
+c58463
+d13
+470713
+468693
+fb071ae3
+47b7
+d0593
+58478513
+2f5020ef
+40513
+fffb0b13
+1aa0a33
+a90ff0ef
+f60b14e3
+4537
+58850513
+2d5020ef
+820037b7
+7a623
+7a823
+7aa23
+b00713
+e7a223
+100713
+e7a423
+f00513
+a2cff0ef
+40513
+abcff0ef
+96cc0513
+29d020ef
+e14bc6e3
+e11ff06f
+4537
+a8613
+40593
+58c50513
+281020ef
+820037b7
+8127aa23
+100713
+82e7a023
+8007aa23
+82003737
+793
+100693
+3579263
+40513
+a6cff0ef
+96cc0513
+24d020ef
+fff98993
+2041063
+100413
+d8dff06f
+81272a23
+82d72223
+80072a23
+178793
+fcdff06f
+6c12083
+6812403
+6412483
+6012903
+5c12983
+5812a03
+5412a83
+5012b03
+4c12b83
+4812c03
+4412c83
+4012d03
+3c12d83
+100513
+7010113
+8067
+fe010113
+4537
+1212823
+59c50513
+82004937
+112e23
+812c23
+912a23
+1312623
+1c1020ef
+80092023
+82003437
+80092223
+42623
+42823
+c00793
+42a23
+c537
+f42023
+35050513
+914ff0ef
+42623
+42823
+e00793
+42a23
+2537
+f42023
+71050513
+8f4ff0ef
+200793
+f42623
+20000713
+e42823
+f42a23
+f00793
+f42223
+100493
+942423
+42623
+42823
+300993
+1342a23
+f42223
+942423
+42623
+600713
+e42823
+942a23
+f42223
+942423
+900713
+e42623
+1737
+92070713
+e42823
+42a23
+f42223
+c800513
+942423
+878ff0ef
+400793
+f42623
+40000793
+f42823
+42a23
+1342223
+c800513
+942423
+854ff0ef
+b8dff0ef
+c2cff0ef
+88dff0ef
+80992023
+2051263
+80992223
+1c12083
+1812403
+1412483
+1012903
+c12983
+2010113
+8067
+100513
+fe1ff06f
+f7010113
+8112623
+8812423
+8912223
+9212023
+7312e23
+793
+bc079073
+30046073
+5437
+315020ef
+96c40513
+65020ef
+4537
+5b450513
+59020ef
+4537
+5dc50513
+4d020ef
+4537
+60450513
+41020ef
+4537
+62850513
+35020ef
+4537
+64c50513
+29020ef
+96c40513
+21020ef
+4537
+67850513
+15020ef
+4537
+6a050513
+9020ef
+96c40513
+1020ef
+4537
+6c450513
+7f4020ef
+684000ef
+96c40513
+7e8020ef
+4537
+6ec50513
+7dc020ef
+4537
+70850513
+7d0020ef
+96c40513
+7c8020ef
+4537
+72450513
+7bc020ef
+45b7
+4537
+6400613
+75858593
+76450513
+7a4020ef
+4537
+1800593
+78450513
+794020ef
+4537
+400593
+7a050513
+784020ef
+4537
+593
+7bc50513
+774020ef
+4537
+45b7
+7d850513
+764020ef
+96c40513
+75c020ef
+4537
+7f450513
+750020ef
+d69ff0ef
+100793
+50493
+f50863
+5537
+82850513
+734020ef
+96c40513
+72c020ef
+2048663
+5537
+84850513
+71c020ef
+a0000ef
+50863
+5537
+87c50513
+708020ef
+96c40513
+700020ef
+5537
+89450513
+6f4020ef
+1a8010ef
+5937
+54b7
+8c890593
+8dc48513
+6dc020ef
+59b7
+4000593
+3010513
+1c4010ef
+3014783
+2078c63
+96c40513
+6bc020ef
+1010613
+c10593
+3010513
+5b4000ef
+50593
+c12503
+1010613
+638000ef
+51663
+8e098513
+690020ef
+8c890593
+8dc48513
+684020ef
+fadff06f
+68067
+5537
+ec010113
+92c50513
+12112e23
+12812c23
+12912a23
+13212823
+13312623
+13412423
+13512223
+13612023
+11712e23
+11812c23
+644020ef
+5537
+5437
+94450513
+90c40493
+630020ef
+90c40413
+4c503
+8051e63
+820027b7
+207a023
+7a823
+7aa23
+7ac23
+7ae23
+100713
+e7a023
+17d00693
+d7a223
+186b7
+d7868693
+d7a423
+17d86b7
+84068693
+d7a623
+2e7a023
+2e7a223
+b13
+82002ab7
+5100493
+1b00913
+e00993
+100a13
+28aa783
+2caa703
+879793
+e7e7b3
+30aa703
+879793
+e7e7b3
+34aa703
+879793
+e7e7b3
+79e63
+5537
+9f450513
+e00006f
+7b4020ef
+148493
+f59ff06f
+78c020ef
+c050e63
+730020ef
+28950863
+29250663
+16407b3
+107c783
+aa79e63
+1b0b13
+b3b1e63
+54b7
+a93
+300993
+100913
+500413
+8f448493
+82000a37
+6f4020ef
+a10623
+6ec020ef
+a106a3
+6e4020ef
+a10723
+c10b93
+6d8020ef
+a107a3
+b8c13
+b13
+c14583
+1c0c13
+6bb4863
+f14783
+f378063
+e14783
+d14703
+158593
+879793
+e7e7b3
+879b13
+87d793
+fb67b3
+1079b13
+f10513
+10b5b13
+140020ef
+5650c63
+6d4020ef
+2051e63
+1a8a93
+28a9e63
+5537
+97050513
+4ac020ef
+580006f
+f8650513
+153b13
+34aa223
+ed9ff06f
+650020ef
+ac01a3
+1b0b13
+f7dff06f
+640020ef
+fbdff06f
+4300513
+6a4020ef
+f3dff06f
+f14783
+16f46e63
+279793
+9787b3
+7a783
+78067
+4b00513
+680020ef
+100513
+13c12083
+13812403
+13412483
+13012903
+12c12983
+12812a03
+12412a83
+12012b03
+11c12b83
+11812c03
+14010113
+8067
+1014783
+1114703
+1879793
+1071713
+e7e7b3
+1314703
+e7e7b3
+1214703
+871713
+e7e7b3
+ffc78793
+400713
+c14683
+e78633
+1b8b93
+d74c63
+f14783
+a93
+4b00513
+e9279ce3
+f55ff06f
+7bc683
+170713
+d60023
+fd1ff06f
+1014403
+1114783
+4b00513
+1841413
+1079793
+f46433
+1314783
+f46433
+1214783
+879793
+f46433
+5b8020ef
+5537
+40593
+99850513
+37c020ef
+5537
+9c050513
+370020ef
+65c020ef
+793
+bc079073
+30047073
+100f
+13
+13
+13
+13
+13
+cc0027f3
+c79693
+147d713
+c6d693
+793
+2d7e063
+368020ef
+40693
+613
+593
+513
+c9dff0ef
+6f
+78513
+7005500f
+e787b3
+fd5ff06f
+4b00513
+528020ef
+12a2023
+dbdff06f
+1a8a93
+e28a8ce3
+5500513
+e6dff06f
+5537
+a0050513
+2d8020ef
+513
+e85ff06f
+fd010113
+3212023
+50913
+5537
+a0c50513
+2912223
+1412c23
+1512a23
+1612823
+1712623
+1812423
+2112623
+2812423
+1312e23
+1912223
+58493
+60a13
+5b37
+204020ef
+5ab7
+5bb7
+5c37
+4904063
+2812403
+2c12083
+2412483
+2012903
+1c12983
+1812a03
+1412a83
+1012b03
+c12b83
+812c03
+412c83
+5537
+96c50513
+3010113
+2380206f
+1000793
+48413
+97d463
+1000413
+5537
+a0593
+a1c50513
+218020ef
+993
+5cb7
+13907b3
+7c583
+a28c8513
+198993
+1fc020ef
+ff3416e3
+40993
+1000c93
+5999a63
+a24a8513
+1e4020ef
+993
+5e00c93
+13907b3
+7c583
+fe058793
+ff7f793
+4fcf063
+a34c0513
+1c0020ef
+198993
+ff3410e3
+40993
+1000c93
+3999863
+890933
+408484b3
+8a0a33
+f29ff06f
+a30b0513
+194020ef
+198993
+fa1ff06f
+a38b8513
+184020ef
+fc5ff06f
+a24a8513
+178020ef
+198993
+fc5ff06f
+ff010113
+65b7
+812423
+793
+ae05a403
+ae058593
+40f585b3
+513
+112623
+60d010ef
+2a41063
+40593
+812403
+c12083
+5537
+a3c50513
+1010113
+1280206f
+50613
+5537
+40593
+a5850513
+114020ef
+812403
+c12083
+5537
+a8450513
+1010113
+fc0206f
+60793
+2060713
+7a023
+478793
+fef71ce3
+a5a023
+2000713
+54783
+4e78e63
+79663
+513
+8067
+150513
+fe9ff06f
+178793
+2c0006f
+78023
+68513
+178793
+7c683
+fee68ce3
+2068e63
+150693
+251513
+a60533
+f52023
+7c583
+fce58ae3
+fc0594e3
+68513
+8067
+150793
+50023
+2000713
+513
+fc1ff06f
+8067
+fd010113
+2812423
+2912223
+6437
+64b7
+3212023
+1312e23
+2112623
+50913
+58993
+94840413
+99848493
+941663
+513
+380006f
+42783
+90513
+c12623
+47a583
+2c8010ef
+c12603
+2051c63
+42783
+98513
+60593
+7a783
+780e7
+42503
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+440413
+fa1ff06f
+cc0027f3
+c79693
+147d713
+c6d693
+793
+d7e463
+8067
+78513
+7005500f
+e787b3
+fedff06f
+820007b7
+100713
+e7a023
+8067
+fe010113
+5537
+1212823
+1312623
+ab850513
+6937
+49b7
+912a23
+1412423
+1512223
+1612023
+112e23
+812c23
+493
+69d010ef
+6a37
+99890913
+5ab7
+46498993
+5b37
+713
+948a0413
+300006f
+42783
+c7a683
+2969063
+87a603
+47a583
+61463
+98613
+adca8513
+719010ef
+100713
+440413
+fd241ae3
+70663
+96cb0513
+701010ef
+148493
+a00793
+faf498e3
+1c12083
+1812403
+1412483
+1012903
+c12983
+812a03
+412a83
+12b03
+2010113
+8067
+ef010113
+10513
+10112623
+7a1010ef
+14783
+10593
+79663
+45b7
+46458593
+5537
+ae850513
+69d010ef
+10c12083
+11010113
+8067
+fe010113
+112e23
+812c23
+912a23
+100793
+2a7c263
+5537
+af450513
+66d010ef
+1c12083
+1812403
+1412483
+2010113
+8067
+58413
+42503
+613
+c10593
+410010ef
+c12783
+50493
+7c783
+78863
+5537
+b0c50513
+fbdff06f
+442503
+c10593
+613
+3e4010ef
+c12783
+50593
+7c783
+78863
+5537
+b2050513
+f91ff06f
+48513
+2b9010ef
+50593
+5537
+b3450513
+5e5010ef
+f79ff06f
+fd010113
+2812423
+2112623
+58413
+a04c63
+513
+93dfe0ef
+5537
+c2850513
+5b9010ef
+42503
+613
+1c10593
+374010ef
+1c12783
+7c783
+2078063
+5537
+c3450513
+591010ef
+2c12083
+2812403
+3010113
+8067
+a12623
+8f1fe0ef
+c12583
+5537
+c4450513
+569010ef
+fd9ff06f
+fff00513
+92dfe06f
+fe010113
+112e23
+812c23
+912a23
+1212823
+2a04463
+5537
+c5850513
+539010ef
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+58413
+50493
+42503
+613
+c10593
+2d4010ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb5ff06f
+100793
+2f48863
+442503
+c10593
+613
+2a0010ef
+c12783
+50593
+7c783
+78a63
+5537
+c6850513
+f81ff06f
+fff00593
+90513
+939fe0ef
+f75ff06f
+fe010113
+112e23
+a04e63
+5537
+c7850513
+491010ef
+1c12083
+2010113
+8067
+58793
+7a503
+613
+c10593
+23c010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+fc9ff06f
+93dfe0ef
+fc5ff06f
+fe010113
+112e23
+a04e63
+5537
+c9c50513
+439010ef
+1c12083
+2010113
+8067
+58793
+7a503
+613
+c10593
+1e4010ef
+c12783
+7c783
+78863
+5537
+b0c50513
+fc9ff06f
+b0dfe0ef
+fc5ff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+100793
+2a7c663
+5537
+dfc50513
+3cd010ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+58413
+50493
+42503
+613
+c10593
+164010ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb1ff06f
+442503
+613
+c10593
+138010ef
+c12783
+50993
+7c783
+78863
+5537
+e1c50513
+f85ff06f
+200793
+100513
+2f48663
+842503
+613
+c10593
+100010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+f51ff06f
+793
+279713
+1270733
+f4f502e3
+1372023
+178793
+fedff06f
+fd010113
+2112623
+2812423
+2912223
+3212023
+1312e23
+100793
+2a7c663
+5537
+e2c50513
+2d5010ef
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+58413
+50493
+42503
+613
+c10593
+6c010ef
+c12783
+50993
+7c783
+78863
+5537
+e4450513
+fb1ff06f
+442503
+613
+c10593
+40010ef
+c12783
+50913
+7c783
+78863
+5537
+e6450513
+f85ff06f
+200793
+100513
+2f48663
+842503
+613
+c10593
+8010ef
+c12783
+7c783
+78863
+5537
+c8c50513
+f51ff06f
+793
+279713
+e986b3
+e90733
+f4f500e3
+72703
+178793
+e6a023
+fe5ff06f
+fe010113
+112e23
+812c23
+912a23
+1212823
+2a04463
+5537
+e8050513
+1dd010ef
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+58413
+50493
+42503
+613
+c10593
+779000ef
+c12783
+50913
+7c783
+78863
+5537
+b0c50513
+fb5ff06f
+100793
+2f48863
+442503
+c10593
+613
+745000ef
+c12783
+50593
+7c783
+78a63
+5537
+e9850513
+f81ff06f
+400593
+90613
+90513
+e80ff0ef
+f71ff06f
+fb010113
+10007b7
+4812423
+3f878413
+5212023
+3312e23
+3412c23
+3512a23
+4112623
+4912223
+3612823
+3712623
+3812423
+3912223
+3a12023
+1b12e23
+50a93
+58a13
+28040993
+3f878713
+3f878913
+70023
+4070713
+ff371ce3
+64b7
+6b37
+94848493
+998b0b13
+a00b93
+7649663
+a8513
+455000ef
+57b7
+9bc78793
+fa2023
+40793
+7c703
+1e071063
+4078793
+ff379ae3
+513
+4c12083
+4812403
+4412483
+4012903
+3c12983
+3812a03
+3412a83
+3012b03
+2c12b83
+2812c03
+2412c83
+2012d03
+1c12d83
+5010113
+8067
+4a783
+a8513
+47a583
+b12623
+3e1000ef
+c12583
+50613
+a8513
+321000ef
+2051463
+40793
+7c703
+2071263
+4a783
+651513
+4000613
+47a583
+a90533
+2a5000ef
+448493
+f45ff06f
+150513
+4078793
+fd7518e3
+fedff06f
+178793
+4070713
+14d79063
+793
+1480006f
+40793
+713
+7c683
+68463
+170713
+4078793
+ff3798e3
+100793
+1000bb7
+513
+af70c63
+a091a63
+4ba503
+a050663
+5cb7
+96cc8513
+7ac010ef
+40b13
+a93
+b4783
+78c63
+b0513
+321000ef
+450513
+aad463
+50a93
+40b0b13
+ff3b10e3
+60a8463
+1a8593
+5000513
+74020ef
+50c13
+a00b13
+5d37
+5db7
+44783
+2078263
+1b0b13
+c0593
+b0513
+90020ef
+4051c63
+40593
+ae4d8513
+738010ef
+4040413
+fd341ae3
+c0593
+b0513
+6c020ef
+50663
+96cc8513
+718010ef
+ba223
+100513
+1248933
+90023
+9a2023
+4c783
+2079263
+100793
+fba223
+e51ff06f
+40613
+a8593
+ef4d0513
+6e0010ef
+fa9ff06f
+ba223
+e35ff06f
+10004b7
+3a048c23
+40713
+793
+3b848493
+a00693
+74603
+ea060ae3
+679793
+f907b3
+913
+a78733
+74683
+ea0688e3
+40713
+74603
+60a63
+a70633
+64603
+60863
+e8d61ae3
+4070713
+ff3712e3
+1248733
+d70023
+150513
+190913
+fc1ff06f
+fe010113
+812c23
+912a23
+1212823
+112e23
+50913
+60493
+6a403
+59663
+62603
+a861e63
+fff78793
+287f063
+1812403
+1c12083
+1412483
+1012903
+700513
+2010113
+4700106f
+140413
+86a023
+8058663
+4a583
+100793
+40b40433
+287f063
+158513
+a70533
+b705b3
+fff40613
+e12623
+2a1000ef
+c12703
+4a783
+5537
+40593
+f707b3
+1278023
+4a603
+f8c50513
+c70633
+5b8010ef
+4a783
+178793
+f4a023
+fff40413
+41e63
+1c12083
+1812403
+1412483
+1012903
+2010113
+8067
+800513
+3e0010ef
+fd9ff06f
+4a783
+5537
+100593
+f707b3
+1278023
+4a603
+f8c50513
+c70633
+55c010ef
+4a783
+178793
+f4a023
+fadff06f
+10007b7
+7aa23
+10007b7
+fff00713
+7a823
+10007b7
+e7a623
+10007b7
+7a423
+10007b7
+3878793
+28078713
+78023
+4078793
+fee79ce3
+8067
+fb010113
+3312e23
+3412c23
+3512a23
+3712623
+59b7
+5bb7
+5ab7
+1000a37
+4812423
+5212023
+3612823
+3812423
+4112623
+4912223
+3912223
+3a12023
+50413
+58b13
+12623
+12823
+100913
+fe498993
+efcb8c13
+9bca8a93
+38a0a13
+358010ef
+1b00793
+50713
+4f51863
+348010ef
+a10c23
+340010ef
+a10ca3
+a98533
+54783
+200493
+47f793
+a078463
+7e00d13
+500c93
+31c010ef
+1810793
+9787b3
+a78023
+148493
+9a50463
+ff9494e3
+fff00713
+ff77513
+a00793
+5af50063
+d00793
+58f50c63
+ff77793
+b00693
+38d78463
+12f6c663
+400693
+30d78863
+8f6cc63
+200693
+2ed78463
+26f6cc63
+100693
+26d78263
+1871713
+41875713
+f4074ce3
+f987b3
+7c783
+977f793
+f40784e3
+b0793
+40713
+1010693
+c10613
+90593
+d71ff0ef
+f2dff06f
+2010793
+9784b3
+fe048c23
+efcb8c93
+493
+1200d13
+ca583
+1810513
+658000ef
+51a63
+349493
+9c04b3
+44c703
+f51ff06f
+148493
+8c8c93
+fda49ce3
+f3dff06f
+600693
+22d78663
+32d7c063
+800693
+10d78063
+900693
+f6d794e3
+1012783
+1410593
+40513
+f407b3
+78023
+c12783
+f407b3
+7c483
+78023
+9fdff0ef
+c12783
+f407b3
+978023
+12051c63
+493
+1412783
+9787b3
+7c503
+e6050ee3
+b0793
+40713
+1010693
+c10613
+90593
+148493
+ca1ff0ef
+fd5ff06f
+1800693
+2ed78063
+6f6c663
+f00693
+2ad78c63
+1000693
+d78663
+e00693
+ecd79ce3
+10007b7
+1000693
+c7a703
+36d51a63
+2074a63
+fff70693
+d7a623
+fff00613
+c69863
+10006b7
+146a683
+d7a623
+10006b7
+c7a583
+106a683
+32d59263
+e7a623
+700513
+e8010ef
+de9ff06f
+8500693
+22d78463
+6f6ca63
+7f00693
+e6d79ae3
+c12583
+dc0586e3
+1012483
+fff58513
+a12623
+40b484b3
+48613
+b405b3
+a40533
+70c000ef
+800513
+a0010ef
+c12603
+5537
+48593
+c40633
+f8c50513
+22c010ef
+2000513
+80010ef
+fff00c93
+800513
+fff48493
+70010ef
+ff949ae3
+1600006f
+8900693
+22d78c63
+ff00693
+f89ff06f
+55b7
+5537
+40613
+8c858593
+f9450513
+1e4010ef
+ea048ae3
+493
+100006f
+800513
+2c010ef
+148493
+1012783
+c12703
+40e787b3
+fef4e4e3
+e8dff06f
+800513
+c010ef
+c12783
+fff78793
+f12623
+c12783
+fe0794e3
+cf9ff06f
+40023
+fff00913
+4c12083
+4812403
+90513
+4412483
+4012903
+3c12983
+3812a03
+3412a83
+3012b03
+2c12b83
+2812c03
+2412c83
+2012d03
+5010113
+8067
+c12783
+1012703
+cae7f4e3
+f407b3
+7c503
+799000ef
+c12783
+178793
+f12623
+c8dff06f
+c12783
+c80782e3
+800513
+779000ef
+c12783
+fff78793
+fe1ff06f
+c12503
+1012483
+c69572e3
+fff48493
+40a484b3
+2048863
+150593
+48613
+b405b3
+a40533
+5a4000ef
+c12603
+5537
+48593
+c40633
+f8c50513
+cc010ef
+2000513
+721000ef
+fff00c93
+800513
+fff48493
+711000ef
+ff949ae3
+1012783
+fff78793
+240006f
+c12483
+1012783
+bef4fce3
+1012783
+48c93
+f4ea63
+c12783
+197ee63
+f12823
+bddff06f
+2000513
+6d1000ef
+148493
+fd9ff06f
+800513
+6c1000ef
+fffc8c93
+fd5ff06f
+c12783
+1012583
+bab7f8e3
+f40633
+40f585b3
+5537
+f8c50513
+3c010ef
+1012783
+f05ff06f
+194913
+b8dff06f
+800513
+681000ef
+c12783
+fff78793
+f12623
+c12783
+fe0794e3
+1012783
+b60784e3
+493
+100006f
+2000513
+655000ef
+148493
+1012783
+48c93
+fef4e6e3
+c12783
+f797f0e3
+800513
+635000ef
+fffc8c93
+fedff06f
+c12503
+1012483
+b29572e3
+40a484b3
+150593
+48613
+b405b3
+a40533
+46c000ef
+c12603
+5537
+fff48593
+c40633
+f8c50513
+795000ef
+2000513
+5e9000ef
+800513
+fff48493
+5dd000ef
+fe049ae3
+ecdff06f
+659593
+ba0cb3
+c12783
+4079a63
+1012783
+8078463
+493
+680006f
+cc0742e3
+10006b7
+106a683
+cae68ce3
+1000637
+1462603
+170713
+e7a623
+e65463
+7a623
+c7a783
+a8c93
+faf68ce3
+679793
+fa0cb3
+fadff06f
+800513
+56d000ef
+c12783
+fff78793
+f12623
+f95ff06f
+2000513
+555000ef
+148493
+1012783
+48d13
+fef4e6e3
+c12783
+3a7ea63
+f12823
+c8593
+40513
+13c000ef
+40513
+254000ef
+c12583
+a12823
+a0a5fee3
+b40633
+40b505b3
+e6dff06f
+800513
+505000ef
+fffd0d13
+fbdff06f
+1012903
+10004b7
+12407b3
+78023
+44783
+6078063
+2100713
+4e78c63
+104a783
+1000537
+3850513
+679793
+f50533
+40593
+d0000ef
+104a783
+900713
+178793
+2f74e63
+f4a823
+10007b7
+104a703
+147a683
+e6d463
+e7aa23
+1000737
+872783
+178793
+f72423
+104a703
+10007b7
+e7a623
+c91ff06f
+4a823
+fc9ff06f
+ff5f593
+54783
+b79463
+8067
+78663
+150513
+fedff06f
+513
+8067
+54703
+2071263
+513
+8067
+fee68ee3
+178793
+7c683
+fe069ae3
+150513
+fddff06f
+58793
+fedff06f
+b505b3
+ff67613
+b50663
+54783
+79663
+513
+8067
+fef60ee3
+150513
+fe5ff06f
+50793
+158593
+fff5c703
+178793
+fee78fa3
+fe0718e3
+8067
+c50633
+50793
+c79463
+8067
+5c703
+e78023
+70463
+158593
+178793
+fe5ff06f
+158593
+54703
+fff5c783
+40f707b3
+1879793
+4187d793
+79663
+150513
+fe0710e3
+78513
+8067
+713
+c71863
+793
+78513
+8067
+e507b3
+7c683
+e587b3
+7c783
+40f687b3
+1879793
+4187d793
+fc079ee3
+fc068ce3
+170713
+fc9ff06f
+50793
+7c703
+178693
+71e63
+158593
+fff5c703
+178793
+fee78fa3
+fe0718e3
+8067
+68793
+fd9ff06f
+50793
+61663
+8067
+68793
+7c703
+178693
+fe071ae3
+c78633
+158593
+fff5c703
+178793
+fee78fa3
+fc070ce3
+fec796e3
+78023
+8067
+50793
+7c703
+71663
+40a78533
+8067
+178793
+fedff06f
+fe010113
+812c23
+b12623
+50413
+112e23
+fd1ff0ef
+c12583
+a40533
+ff5f593
+54783
+b78863
+fff50513
+fe857ae3
+513
+1c12083
+1812403
+2010113
+8067
+b505b3
+50793
+b78663
+7c703
+71663
+40a78533
+8067
+178793
+fe9ff06f
+793
+f50733
+74683
+68e63
+58713
+c0006f
+d60c63
+170713
+74603
+fe061ae3
+78513
+8067
+178793
+fd1ff06f
+713
+e61663
+793
+200006f
+e507b3
+e586b3
+7c783
+6c683
+170713
+40d787b3
+fc078ee3
+78513
+8067
+c50633
+50793
+c79463
+8067
+178793
+feb78fa3
+ff1ff06f
+793
+f61463
+8067
+f58733
+74683
+f50733
+178793
+d70023
+fe5ff06f
+2a5fa63
+fff64693
+793
+fff78793
+2f69663
+8067
+f58733
+74683
+f50733
+178793
+d70023
+fef616e3
+8067
+793
+ff5ff06f
+f60733
+e58833
+84803
+e50733
+1070023
+fbdff06f
+fe010113
+812c23
+50413
+58513
+1312623
+112e23
+912a23
+1212823
+1412423
+58993
+e51ff0ef
+4050063
+50913
+40513
+e41ff0ef
+50493
+a40a33
+409a0433
+124f663
+413
+1c0006f
+90613
+98593
+40513
+fff48493
+ed5ff0ef
+fc051ee3
+40513
+1c12083
+1812403
+1412483
+1012903
+c12983
+812a03
+2010113
+8067
+c50633
+ff5f593
+c51663
+513
+8067
+54703
+150793
+feb70ae3
+78513
+fe5ff06f
+fd010113
+2812423
+3212023
+1312e23
+2112623
+2912223
+5937
+50413
+58993
+54783
+fe490913
+4061e63
+3000713
+a00613
+4e79463
+154783
+150693
+f90733
+74703
+277713
+70663
+fe078793
+ff7f793
+5800713
+ce79c63
+244783
+f907b3
+7c783
+447f793
+c078263
+240413
+1000613
+513
+580006f
+1000713
+fee61ae3
+3000713
+fee796e3
+154783
+f90733
+74703
+277713
+70663
+fe078793
+ff7f793
+5800713
+fce794e3
+240413
+fc1ff06f
+60593
+c12623
+388010ef
+c12603
+950533
+140413
+44783
+f90733
+74703
+4477693
+2068463
+477693
+fd078493
+69c63
+277713
+70663
+fe078793
+ff7f793
+fc978493
+fac4eae3
+98463
+89a023
+2c12083
+2812403
+2412483
+2012903
+1c12983
+3010113
+8067
+68413
+800613
+f41ff06f
+54683
+2d00713
+e68463
+eb1ff06f
+ff010113
+150513
+112623
+ea1ff0ef
+c12083
+40a00533
+1010113
+8067
+5737
+50613
+fe470713
+513
+62683
+6c783
+f707b3
+7c783
+47f793
+79463
+8067
+168793
+f62023
+251793
+a787b3
+6c503
+179793
+a787b3
+fd078513
+fc5ff06f
+f7010113
+7312e23
+68993
+56b7
+8812423
+9212023
+7412c23
+7612823
+60a13
+fe468693
+8112623
+8912223
+7512a23
+7712623
+7812423
+7912223
+4087613
+50413
+58913
+12868b13
+60463
+10068b13
+1087693
+68463
+ffe87813
+ffe98693
+2200613
+513
+22d66a63
+187693
+3000c13
+69463
+2000c13
+287693
+a93
+68a63
+80a5863
+41400a33
+fff70713
+2d00a93
+2087c93
+c8863
+1000693
+8d99e63
+ffe70713
+a0a1263
+3000693
+d10e23
+100493
+48693
+f4d463
+78693
+1187793
+40d70733
+10078463
+a8863
+1247463
+1540023
+140413
+c8e63
+800793
+ef99e63
+1247663
+3000793
+f40023
+140413
+1087813
+14080063
+40513
+d406b3
+3000613
+1480006f
+487693
+68863
+fff70713
+2b00a93
+f71ff06f
+887693
+f60684e3
+fff70713
+2000a93
+f5dff06f
+800693
+f6d994e3
+fff70713
+f61ff06f
+1c10b93
+493
+98593
+a0513
+1012623
+f12423
+e12223
+705000ef
+ab0533
+54683
+98593
+a0513
+db8023
+72d000ef
+148493
+1b8b93
+412703
+812783
+c12803
+f33a60e3
+50a13
+fb5ff06f
+127f463
+a78023
+178793
+40f58633
+fec048e3
+70793
+75463
+793
+fff70713
+f40433
+40f70733
+f01ff06f
+40793
+e405b3
+2000513
+fd1ff06f
+1000793
+f0f99ae3
+1247663
+3000793
+f40023
+140793
+127f663
+21b4783
+f400a3
+240413
+ef1ff06f
+127f463
+1878023
+178793
+40f58633
+fec048e3
+70793
+75463
+793
+fff70713
+f40433
+40f70733
+ec9ff06f
+40793
+e405b3
+fd5ff06f
+1257463
+c50023
+150513
+40a687b3
+fef4c8e3
+48793
+50693
+fff00613
+fff78793
+4c79e63
+950533
+50793
+e50633
+2000593
+40f606b3
+6d04063
+75463
+713
+e50533
+8c12083
+8812403
+8412483
+8012903
+7c12983
+7812a03
+7412a83
+7012b03
+6c12b83
+6812c03
+6412c83
+9010113
+8067
+126fa63
+1c10593
+f585b3
+5c583
+b68023
+168693
+f89ff06f
+127f463
+b78023
+178793
+f91ff06f
+ff010113
+812423
+112623
+58413
+65000ef
+856463
+fff40513
+c12083
+812403
+1010113
+8067
+fc010113
+2d12623
+2c10693
+112e23
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+25000ef
+1c12083
+4010113
+8067
+fc010113
+2d12623
+2c10693
+812c23
+112e23
+58413
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+7e8000ef
+856463
+fff40513
+1c12083
+1812403
+4010113
+8067
+60693
+58613
+800005b7
+fff5c593
+7bc0006f
+fc010113
+2c12423
+58613
+800005b7
+2d12623
+fff5c593
+2810693
+112e23
+2e12823
+2f12a23
+3012c23
+3112e23
+d12623
+784000ef
+1c12083
+4010113
+8067
+1000737
+1872783
+779513
+f50533
+361967b7
+2e978793
+f50533
+a72c23
+8067
+10007b7
+a7ac23
+8067
+5537
+ff010113
+13450513
+112623
+42c000ef
+6f
+1851713
+1855793
+106b7
+e7e7b3
+f0068693
+855713
+d77733
+e7e7b3
+851513
+ff0737
+e57533
+a7e533
+8067
+851793
+855513
+a7e533
+1051513
+1055513
+8067
+1851713
+1855793
+106b7
+e7e7b3
+f0068693
+855713
+d77733
+e7e7b3
+851513
+ff0737
+e57533
+a7e533
+8067
+851793
+855513
+a7e533
+1051513
+1055513
+8067
+56b7
+793
+b505b3
+14068693
+40a58733
+e04663
+78513
+8067
+150513
+fff54603
+87d713
+879793
+c74733
+271713
+e68733
+75703
+1079793
+107d793
+f747b3
+fc5ff06f
+56b7
+50713
+fff00793
+b508b3
+700813
+54068693
+40e88633
+4c86a63
+35d713
+371693
+40d585b3
+d50533
+2058c63
+56b7
+b505b3
+54068693
+150513
+fff54703
+f74733
+ff77713
+271713
+e68733
+72703
+87d793
+f747b3
+fcb51ee3
+fff7c513
+8067
+74603
+870713
+f64633
+ff67613
+261613
+c68633
+62603
+87d793
+f647b3
+ff974603
+f64633
+ff67613
+261613
+c68633
+62603
+87d793
+f64633
+ffa74783
+c7c7b3
+ff7f793
+279793
+f687b3
+7a303
+ffb74783
+865613
+c34333
+67c7b3
+ff7f793
+279793
+f687b3
+7a603
+ffc74783
+835313
+664633
+c7c7b3
+ff7f793
+279793
+f687b3
+7a303
+ffd74783
+865613
+c34333
+67c7b3
+ff7f793
+279793
+f687b3
+7a783
+ffe74603
+835313
+67c7b3
+f64633
+ff67613
+261613
+c68633
+62303
+fff74603
+87d793
+f34333
+664633
+ff67613
+261613
+c68633
+62783
+835313
+67c7b3
+ea5ff06f
+10007b7
+2a7a223
+8067
+10007b7
+2a7a023
+10007b7
+b7ae23
+8067
+ff010113
+912223
+ff57493
+812423
+50413
+48513
+112623
+3b4000ef
+10007b7
+247a783
+78663
+48513
+780e7
+a00793
+f41663
+d00513
+fc1ff0ef
+40513
+c12083
+812403
+412483
+1010113
+8067
+ff010113
+812423
+112623
+1000437
+348000ef
+50a63
+812403
+c12083
+1010113
+2e00006f
+1c42783
+fe0782e3
+780e7
+fc050ee3
+812403
+10007b7
+c12083
+207a303
+1010113
+30067
+ff010113
+112623
+300000ef
+2051263
+10007b7
+1c7a783
+78663
+780e7
+a03533
+c12083
+1010113
+8067
+100513
+ff1ff06f
+ff010113
+812423
+112623
+50413
+44503
+2051063
+a00513
+f01ff0ef
+c12083
+812403
+100513
+1010113
+8067
+ee9ff0ef
+140413
+fd5ff06f
+ff010113
+812423
+112623
+50413
+44503
+51a63
+c12083
+812403
+1010113
+8067
+eb5ff0ef
+140413
+fe1ff06f
+ef010113
+58693
+50613
+10000593
+10513
+10112623
+10812423
+ac5ff0ef
+10010793
+50413
+a787b3
+10513
+f0078023
+f99ff0ef
+40513
+10c12083
+10812403
+11010113
+8067
+fc010113
+2b12223
+2410593
+112e23
+2c12423
+2d12623
+2e12823
+2f12a23
+3012c23
+3112e23
+b12623
+f89ff0ef
+1c12083
+4010113
+8067
+8067
+ff010113
+812423
+112623
+82002437
+2042023
+42823
+42a23
+42c23
+185b7
+42e23
+6a058593
+1b5000ef
+1855793
+f42023
+1055793
+f42223
+855793
+f42423
+a42623
+100793
+2f42023
+2f42223
+82002737
+100613
+2872783
+2c72683
+879793
+d7e7b3
+3072683
+879793
+d7e7b3
+3472683
+879793
+d7e7b3
+79a63
+c12083
+812403
+1010113
+8067
+2c72223
+fc1ff06f
+50023
+8067
+820027b7
+8107a703
+277793
+79863
+177713
+4071e63
+8067
+10007b7
+307a803
+10005b7
+820026b7
+1000637
+2b858593
+200893
+8086a783
+ff7f793
+fc0798e3
+3462783
+178793
+7f7f793
+f80c63
+3462503
+8006a303
+2f62a23
+a58533
+650023
+8116a823
+fcdff06f
+820027b7
+100713
+80e7a823
+10007b7
+2c7a583
+10006b7
+1000737
+82002637
+2b868693
+2872783
+b78863
+80462783
+ff7f793
+78463
+8067
+2872783
+f687b3
+807c783
+80f62023
+2872783
+178793
+7f7f793
+2f72423
+fc9ff06f
+30002673
+1000737
+867613
+3072783
+70693
+1000737
+2060663
+3472603
+fef60ee3
+1000737
+2b870713
+f70733
+178793
+7f7f793
+74503
+2f6a823
+100006f
+3472703
+513
+fcf71ce3
+8067
+1000737
+10007b7
+347a783
+3072503
+40f50533
+a03533
+8067
+10006b7
+2c6a603
+160793
+7f7f793
+300025f3
+85f593
+1000737
+4058663
+2872583
+fef58ee3
+bc0025f3
+ffe5f813
+bc081073
+2872703
+e61a63
+82002837
+80482703
+ff77713
+2070663
+1000737
+2b870713
+c70733
+8a70023
+2f6a623
+bc059073
+c0006f
+2872583
+faf59ee3
+8067
+80a82023
+fe9ff06f
+10007b7
+207aa23
+10007b7
+207a823
+10007b7
+207a623
+10007b7
+207a423
+820027b7
+8107a703
+ff77713
+80e7a823
+300713
+80e7aa23
+bc0027f3
+17e793
+bc079073
+8067
+10007b7
+2c7a783
+10006b7
+286a703
+fef71ee3
+8067
+fc010113
+2112e23
+2812c23
+2912a23
+3212823
+3312623
+3412423
+3512223
+3612023
+1712e23
+1812c23
+1912a23
+1a12823
+c12623
+4c05c063
+b509b3
+50a13
+58b13
+68493
+a9f663
+fff54b13
+fff00993
+5c37
+6cb7
+a0413
+2500b93
+2000a93
+fe4c0c13
+940c8c93
+2b40006f
+1778a63
+1347463
+f40023
+140413
+2940006f
+913
+2b00713
+2d00613
+3000593
+2300513
+c12683
+168793
+f12623
+16c783
+12e78e63
+12f76063
+13578e63
+14a78063
+fc0733
+74703
+477713
+12070c63
+c10513
+b64ff0ef
+50713
+c12683
+2e00613
+fff00793
+6c583
+2c59e63
+168793
+f12623
+16c603
+cc07b3
+7c783
+47f793
+12078463
+c10513
+e12423
+b24ff0ef
+812703
+50793
+55463
+793
+c12683
+6800593
+6c603
+2b60263
+df67593
+4c00513
+a58c63
+5a00513
+a58863
+7400593
+fff00813
+2b61663
+60813
+168613
+c12623
+6c00613
+c81c63
+16c603
+1061863
+268693
+d12623
+4c00813
+c12683
+6c603
+6e00693
+2cd60a63
+cc6ee63
+6300693
+14d60a63
+ac6ea63
+2d760a63
+5800693
+2cd60c63
+1347463
+1740023
+c12783
+140713
+7c683
+2c068663
+1377463
+d400a3
+240413
+14c0006f
+c78863
+eeb794e3
+196913
+ec1ff06f
+1096913
+eb9ff06f
+496913
+eb1ff06f
+896913
+ea9ff06f
+2096913
+ea1ff06f
+2a00613
+fff00713
+ecc798e3
+4a703
+268693
+d12623
+448493
+ea075ee3
+40e00733
+1096913
+eb1ff06f
+2a00593
+793
+eeb618e3
+268693
+4a503
+d12623
+448493
+ed1ff06f
+6400693
+d60663
+6900693
+f4d618e3
+296913
+a00693
+680006f
+7300693
+14d60863
+4c6e463
+6f00693
+22d60063
+7000693
+f2d614e3
+fff00693
+d71663
+196913
+800713
+4a603
+448d13
+90813
+1000693
+40513
+98593
+9d8ff0ef
+50413
+1640006f
+7500693
+fad602e3
+7800593
+1000693
+eeb610e3
+4c00613
+1cc81863
+748493
+ff84f493
+848d13
+4a603
+1f80006f
+1097913
+a090c63
+40793
+448693
+1347663
+4a603
+c40023
+140413
+e78733
+408707b3
+8f04e63
+68493
+c12783
+178793
+f12623
+c12783
+7c783
+d40794e3
+b0663
+1b347c63
+40023
+41440533
+3c12083
+3812403
+3412483
+3012903
+2c12983
+2812a03
+2412a83
+2012b03
+1c12b83
+1812c03
+1412c83
+1012d03
+4010113
+8067
+1347463
+1540023
+140413
+fff78793
+fef048e3
+fff70793
+e04463
+100713
+40e78733
+170713
+f51ff06f
+70793
+fddff06f
+1347463
+1540023
+140413
+f55ff06f
+448d13
+4a483
+49463
+c8493
+78593
+48513
+e12423
+1097913
+d09fe0ef
+812703
+91863
+70793
+fff70713
+2f54863
+793
+2a7cc63
+50793
+55463
+793
+f40433
+e40733
+408707b3
+2f54c63
+d0493
+efdff06f
+1347463
+1540023
+140413
+fbdff06f
+f406b3
+136f863
+f48633
+64603
+c68023
+178793
+fb1ff06f
+1347463
+1540023
+140413
+fb9ff06f
+4a783
+41440733
+448493
+e7a023
+eadff06f
+c13478e3
+1740023
+c09ff06f
+4096913
+1000693
+e49ff06f
+fff78793
+f12623
+70413
+e85ff06f
+800693
+e31ff06f
+6c00613
+448d13
+e2c80ce3
+fdf87613
+5a00593
+e2b606e3
+7400613
+e2c802e3
+6800613
+297593
+e0c81ce3
+4a603
+1061613
+59863
+1065613
+90813
+dc5ff06f
+41065613
+ff5ff06f
+fe098fa3
+e4dff06f
+513
+e49ff06f
+ff010113
+112623
+812423
+912223
+50413
+58493
+28000ef
+50593
+48513
+1f4000ef
+40a40533
+c12083
+812403
+412483
+1010113
+8067
+fe010113
+112e23
+812c23
+912a23
+a058263
+50413
+8050263
+58513
+b12623
+11c000ef
+50493
+40513
+110000ef
+40a48533
+1f00793
+6a7ec63
+4f50e63
+c12583
+150513
+2000713
+40a70733
+e41733
+793
+a45433
+fff58813
+141413
+1f75613
+866633
+40c806b3
+41f6d693
+171713
+b6f433
+fff50513
+f76733
+40860433
+16f793
+fc051ae3
+171413
+f46433
+40513
+1c12083
+1812403
+1412483
+2010113
+8067
+413
+fe5ff06f
+41f55793
+41f5d713
+f54533
+e5c5b3
+ff010113
+40e585b3
+40f50533
+812423
+112623
+e7c433
+f1dff0ef
+854533
+40850533
+c12083
+812403
+1010113
+8067
+ff010113
+112623
+812423
+912223
+50413
+58493
+fa5ff0ef
+50593
+48513
+b4000ef
+40a40533
+c12083
+812403
+412483
+1010113
+8067
+ffff0737
+e57733
+173693
+469693
+1000793
+40d787b3
+10737
+f557b3
+f0070713
+e7f733
+173713
+371713
+800513
+40e50533
+a7d7b3
+f07f513
+153513
+251513
+d70733
+400693
+40a686b3
+d7d7b3
+e50733
+c7f513
+153513
+200613
+151513
+40a606b3
+d7d7b3
+17d693
+16c693
+16f693
+40d006b3
+40f607b3
+f6f7b3
+e50533
+a78533
+8067
+50793
+513
+79463
+8067
+17f713
+70463
+b50533
+159593
+17d793
+fe5ff06f
+82003028
+8200305c
+82003090
+820030c4
+82003018
+8200304c
+82003080
+820030b4
+616c6564
+203a7379
+0
+2d
+64323025
+30252d2b
+6432
+41524453
+6f6e204d
+6e752077
+20726564
+74666f73
+65726177
+6e6f6320
+6c6f7274
+a
+41524453
+6f6e204d
+6e752077
+20726564
+64726168
+65726177
+6e6f6320
+6c6f7274
+a
+78323025
+0
+783225
+746d654d
+20747365
+20737562
+6c696166
+203a6465
+252f6425
+72652064
+73726f72
+a
+746d654d
+20747365
+61746164
+69616620
+3a64656c
+2f642520
+65206425
+726f7272
+a73
+746d654d
+20747365
+72646461
+69616620
+3a64656c
+2f642520
+65206425
+726f7272
+a73
+746d654d
+20747365
+a4b4f
+736d654d
+64656570
+69725720
+3a736574
+4d642520
+20737062
+64616552
+25203a73
+70624d64
+a73
+64616552
+76656c20
+6e696c65
+a3a67
+2c64256d
+64256220
+7c203a
+6425
+207c
+74736562
+256d203a
+62202c64
+206425
+74696e49
+696c6169
+676e697a
+52445320
+2e2e4d41
+a2e
+6d315b1b
+20202020
+20202020
+20205f5f
+5f205f20
+2020205f
+5f202020
+5f5f2020
+6d305b1b
+a
+6d315b1b
+20202020
+2f202020
+20202f20
+20295f28
+5f5f5f2f
+207c205f
+2f5f2f7c
+6d305b1b
+a
+6d315b1b
+20202020
+202f2020
+2f5f5f2f
+5f202f20
+2d202f5f
+203e295f
+5b1b3c20
+a6d30
+6d315b1b
+20202020
+5f5f2f20
+5f2f5f5f
+5f5f5c2f
+5f5f5c2f
+7c2f5f2f
+5b1b7c5f
+a6d30
+6d315b1b
+42202020
+646c6975
+756f7920
+61682072
+61776472
+202c6572
+69736165
+1b21796c
+a6d305b
+0
+29632820
+706f4320
+67697279
+32207468
+2d323130
+30323032
+6a6e4520
+442d796f
+74696769
+a6c61
+29632820
+706f4320
+67697279
+32207468
+2d373030
+35313032
+4c2d4d20
+a736261
+0
+4f494220
+75622053
+20746c69
+4d206e6f
+20207961
+30322038
+30203032
+39323a31
+a31323a
+0
+67694d20
+67206e65
+73207469
+3a316168
+39636420
+36656663
+a
+74694c20
+67205865
+73207469
+3a316168
+65393720
+35333165
+a66
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+5b1b203d
+6f536d31
+305b1b43
+3d3d206d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+52786556
+76637369
+0
+6d315b1b
+1b555043
+3a6d305b
+20202020
+25202020
+20402073
+484d6425
+a7a
+6d315b1b
+1b4d4f52
+3a6d305b
+20202020
+25202020
+a424b64
+0
+6d315b1b
+4d415253
+6d305b1b
+2020203a
+25202020
+a424b64
+0
+6d315b1b
+5b1b324c
+203a6d30
+20202020
+25202020
+a424b64
+0
+6d315b1b
+4e49414d
+4d41522d
+6d305b1b
+2520203a
+a424b64
+0
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+315b1b20
+696e496d
+6c616974
+74617a69
+1b6e6f69
+206d305b
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+6f6d654d
+69207972
+6974696e
+7a696c61
+6f697461
+6166206e
+64656c69
+a
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+315b1b20
+6f6f426d
+305b1b74
+3d3d206d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+62206f4e
+20746f6f
+6964656d
+66206d75
+646e756f
+a
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+203d3d3d
+6d315b1b
+736e6f43
+1b656c6f
+206d305b
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+32395b1b
+6c6d313b
+78657469
+6d305b1b
+203e
+73250a
+6d6d6f43
+20646e61
+20746f6e
+6e756f66
+64
+1598
+15d4
+1638
+15d4
+14b8
+16f0
+44354c73
+6d4d5364
+726b656b
+a6f
+4849367a
+59633747
+36444944
+a6f
+746f6f42
+20676e69
+6d6f7266
+72657320
+2e6c6169
+a2e2e
+73657250
+20512073
+4520726f
+74204353
+6261206f
+2074726f
+746f6f62
+6d6f6320
+74656c70
+2e796c65
+a
+206f6f54
+796e616d
+6e6f6320
+75636573
+65766974
+72726520
+2c73726f
+6f626120
+6e697472
+67
+63657845
+6e697475
+6f622067
+6465746f
+6f727020
+6d617267
+20746120
+30257830
+a0a7838
+0
+3d3d2d2d
+3d3d3d3d
+3d3d3d3d
+203d3d3d
+6d315b1b
+7466694c
+2166666f
+6d305b1b
+3d3d3d20
+3d3d3d3d
+3d3d3d3d
+3d3d3d3d
+a2d2d
+656d6954
+a74756f
+0
+636e6143
+656c6c65
+a64
+6f6d654d
+64207972
+3a706d75
+0
+2578300a
+20783830
+20
+78323025
+20
+202020
+2e
+6325
+4f494220
+52432053
+61702043
+64657373
+30252820
+a297838
+0
+4f494220
+52432053
+61662043
+64656c69
+78652820
+74636570
+25206465
+2c783830
+746f6720
+38302520
+a2978
+65685420
+73797320
+206d6574
+6c6c6977
+6e6f6320
+756e6974
+62202c65
+65207475
+63657078
+72702074
+656c626f
+a2e736d
+0
+74694c0a
+42205865
+2c534f49
+61766120
+62616c69
+6320656c
+616d6d6f
+3a73646e
+a
+36312d25
+202d2073
+a7325
+6e656449
+25203a74
+73
+20637263
+6464613c
+73736572
+6c3c203e
+74676e65
+3e68
+6f636e49
+63657272
+64612074
+73657264
+73
+6f636e49
+63657272
+656c2074
+6874676e
+0
+33435243
+25203a32
+783830
+73756c66
+326c5f68
+6361635f
+6568
+73756c46
+324c2068
+63616320
+6568
+73756c66
+70635f68
+63645f75
+65686361
+0
+73756c46
+50432068
+61642055
+63206174
+65686361
+0
+637263
+706d6f43
+20657475
+33435243
+666f2032
+70206120
+20747261
+7420666f
+61206568
+65726464
+73207373
+65636170
+0
+6f626572
+746f
+65736552
+72702074
+7365636f
+726f73
+6e656469
+74
+70736944
+2079616c
+6e656469
+69666974
+7265
+706c6568
+0
+6e697250
+68742074
+68207369
+706c65
+69726573
+6f626c61
+746f
+746f6f42
+61697620
+4c465320
+0
+63657250
+67726168
+6465
+6f636e49
+63657272
+6f722074
+77
+69746341
+65746176
+6f722064
+64252077
+0
+72726473
+613c2064
+65726464
+3e7373
+6f636e49
+63657272
+51442074
+0
+72726473
+72726564
+6f633c20
+3e746e75
+0
+6f636e49
+63657272
+6f632074
+746e75
+77726473
+613c2072
+65726464
+3e7373
+746d656d
+747365
+206e7552
+656d2061
+79726f6d
+73657420
+74
+6c726473
+6c657665
+0
+66726550
+206d726f
+64616572
+6972772f
+6c206574
+6c657665
+676e69
+69726473
+74696e
+72617453
+44532074
+204d4152
+74696e69
+696c6169
+69746173
+6e6f
+77726473
+72
+74697257
+44532065
+204d4152
+74736574
+74616420
+61
+72726473
+72726564
+0
+6e697250
+44532074
+204d4152
+64616572
+72726520
+73726f
+72726473
+64
+64616552
+52445320
+64204d41
+617461
+72726473
+66756264
+0
+706d7544
+52445320
+72204d41
+20646165
+66667562
+7265
+68726473
+77
+65766947
+44532073
+204d4152
+746e6f63
+206c6f72
+48206f74
+57
+73726473
+77
+65766947
+44532073
+204d4152
+746e6f63
+206c6f72
+53206f74
+57
+72726473
+776f
+63657250
+67726168
+63412f65
+61766974
+72206574
+776f
+3c20776d
+72646461
+3e737365
+61763c20
+3e65756c
+6f635b20
+5d746e75
+0
+6f636e49
+63657272
+61762074
+65756c
+3c20636d
+3e747364
+72733c20
+5b203e63
+6e756f63
+5d74
+6f636e49
+63657272
+65642074
+6e697473
+6f697461
+6461206e
+73657264
+73
+6f636e49
+63657272
+6f732074
+65637275
+64646120
+73736572
+0
+3c20726d
+72646461
+3e737365
+656c5b20
+6874676e
+5d
+636e490a
+6572726f
+6c207463
+74676e65
+68
+636d
+79706f43
+64646120
+73736572
+61707320
+6563
+776d
+74697257
+64612065
+73657264
+70732073
+656361
+726d
+64616552
+64646120
+73736572
+61707320
+6563
+732a2d25
+0
+4f9c
+10
+4fa0
+e
+4fa4
+6
+4fa8
+2
+4fac
+1
+4fb0
+85
+4fb4
+10
+4fb8
+e
+4fbc
+6
+4fc0
+2
+4fc4
+1
+4fc8
+85
+4fcc
+1
+4fd0
+f
+4fd4
+89
+4fd8
+85
+4fdc
+87
+4fe0
+88
+732a2e25
+0
+73257325
+0
+414f
+424f
+434f
+444f
+484f
+464f
+415b
+425b
+435b
+445b
+485b
+465b
+7e315b
+7e325b
+7e335b
+7e345b
+7e355b
+7e365b
+8080808
+8080808
+28282808
+8082828
+8080808
+8080808
+8080808
+8080808
+101010a0
+10101010
+10101010
+10101010
+4040404
+4040404
+10100404
+10101010
+41414110
+1414141
+1010101
+1010101
+1010101
+1010101
+10010101
+10101010
+42424210
+2424242
+2020202
+2020202
+2020202
+2020202
+10020202
+8101010
+0
+0
+0
+0
+0
+0
+0
+0
+101010a0
+10101010
+10101010
+10101010
+10101010
+10101010
+10101010
+10101010
+1010101
+1010101
+1010101
+1010101
+1010101
+10010101
+1010101
+2010101
+2020202
+2020202
+2020202
+2020202
+2020202
+10020202
+2020202
+2020202
+33323130
+37363534
+42413938
+46454443
+4a494847
+4e4d4c4b
+5251504f
+56555453
+5a595857
+0
+33323130
+37363534
+62613938
+66656463
+6a696867
+6e6d6c6b
+7271706f
+76757473
+7a797877
+0
+726f6241
+2e646574
+0
+0
+1021
+2042
+3063
+4084
+50a5
+60c6
+70e7
+8108
+9129
+a14a
+b16b
+c18c
+d1ad
+e1ce
+f1ef
+1231
+210
+3273
+2252
+52b5
+4294
+72f7
+62d6
+9339
+8318
+b37b
+a35a
+d3bd
+c39c
+f3ff
+e3de
+2462
+3443
+420
+1401
+64e6
+74c7
+44a4
+5485
+a56a
+b54b
+8528
+9509
+e5ee
+f5cf
+c5ac
+d58d
+3653
+2672
+1611
+630
+76d7
+66f6
+5695
+46b4
+b75b
+a77a
+9719
+8738
+f7df
+e7fe
+d79d
+c7bc
+48c4
+58e5
+6886
+78a7
+840
+1861
+2802
+3823
+c9cc
+d9ed
+e98e
+f9af
+8948
+9969
+a90a
+b92b
+5af5
+4ad4
+7ab7
+6a96
+1a71
+a50
+3a33
+2a12
+dbfd
+cbdc
+fbbf
+eb9e
+9b79
+8b58
+bb3b
+ab1a
+6ca6
+7c87
+4ce4
+5cc5
+2c22
+3c03
+c60
+1c41
+edae
+fd8f
+cdec
+ddcd
+ad2a
+bd0b
+8d68
+9d49
+7e97
+6eb6
+5ed5
+4ef4
+3e13
+2e32
+1e51
+e70
+ff9f
+efbe
+dfdd
+cffc
+bf1b
+af3a
+9f59
+8f78
+9188
+81a9
+b1ca
+a1eb
+d10c
+c12d
+f14e
+e16f
+1080
+a1
+30c2
+20e3
+5004
+4025
+7046
+6067
+83b9
+9398
+a3fb
+b3da
+c33d
+d31c
+e37f
+f35e
+2b1
+1290
+22f3
+32d2
+4235
+5214
+6277
+7256
+b5ea
+a5cb
+95a8
+8589
+f56e
+e54f
+d52c
+c50d
+34e2
+24c3
+14a0
+481
+7466
+6447
+5424
+4405
+a7db
+b7fa
+8799
+97b8
+e75f
+f77e
+c71d
+d73c
+26d3
+36f2
+691
+16b0
+6657
+7676
+4615
+5634
+d94c
+c96d
+f90e
+e92f
+99c8
+89e9
+b98a
+a9ab
+5844
+4865
+7806
+6827
+18c0
+8e1
+3882
+28a3
+cb7d
+db5c
+eb3f
+fb1e
+8bf9
+9bd8
+abbb
+bb9a
+4a75
+5a54
+6a37
+7a16
+af1
+1ad0
+2ab3
+3a92
+fd2e
+ed0f
+dd6c
+cd4d
+bdaa
+ad8b
+9de8
+8dc9
+7c26
+6c07
+5c64
+4c45
+3ca2
+2c83
+1ce0
+cc1
+ef1f
+ff3e
+cf5d
+df7c
+af9b
+bfba
+8fd9
+9ff8
+6e17
+7e36
+4e55
+5e74
+2e93
+3eb2
+ed1
+1ef0
+0
+77073096
+ee0e612c
+990951ba
+76dc419
+706af48f
+e963a535
+9e6495a3
+edb8832
+79dcb8a4
+e0d5e91e
+97d2d988
+9b64c2b
+7eb17cbd
+e7b82d07
+90bf1d91
+1db71064
+6ab020f2
+f3b97148
+84be41de
+1adad47d
+6ddde4eb
+f4d4b551
+83d385c7
+136c9856
+646ba8c0
+fd62f97a
+8a65c9ec
+14015c4f
+63066cd9
+fa0f3d63
+8d080df5
+3b6e20c8
+4c69105e
+d56041e4
+a2677172
+3c03e4d1
+4b04d447
+d20d85fd
+a50ab56b
+35b5a8fa
+42b2986c
+dbbbc9d6
+acbcf940
+32d86ce3
+45df5c75
+dcd60dcf
+abd13d59
+26d930ac
+51de003a
+c8d75180
+bfd06116
+21b4f4b5
+56b3c423
+cfba9599
+b8bda50f
+2802b89e
+5f058808
+c60cd9b2
+b10be924
+2f6f7c87
+58684c11
+c1611dab
+b6662d3d
+76dc4190
+1db7106
+98d220bc
+efd5102a
+71b18589
+6b6b51f
+9fbfe4a5
+e8b8d433
+7807c9a2
+f00f934
+9609a88e
+e10e9818
+7f6a0dbb
+86d3d2d
+91646c97
+e6635c01
+6b6b51f4
+1c6c6162
+856530d8
+f262004e
+6c0695ed
+1b01a57b
+8208f4c1
+f50fc457
+65b0d9c6
+12b7e950
+8bbeb8ea
+fcb9887c
+62dd1ddf
+15da2d49
+8cd37cf3
+fbd44c65
+4db26158
+3ab551ce
+a3bc0074
+d4bb30e2
+4adfa541
+3dd895d7
+a4d1c46d
+d3d6f4fb
+4369e96a
+346ed9fc
+ad678846
+da60b8d0
+44042d73
+33031de5
+aa0a4c5f
+dd0d7cc9
+5005713c
+270241aa
+be0b1010
+c90c2086
+5768b525
+206f85b3
+b966d409
+ce61e49f
+5edef90e
+29d9c998
+b0d09822
+c7d7a8b4
+59b33d17
+2eb40d81
+b7bd5c3b
+c0ba6cad
+edb88320
+9abfb3b6
+3b6e20c
+74b1d29a
+ead54739
+9dd277af
+4db2615
+73dc1683
+e3630b12
+94643b84
+d6d6a3e
+7a6a5aa8
+e40ecf0b
+9309ff9d
+a00ae27
+7d079eb1
+f00f9344
+8708a3d2
+1e01f268
+6906c2fe
+f762575d
+806567cb
+196c3671
+6e6b06e7
+fed41b76
+89d32be0
+10da7a5a
+67dd4acc
+f9b9df6f
+8ebeeff9
+17b7be43
+60b08ed5
+d6d6a3e8
+a1d1937e
+38d8c2c4
+4fdff252
+d1bb67f1
+a6bc5767
+3fb506dd
+48b2364b
+d80d2bda
+af0a1b4c
+36034af6
+41047a60
+df60efc3
+a867df55
+316e8eef
+4669be79
+cb61b38c
+bc66831a
+256fd2a0
+5268e236
+cc0c7795
+bb0b4703
+220216b9
+5505262f
+c5ba3bbe
+b2bd0b28
+2bb45a92
+5cb36a04
+c2d7ffa7
+b5d0cf31
+2cd99e8b
+5bdeae1d
+9b64c2b0
+ec63f226
+756aa39c
+26d930a
+9c0906a9
+eb0e363f
+72076785
+5005713
+95bf4a82
+e2b87a14
+7bb12bae
+cb61b38
+92d28e9b
+e5d5be0d
+7cdcefb7
+bdbdf21
+86d3d2d4
+f1d4e242
+68ddb3f8
+1fda836e
+81be16cd
+f6b9265b
+6fb077e1
+18b74777
+88085ae6
+ff0f6a70
+66063bca
+11010b5c
+8f659eff
+f862ae69
+616bffd3
+166ccf45
+a00ae278
+d70dd2ee
+4e048354
+3903b3c2
+a7672661
+d06016f7
+4969474d
+3e6e77db
+aed16a4a
+d9d65adc
+40df0b66
+37d83bf0
+a9bcae53
+debb9ec5
+47b2cf7f
+30b5ffe9
+bdbdf21c
+cabac28a
+53b39330
+24b4a3a6
+bad03605
+cdd70693
+54de5729
+23d967bf
+b3667a2e
+c4614ab8
+5d681b02
+2a6f2b94
+b40bbe37
+c30c8ea1
+5a05df1b
+2d02ef8d
+4c554e3c
+3e4c
+5998
+59a8
+59b8
+59c8
+59d8
+59e8
+59f8
+5a08
+5a18
+5a28
+5a38
+5a48
+5a58
+5a68
+5a78
+5a88
+5a98
+5aa8
+5ab8
+5ac8
+3a2c
+4b40
+4b50
+2
+1a20
+4b60
+4b74
+2
+1b64
+4b8c
+4b90
+0
+1a4c
+4bc0
+4bc8
+1
+1b28
+4bd8
+4be0
+1
+1a5c
+4bf4
+4bfc
+0
+1378
+4c0c
+4c18
+3
+9b4
+4cac
+4cb4
+4
+cac
+4cc8
+4cd4
+4
+100c
+4cf0
+4cf8
+4
+1da4
+4d14
+4d1c
+4
+1d4c
+4d34
+4d40
+4
+1c98
+4d58
+4d60
+4
+1c90
+4d70
+4d7c
+4
+550
+4d94
+4d9c
+4
+538
+4db8
+4dc0
+4
+1c14
+4ddc
+4de4
+4
+1ef4
+4eac
+4eb0
+6
+1dfc
+4ec4
+4ec8
+6
+1ff4
+4edc
+4ee0
+6
+1
+0
+f4e72d36
--- /dev/null
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:22
+//--------------------------------------------------------------------------------
+module litedram_core(
+ output reg serial_tx,
+ input wire serial_rx,
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [14:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [24:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
+);
+
+reg soc_litedramcore_soccontroller_reset_storage = 1'd0;
+reg soc_litedramcore_soccontroller_reset_re = 1'd0;
+reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896;
+reg soc_litedramcore_soccontroller_scratch_re = 1'd0;
+wire [31:0] soc_litedramcore_soccontroller_bus_errors_status;
+wire soc_litedramcore_soccontroller_bus_errors_we;
+wire soc_litedramcore_soccontroller_reset;
+wire soc_litedramcore_soccontroller_bus_error;
+reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0;
+wire soc_litedramcore_cpu_reset;
+reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0;
+wire [29:0] soc_litedramcore_cpu_ibus_adr;
+wire [31:0] soc_litedramcore_cpu_ibus_dat_w;
+wire [31:0] soc_litedramcore_cpu_ibus_dat_r;
+wire [3:0] soc_litedramcore_cpu_ibus_sel;
+wire soc_litedramcore_cpu_ibus_cyc;
+wire soc_litedramcore_cpu_ibus_stb;
+wire soc_litedramcore_cpu_ibus_ack;
+wire soc_litedramcore_cpu_ibus_we;
+wire [2:0] soc_litedramcore_cpu_ibus_cti;
+wire [1:0] soc_litedramcore_cpu_ibus_bte;
+wire soc_litedramcore_cpu_ibus_err;
+wire [29:0] soc_litedramcore_cpu_dbus_adr;
+wire [31:0] soc_litedramcore_cpu_dbus_dat_w;
+wire [31:0] soc_litedramcore_cpu_dbus_dat_r;
+wire [3:0] soc_litedramcore_cpu_dbus_sel;
+wire soc_litedramcore_cpu_dbus_cyc;
+wire soc_litedramcore_cpu_dbus_stb;
+wire soc_litedramcore_cpu_dbus_ack;
+wire soc_litedramcore_cpu_dbus_we;
+wire [2:0] soc_litedramcore_cpu_dbus_cti;
+wire [1:0] soc_litedramcore_cpu_dbus_bte;
+wire soc_litedramcore_cpu_dbus_err;
+reg [31:0] soc_litedramcore_vexriscv = 32'd0;
+wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr;
+wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w;
+wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r;
+wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel;
+wire soc_litedramcore_litedramcore_ram_bus_cyc;
+wire soc_litedramcore_litedramcore_ram_bus_stb;
+reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0;
+wire soc_litedramcore_litedramcore_ram_bus_we;
+wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti;
+wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte;
+reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0;
+wire [12:0] soc_litedramcore_litedramcore_adr;
+wire [31:0] soc_litedramcore_litedramcore_dat_r;
+wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr;
+wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w;
+wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r;
+wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel;
+wire soc_litedramcore_ram_bus_ram_bus_cyc;
+wire soc_litedramcore_ram_bus_ram_bus_stb;
+reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0;
+wire soc_litedramcore_ram_bus_ram_bus_we;
+wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti;
+wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte;
+reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0;
+wire [9:0] soc_litedramcore_ram_adr;
+wire [31:0] soc_litedramcore_ram_dat_r;
+reg [3:0] soc_litedramcore_ram_we = 4'd0;
+wire [31:0] soc_litedramcore_ram_dat_w;
+reg [31:0] soc_litedramcore_storage = 32'd4947802;
+reg soc_litedramcore_re = 1'd0;
+wire soc_litedramcore_sink_valid;
+reg soc_litedramcore_sink_ready = 1'd0;
+wire soc_litedramcore_sink_first;
+wire soc_litedramcore_sink_last;
+wire [7:0] soc_litedramcore_sink_payload_data;
+reg soc_litedramcore_uart_clk_txen = 1'd0;
+reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0;
+reg [7:0] soc_litedramcore_tx_reg = 8'd0;
+reg [3:0] soc_litedramcore_tx_bitcount = 4'd0;
+reg soc_litedramcore_tx_busy = 1'd0;
+reg soc_litedramcore_source_valid = 1'd0;
+wire soc_litedramcore_source_ready;
+reg soc_litedramcore_source_first = 1'd0;
+reg soc_litedramcore_source_last = 1'd0;
+reg [7:0] soc_litedramcore_source_payload_data = 8'd0;
+reg soc_litedramcore_uart_clk_rxen = 1'd0;
+reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0;
+wire soc_litedramcore_rx;
+reg soc_litedramcore_rx_r = 1'd0;
+reg [7:0] soc_litedramcore_rx_reg = 8'd0;
+reg [3:0] soc_litedramcore_rx_bitcount = 4'd0;
+reg soc_litedramcore_rx_busy = 1'd0;
+wire soc_litedramcore_uart_rxtx_re;
+wire [7:0] soc_litedramcore_uart_rxtx_r;
+wire soc_litedramcore_uart_rxtx_we;
+wire [7:0] soc_litedramcore_uart_rxtx_w;
+wire soc_litedramcore_uart_txfull_status;
+wire soc_litedramcore_uart_txfull_we;
+wire soc_litedramcore_uart_rxempty_status;
+wire soc_litedramcore_uart_rxempty_we;
+wire soc_litedramcore_uart_irq;
+wire soc_litedramcore_uart_tx_status;
+reg soc_litedramcore_uart_tx_pending = 1'd0;
+wire soc_litedramcore_uart_tx_trigger;
+reg soc_litedramcore_uart_tx_clear = 1'd0;
+reg soc_litedramcore_uart_tx_old_trigger = 1'd0;
+wire soc_litedramcore_uart_rx_status;
+reg soc_litedramcore_uart_rx_pending = 1'd0;
+wire soc_litedramcore_uart_rx_trigger;
+reg soc_litedramcore_uart_rx_clear = 1'd0;
+reg soc_litedramcore_uart_rx_old_trigger = 1'd0;
+wire soc_litedramcore_uart_eventmanager_status_re;
+wire [1:0] soc_litedramcore_uart_eventmanager_status_r;
+wire soc_litedramcore_uart_eventmanager_status_we;
+reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0;
+wire soc_litedramcore_uart_eventmanager_pending_re;
+wire [1:0] soc_litedramcore_uart_eventmanager_pending_r;
+wire soc_litedramcore_uart_eventmanager_pending_we;
+reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0;
+reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0;
+reg soc_litedramcore_uart_eventmanager_re = 1'd0;
+wire soc_litedramcore_uart_uart_sink_valid;
+wire soc_litedramcore_uart_uart_sink_ready;
+wire soc_litedramcore_uart_uart_sink_first;
+wire soc_litedramcore_uart_uart_sink_last;
+wire [7:0] soc_litedramcore_uart_uart_sink_payload_data;
+wire soc_litedramcore_uart_uart_source_valid;
+wire soc_litedramcore_uart_uart_source_ready;
+wire soc_litedramcore_uart_uart_source_first;
+wire soc_litedramcore_uart_uart_source_last;
+wire [7:0] soc_litedramcore_uart_uart_source_payload_data;
+wire soc_litedramcore_uart_tx_fifo_sink_valid;
+wire soc_litedramcore_uart_tx_fifo_sink_ready;
+reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0;
+reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0;
+wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data;
+wire soc_litedramcore_uart_tx_fifo_source_valid;
+wire soc_litedramcore_uart_tx_fifo_source_ready;
+wire soc_litedramcore_uart_tx_fifo_source_first;
+wire soc_litedramcore_uart_tx_fifo_source_last;
+wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data;
+wire soc_litedramcore_uart_tx_fifo_re;
+reg soc_litedramcore_uart_tx_fifo_readable = 1'd0;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_we;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_writable;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_re;
+wire soc_litedramcore_uart_tx_fifo_syncfifo_readable;
+wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din;
+wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0;
+reg soc_litedramcore_uart_tx_fifo_replace = 1'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0;
+reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0;
+wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r;
+wire soc_litedramcore_uart_tx_fifo_wrport_we;
+wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w;
+wire soc_litedramcore_uart_tx_fifo_do_read;
+wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr;
+wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r;
+wire soc_litedramcore_uart_tx_fifo_rdport_re;
+wire [4:0] soc_litedramcore_uart_tx_fifo_level1;
+wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data;
+wire soc_litedramcore_uart_tx_fifo_fifo_in_first;
+wire soc_litedramcore_uart_tx_fifo_fifo_in_last;
+wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
+wire soc_litedramcore_uart_tx_fifo_fifo_out_first;
+wire soc_litedramcore_uart_tx_fifo_fifo_out_last;
+wire soc_litedramcore_uart_rx_fifo_sink_valid;
+wire soc_litedramcore_uart_rx_fifo_sink_ready;
+wire soc_litedramcore_uart_rx_fifo_sink_first;
+wire soc_litedramcore_uart_rx_fifo_sink_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data;
+wire soc_litedramcore_uart_rx_fifo_source_valid;
+wire soc_litedramcore_uart_rx_fifo_source_ready;
+wire soc_litedramcore_uart_rx_fifo_source_first;
+wire soc_litedramcore_uart_rx_fifo_source_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data;
+wire soc_litedramcore_uart_rx_fifo_re;
+reg soc_litedramcore_uart_rx_fifo_readable = 1'd0;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_we;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_writable;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_re;
+wire soc_litedramcore_uart_rx_fifo_syncfifo_readable;
+wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din;
+wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0;
+reg soc_litedramcore_uart_rx_fifo_replace = 1'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0;
+reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0;
+wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r;
+wire soc_litedramcore_uart_rx_fifo_wrport_we;
+wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w;
+wire soc_litedramcore_uart_rx_fifo_do_read;
+wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr;
+wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r;
+wire soc_litedramcore_uart_rx_fifo_rdport_re;
+wire [4:0] soc_litedramcore_uart_rx_fifo_level1;
+wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data;
+wire soc_litedramcore_uart_rx_fifo_fifo_in_first;
+wire soc_litedramcore_uart_rx_fifo_fifo_in_last;
+wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
+wire soc_litedramcore_uart_rx_fifo_fifo_out_first;
+wire soc_litedramcore_uart_rx_fifo_fifo_out_last;
+reg soc_litedramcore_uart_reset = 1'd0;
+reg [31:0] soc_litedramcore_timer_load_storage = 32'd0;
+reg soc_litedramcore_timer_load_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0;
+reg soc_litedramcore_timer_reload_re = 1'd0;
+reg soc_litedramcore_timer_en_storage = 1'd0;
+reg soc_litedramcore_timer_en_re = 1'd0;
+reg soc_litedramcore_timer_update_value_storage = 1'd0;
+reg soc_litedramcore_timer_update_value_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_value_status = 32'd0;
+wire soc_litedramcore_timer_value_we;
+wire soc_litedramcore_timer_irq;
+wire soc_litedramcore_timer_zero_status;
+reg soc_litedramcore_timer_zero_pending = 1'd0;
+wire soc_litedramcore_timer_zero_trigger;
+reg soc_litedramcore_timer_zero_clear = 1'd0;
+reg soc_litedramcore_timer_zero_old_trigger = 1'd0;
+wire soc_litedramcore_timer_eventmanager_status_re;
+wire soc_litedramcore_timer_eventmanager_status_r;
+wire soc_litedramcore_timer_eventmanager_status_we;
+wire soc_litedramcore_timer_eventmanager_status_w;
+wire soc_litedramcore_timer_eventmanager_pending_re;
+wire soc_litedramcore_timer_eventmanager_pending_r;
+wire soc_litedramcore_timer_eventmanager_pending_we;
+wire soc_litedramcore_timer_eventmanager_pending_w;
+reg soc_litedramcore_timer_eventmanager_storage = 1'd0;
+reg soc_litedramcore_timer_eventmanager_re = 1'd0;
+reg [31:0] soc_litedramcore_timer_value = 32'd0;
+reg [13:0] soc_litedramcore_interface_adr = 14'd0;
+reg soc_litedramcore_interface_we = 1'd0;
+wire [7:0] soc_litedramcore_interface_dat_w;
+wire [7:0] soc_litedramcore_interface_dat_r;
+wire [29:0] soc_litedramcore_bus_wishbone_adr;
+wire [31:0] soc_litedramcore_bus_wishbone_dat_w;
+wire [31:0] soc_litedramcore_bus_wishbone_dat_r;
+wire [3:0] soc_litedramcore_bus_wishbone_sel;
+wire soc_litedramcore_bus_wishbone_cyc;
+wire soc_litedramcore_bus_wishbone_stb;
+reg soc_litedramcore_bus_wishbone_ack = 1'd0;
+wire soc_litedramcore_bus_wishbone_we;
+wire [2:0] soc_litedramcore_bus_wishbone_cti;
+wire [1:0] soc_litedramcore_bus_wishbone_bte;
+reg soc_litedramcore_bus_wishbone_err = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire soc_sys_pll_reset;
+wire soc_sys_pll_locked;
+wire soc_s7pll0_clkin;
+wire soc_s7pll0_clkout0;
+wire soc_s7pll0_clkout_buf0;
+wire soc_s7pll0_clkout1;
+wire soc_s7pll0_clkout_buf1;
+wire soc_s7pll0_clkout2;
+wire soc_s7pll0_clkout_buf2;
+wire soc_iodelay_pll_reset;
+wire soc_iodelay_pll_locked;
+wire soc_s7pll1_clkin;
+wire soc_s7pll1_clkout;
+wire soc_s7pll1_clkout_buf;
+reg [3:0] soc_reset_counter = 4'd15;
+reg soc_ic_reset = 1'd1;
+reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
+reg soc_a7ddrphy_wlevel_en_re = 1'd0;
+wire soc_a7ddrphy_wlevel_strobe_re;
+wire soc_a7ddrphy_wlevel_strobe_r;
+wire soc_a7ddrphy_wlevel_strobe_we;
+reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
+wire soc_a7ddrphy_cdly_rst_re;
+wire soc_a7ddrphy_cdly_rst_r;
+wire soc_a7ddrphy_cdly_rst_we;
+reg soc_a7ddrphy_cdly_rst_w = 1'd0;
+wire soc_a7ddrphy_cdly_inc_re;
+wire soc_a7ddrphy_cdly_inc_r;
+wire soc_a7ddrphy_cdly_inc_we;
+reg soc_a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
+reg soc_a7ddrphy_dly_sel_re = 1'd0;
+wire soc_a7ddrphy_rdly_dq_rst_re;
+wire soc_a7ddrphy_rdly_dq_rst_r;
+wire soc_a7ddrphy_rdly_dq_rst_we;
+reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_inc_re;
+wire soc_a7ddrphy_rdly_dq_inc_r;
+wire soc_a7ddrphy_rdly_dq_inc_we;
+reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire soc_a7ddrphy_rdly_dq_bitslip_re;
+wire soc_a7ddrphy_rdly_dq_bitslip_r;
+wire soc_a7ddrphy_rdly_dq_bitslip_we;
+reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p0_address;
+wire [2:0] soc_a7ddrphy_dfi_p0_bank;
+wire soc_a7ddrphy_dfi_p0_cas_n;
+wire soc_a7ddrphy_dfi_p0_cs_n;
+wire soc_a7ddrphy_dfi_p0_ras_n;
+wire soc_a7ddrphy_dfi_p0_we_n;
+wire soc_a7ddrphy_dfi_p0_cke;
+wire soc_a7ddrphy_dfi_p0_odt;
+wire soc_a7ddrphy_dfi_p0_reset_n;
+wire soc_a7ddrphy_dfi_p0_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
+wire soc_a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
+wire soc_a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p1_address;
+wire [2:0] soc_a7ddrphy_dfi_p1_bank;
+wire soc_a7ddrphy_dfi_p1_cas_n;
+wire soc_a7ddrphy_dfi_p1_cs_n;
+wire soc_a7ddrphy_dfi_p1_ras_n;
+wire soc_a7ddrphy_dfi_p1_we_n;
+wire soc_a7ddrphy_dfi_p1_cke;
+wire soc_a7ddrphy_dfi_p1_odt;
+wire soc_a7ddrphy_dfi_p1_reset_n;
+wire soc_a7ddrphy_dfi_p1_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
+wire soc_a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
+wire soc_a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p2_address;
+wire [2:0] soc_a7ddrphy_dfi_p2_bank;
+wire soc_a7ddrphy_dfi_p2_cas_n;
+wire soc_a7ddrphy_dfi_p2_cs_n;
+wire soc_a7ddrphy_dfi_p2_ras_n;
+wire soc_a7ddrphy_dfi_p2_we_n;
+wire soc_a7ddrphy_dfi_p2_cke;
+wire soc_a7ddrphy_dfi_p2_odt;
+wire soc_a7ddrphy_dfi_p2_reset_n;
+wire soc_a7ddrphy_dfi_p2_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
+wire soc_a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
+wire soc_a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] soc_a7ddrphy_dfi_p3_address;
+wire [2:0] soc_a7ddrphy_dfi_p3_bank;
+wire soc_a7ddrphy_dfi_p3_cas_n;
+wire soc_a7ddrphy_dfi_p3_cs_n;
+wire soc_a7ddrphy_dfi_p3_ras_n;
+wire soc_a7ddrphy_dfi_p3_we_n;
+wire soc_a7ddrphy_dfi_p3_cke;
+wire soc_a7ddrphy_dfi_p3_odt;
+wire soc_a7ddrphy_dfi_p3_reset_n;
+wire soc_a7ddrphy_dfi_p3_act_n;
+wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
+wire soc_a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
+wire soc_a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
+reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire soc_a7ddrphy_sd_clk_se_nodelay;
+reg soc_a7ddrphy_dqs_oe = 1'd0;
+reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dqspattern0;
+wire soc_a7ddrphy_dqspattern1;
+reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] soc_a7ddrphy_dqs_i;
+wire [1:0] soc_a7ddrphy_dqs_i_delayed;
+wire soc_a7ddrphy_dqs_o_no_delay0;
+wire soc_a7ddrphy_dqs_t0;
+wire soc_a7ddrphy0;
+wire soc_a7ddrphy_dqs_o_no_delay1;
+wire soc_a7ddrphy_dqs_t1;
+wire soc_a7ddrphy1;
+wire soc_a7ddrphy_dq_oe;
+reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
+wire soc_a7ddrphy_dq_o_nodelay0;
+wire soc_a7ddrphy_dq_i_nodelay0;
+wire soc_a7ddrphy_dq_i_delayed0;
+wire soc_a7ddrphy_dq_t0;
+wire [7:0] soc_a7ddrphy_dq_i_data0;
+wire [7:0] soc_a7ddrphy_bitslip0_i;
+reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay1;
+wire soc_a7ddrphy_dq_i_nodelay1;
+wire soc_a7ddrphy_dq_i_delayed1;
+wire soc_a7ddrphy_dq_t1;
+wire [7:0] soc_a7ddrphy_dq_i_data1;
+wire [7:0] soc_a7ddrphy_bitslip1_i;
+reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay2;
+wire soc_a7ddrphy_dq_i_nodelay2;
+wire soc_a7ddrphy_dq_i_delayed2;
+wire soc_a7ddrphy_dq_t2;
+wire [7:0] soc_a7ddrphy_dq_i_data2;
+wire [7:0] soc_a7ddrphy_bitslip2_i;
+reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay3;
+wire soc_a7ddrphy_dq_i_nodelay3;
+wire soc_a7ddrphy_dq_i_delayed3;
+wire soc_a7ddrphy_dq_t3;
+wire [7:0] soc_a7ddrphy_dq_i_data3;
+wire [7:0] soc_a7ddrphy_bitslip3_i;
+reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay4;
+wire soc_a7ddrphy_dq_i_nodelay4;
+wire soc_a7ddrphy_dq_i_delayed4;
+wire soc_a7ddrphy_dq_t4;
+wire [7:0] soc_a7ddrphy_dq_i_data4;
+wire [7:0] soc_a7ddrphy_bitslip4_i;
+reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay5;
+wire soc_a7ddrphy_dq_i_nodelay5;
+wire soc_a7ddrphy_dq_i_delayed5;
+wire soc_a7ddrphy_dq_t5;
+wire [7:0] soc_a7ddrphy_dq_i_data5;
+wire [7:0] soc_a7ddrphy_bitslip5_i;
+reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay6;
+wire soc_a7ddrphy_dq_i_nodelay6;
+wire soc_a7ddrphy_dq_i_delayed6;
+wire soc_a7ddrphy_dq_t6;
+wire [7:0] soc_a7ddrphy_dq_i_data6;
+wire [7:0] soc_a7ddrphy_bitslip6_i;
+reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay7;
+wire soc_a7ddrphy_dq_i_nodelay7;
+wire soc_a7ddrphy_dq_i_delayed7;
+wire soc_a7ddrphy_dq_t7;
+wire [7:0] soc_a7ddrphy_dq_i_data7;
+wire [7:0] soc_a7ddrphy_bitslip7_i;
+reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay8;
+wire soc_a7ddrphy_dq_i_nodelay8;
+wire soc_a7ddrphy_dq_i_delayed8;
+wire soc_a7ddrphy_dq_t8;
+wire [7:0] soc_a7ddrphy_dq_i_data8;
+wire [7:0] soc_a7ddrphy_bitslip8_i;
+reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay9;
+wire soc_a7ddrphy_dq_i_nodelay9;
+wire soc_a7ddrphy_dq_i_delayed9;
+wire soc_a7ddrphy_dq_t9;
+wire [7:0] soc_a7ddrphy_dq_i_data9;
+wire [7:0] soc_a7ddrphy_bitslip9_i;
+reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay10;
+wire soc_a7ddrphy_dq_i_nodelay10;
+wire soc_a7ddrphy_dq_i_delayed10;
+wire soc_a7ddrphy_dq_t10;
+wire [7:0] soc_a7ddrphy_dq_i_data10;
+wire [7:0] soc_a7ddrphy_bitslip10_i;
+reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay11;
+wire soc_a7ddrphy_dq_i_nodelay11;
+wire soc_a7ddrphy_dq_i_delayed11;
+wire soc_a7ddrphy_dq_t11;
+wire [7:0] soc_a7ddrphy_dq_i_data11;
+wire [7:0] soc_a7ddrphy_bitslip11_i;
+reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay12;
+wire soc_a7ddrphy_dq_i_nodelay12;
+wire soc_a7ddrphy_dq_i_delayed12;
+wire soc_a7ddrphy_dq_t12;
+wire [7:0] soc_a7ddrphy_dq_i_data12;
+wire [7:0] soc_a7ddrphy_bitslip12_i;
+reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay13;
+wire soc_a7ddrphy_dq_i_nodelay13;
+wire soc_a7ddrphy_dq_i_delayed13;
+wire soc_a7ddrphy_dq_t13;
+wire [7:0] soc_a7ddrphy_dq_i_data13;
+wire [7:0] soc_a7ddrphy_bitslip13_i;
+reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay14;
+wire soc_a7ddrphy_dq_i_nodelay14;
+wire soc_a7ddrphy_dq_i_delayed14;
+wire soc_a7ddrphy_dq_t14;
+wire [7:0] soc_a7ddrphy_dq_i_data14;
+wire [7:0] soc_a7ddrphy_bitslip14_i;
+reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
+wire soc_a7ddrphy_dq_o_nodelay15;
+wire soc_a7ddrphy_dq_i_nodelay15;
+wire soc_a7ddrphy_dq_i_delayed15;
+wire soc_a7ddrphy_dq_t15;
+wire [7:0] soc_a7ddrphy_dq_i_data15;
+wire [7:0] soc_a7ddrphy_bitslip15_i;
+reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
+reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
+reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
+wire [7:0] soc_a7ddrphy_rddata_en;
+reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] soc_a7ddrphy_wrdata_en;
+reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
+wire [14:0] soc_sdram_inti_p0_address;
+wire [2:0] soc_sdram_inti_p0_bank;
+reg soc_sdram_inti_p0_cas_n = 1'd1;
+reg soc_sdram_inti_p0_cs_n = 1'd1;
+reg soc_sdram_inti_p0_ras_n = 1'd1;
+reg soc_sdram_inti_p0_we_n = 1'd1;
+wire soc_sdram_inti_p0_cke;
+wire soc_sdram_inti_p0_odt;
+wire soc_sdram_inti_p0_reset_n;
+reg soc_sdram_inti_p0_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p0_wrdata;
+wire soc_sdram_inti_p0_wrdata_en;
+wire [3:0] soc_sdram_inti_p0_wrdata_mask;
+wire soc_sdram_inti_p0_rddata_en;
+reg [31:0] soc_sdram_inti_p0_rddata = 32'd0;
+reg soc_sdram_inti_p0_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_inti_p1_address;
+wire [2:0] soc_sdram_inti_p1_bank;
+reg soc_sdram_inti_p1_cas_n = 1'd1;
+reg soc_sdram_inti_p1_cs_n = 1'd1;
+reg soc_sdram_inti_p1_ras_n = 1'd1;
+reg soc_sdram_inti_p1_we_n = 1'd1;
+wire soc_sdram_inti_p1_cke;
+wire soc_sdram_inti_p1_odt;
+wire soc_sdram_inti_p1_reset_n;
+reg soc_sdram_inti_p1_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p1_wrdata;
+wire soc_sdram_inti_p1_wrdata_en;
+wire [3:0] soc_sdram_inti_p1_wrdata_mask;
+wire soc_sdram_inti_p1_rddata_en;
+reg [31:0] soc_sdram_inti_p1_rddata = 32'd0;
+reg soc_sdram_inti_p1_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_inti_p2_address;
+wire [2:0] soc_sdram_inti_p2_bank;
+reg soc_sdram_inti_p2_cas_n = 1'd1;
+reg soc_sdram_inti_p2_cs_n = 1'd1;
+reg soc_sdram_inti_p2_ras_n = 1'd1;
+reg soc_sdram_inti_p2_we_n = 1'd1;
+wire soc_sdram_inti_p2_cke;
+wire soc_sdram_inti_p2_odt;
+wire soc_sdram_inti_p2_reset_n;
+reg soc_sdram_inti_p2_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p2_wrdata;
+wire soc_sdram_inti_p2_wrdata_en;
+wire [3:0] soc_sdram_inti_p2_wrdata_mask;
+wire soc_sdram_inti_p2_rddata_en;
+reg [31:0] soc_sdram_inti_p2_rddata = 32'd0;
+reg soc_sdram_inti_p2_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_inti_p3_address;
+wire [2:0] soc_sdram_inti_p3_bank;
+reg soc_sdram_inti_p3_cas_n = 1'd1;
+reg soc_sdram_inti_p3_cs_n = 1'd1;
+reg soc_sdram_inti_p3_ras_n = 1'd1;
+reg soc_sdram_inti_p3_we_n = 1'd1;
+wire soc_sdram_inti_p3_cke;
+wire soc_sdram_inti_p3_odt;
+wire soc_sdram_inti_p3_reset_n;
+reg soc_sdram_inti_p3_act_n = 1'd1;
+wire [31:0] soc_sdram_inti_p3_wrdata;
+wire soc_sdram_inti_p3_wrdata_en;
+wire [3:0] soc_sdram_inti_p3_wrdata_mask;
+wire soc_sdram_inti_p3_rddata_en;
+reg [31:0] soc_sdram_inti_p3_rddata = 32'd0;
+reg soc_sdram_inti_p3_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_slave_p0_address;
+wire [2:0] soc_sdram_slave_p0_bank;
+wire soc_sdram_slave_p0_cas_n;
+wire soc_sdram_slave_p0_cs_n;
+wire soc_sdram_slave_p0_ras_n;
+wire soc_sdram_slave_p0_we_n;
+wire soc_sdram_slave_p0_cke;
+wire soc_sdram_slave_p0_odt;
+wire soc_sdram_slave_p0_reset_n;
+wire soc_sdram_slave_p0_act_n;
+wire [31:0] soc_sdram_slave_p0_wrdata;
+wire soc_sdram_slave_p0_wrdata_en;
+wire [3:0] soc_sdram_slave_p0_wrdata_mask;
+wire soc_sdram_slave_p0_rddata_en;
+reg [31:0] soc_sdram_slave_p0_rddata = 32'd0;
+reg soc_sdram_slave_p0_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_slave_p1_address;
+wire [2:0] soc_sdram_slave_p1_bank;
+wire soc_sdram_slave_p1_cas_n;
+wire soc_sdram_slave_p1_cs_n;
+wire soc_sdram_slave_p1_ras_n;
+wire soc_sdram_slave_p1_we_n;
+wire soc_sdram_slave_p1_cke;
+wire soc_sdram_slave_p1_odt;
+wire soc_sdram_slave_p1_reset_n;
+wire soc_sdram_slave_p1_act_n;
+wire [31:0] soc_sdram_slave_p1_wrdata;
+wire soc_sdram_slave_p1_wrdata_en;
+wire [3:0] soc_sdram_slave_p1_wrdata_mask;
+wire soc_sdram_slave_p1_rddata_en;
+reg [31:0] soc_sdram_slave_p1_rddata = 32'd0;
+reg soc_sdram_slave_p1_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_slave_p2_address;
+wire [2:0] soc_sdram_slave_p2_bank;
+wire soc_sdram_slave_p2_cas_n;
+wire soc_sdram_slave_p2_cs_n;
+wire soc_sdram_slave_p2_ras_n;
+wire soc_sdram_slave_p2_we_n;
+wire soc_sdram_slave_p2_cke;
+wire soc_sdram_slave_p2_odt;
+wire soc_sdram_slave_p2_reset_n;
+wire soc_sdram_slave_p2_act_n;
+wire [31:0] soc_sdram_slave_p2_wrdata;
+wire soc_sdram_slave_p2_wrdata_en;
+wire [3:0] soc_sdram_slave_p2_wrdata_mask;
+wire soc_sdram_slave_p2_rddata_en;
+reg [31:0] soc_sdram_slave_p2_rddata = 32'd0;
+reg soc_sdram_slave_p2_rddata_valid = 1'd0;
+wire [14:0] soc_sdram_slave_p3_address;
+wire [2:0] soc_sdram_slave_p3_bank;
+wire soc_sdram_slave_p3_cas_n;
+wire soc_sdram_slave_p3_cs_n;
+wire soc_sdram_slave_p3_ras_n;
+wire soc_sdram_slave_p3_we_n;
+wire soc_sdram_slave_p3_cke;
+wire soc_sdram_slave_p3_odt;
+wire soc_sdram_slave_p3_reset_n;
+wire soc_sdram_slave_p3_act_n;
+wire [31:0] soc_sdram_slave_p3_wrdata;
+wire soc_sdram_slave_p3_wrdata_en;
+wire [3:0] soc_sdram_slave_p3_wrdata_mask;
+wire soc_sdram_slave_p3_rddata_en;
+reg [31:0] soc_sdram_slave_p3_rddata = 32'd0;
+reg soc_sdram_slave_p3_rddata_valid = 1'd0;
+reg [14:0] soc_sdram_master_p0_address = 15'd0;
+reg [2:0] soc_sdram_master_p0_bank = 3'd0;
+reg soc_sdram_master_p0_cas_n = 1'd1;
+reg soc_sdram_master_p0_cs_n = 1'd1;
+reg soc_sdram_master_p0_ras_n = 1'd1;
+reg soc_sdram_master_p0_we_n = 1'd1;
+reg soc_sdram_master_p0_cke = 1'd0;
+reg soc_sdram_master_p0_odt = 1'd0;
+reg soc_sdram_master_p0_reset_n = 1'd0;
+reg soc_sdram_master_p0_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p0_wrdata = 32'd0;
+reg soc_sdram_master_p0_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0;
+reg soc_sdram_master_p0_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p0_rddata;
+wire soc_sdram_master_p0_rddata_valid;
+reg [14:0] soc_sdram_master_p1_address = 15'd0;
+reg [2:0] soc_sdram_master_p1_bank = 3'd0;
+reg soc_sdram_master_p1_cas_n = 1'd1;
+reg soc_sdram_master_p1_cs_n = 1'd1;
+reg soc_sdram_master_p1_ras_n = 1'd1;
+reg soc_sdram_master_p1_we_n = 1'd1;
+reg soc_sdram_master_p1_cke = 1'd0;
+reg soc_sdram_master_p1_odt = 1'd0;
+reg soc_sdram_master_p1_reset_n = 1'd0;
+reg soc_sdram_master_p1_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p1_wrdata = 32'd0;
+reg soc_sdram_master_p1_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0;
+reg soc_sdram_master_p1_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p1_rddata;
+wire soc_sdram_master_p1_rddata_valid;
+reg [14:0] soc_sdram_master_p2_address = 15'd0;
+reg [2:0] soc_sdram_master_p2_bank = 3'd0;
+reg soc_sdram_master_p2_cas_n = 1'd1;
+reg soc_sdram_master_p2_cs_n = 1'd1;
+reg soc_sdram_master_p2_ras_n = 1'd1;
+reg soc_sdram_master_p2_we_n = 1'd1;
+reg soc_sdram_master_p2_cke = 1'd0;
+reg soc_sdram_master_p2_odt = 1'd0;
+reg soc_sdram_master_p2_reset_n = 1'd0;
+reg soc_sdram_master_p2_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p2_wrdata = 32'd0;
+reg soc_sdram_master_p2_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0;
+reg soc_sdram_master_p2_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p2_rddata;
+wire soc_sdram_master_p2_rddata_valid;
+reg [14:0] soc_sdram_master_p3_address = 15'd0;
+reg [2:0] soc_sdram_master_p3_bank = 3'd0;
+reg soc_sdram_master_p3_cas_n = 1'd1;
+reg soc_sdram_master_p3_cs_n = 1'd1;
+reg soc_sdram_master_p3_ras_n = 1'd1;
+reg soc_sdram_master_p3_we_n = 1'd1;
+reg soc_sdram_master_p3_cke = 1'd0;
+reg soc_sdram_master_p3_odt = 1'd0;
+reg soc_sdram_master_p3_reset_n = 1'd0;
+reg soc_sdram_master_p3_act_n = 1'd1;
+reg [31:0] soc_sdram_master_p3_wrdata = 32'd0;
+reg soc_sdram_master_p3_wrdata_en = 1'd0;
+reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0;
+reg soc_sdram_master_p3_rddata_en = 1'd0;
+wire [31:0] soc_sdram_master_p3_rddata;
+wire soc_sdram_master_p3_rddata_valid;
+reg [3:0] soc_sdram_storage = 4'd0;
+reg soc_sdram_re = 1'd0;
+reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0;
+reg soc_sdram_phaseinjector0_command_re = 1'd0;
+wire soc_sdram_phaseinjector0_command_issue_re;
+wire soc_sdram_phaseinjector0_command_issue_r;
+wire soc_sdram_phaseinjector0_command_issue_we;
+reg soc_sdram_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] soc_sdram_phaseinjector0_address_storage = 15'd0;
+reg soc_sdram_phaseinjector0_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector0_status = 32'd0;
+wire soc_sdram_phaseinjector0_we;
+reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0;
+reg soc_sdram_phaseinjector1_command_re = 1'd0;
+wire soc_sdram_phaseinjector1_command_issue_re;
+wire soc_sdram_phaseinjector1_command_issue_r;
+wire soc_sdram_phaseinjector1_command_issue_we;
+reg soc_sdram_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] soc_sdram_phaseinjector1_address_storage = 15'd0;
+reg soc_sdram_phaseinjector1_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector1_status = 32'd0;
+wire soc_sdram_phaseinjector1_we;
+reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0;
+reg soc_sdram_phaseinjector2_command_re = 1'd0;
+wire soc_sdram_phaseinjector2_command_issue_re;
+wire soc_sdram_phaseinjector2_command_issue_r;
+wire soc_sdram_phaseinjector2_command_issue_we;
+reg soc_sdram_phaseinjector2_command_issue_w = 1'd0;
+reg [14:0] soc_sdram_phaseinjector2_address_storage = 15'd0;
+reg soc_sdram_phaseinjector2_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector2_status = 32'd0;
+wire soc_sdram_phaseinjector2_we;
+reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0;
+reg soc_sdram_phaseinjector3_command_re = 1'd0;
+wire soc_sdram_phaseinjector3_command_issue_re;
+wire soc_sdram_phaseinjector3_command_issue_r;
+wire soc_sdram_phaseinjector3_command_issue_we;
+reg soc_sdram_phaseinjector3_command_issue_w = 1'd0;
+reg [14:0] soc_sdram_phaseinjector3_address_storage = 15'd0;
+reg soc_sdram_phaseinjector3_address_re = 1'd0;
+reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0;
+reg soc_sdram_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0;
+reg soc_sdram_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] soc_sdram_phaseinjector3_status = 32'd0;
+wire soc_sdram_phaseinjector3_we;
+wire soc_sdram_interface_bank0_valid;
+wire soc_sdram_interface_bank0_ready;
+wire soc_sdram_interface_bank0_we;
+wire [21:0] soc_sdram_interface_bank0_addr;
+wire soc_sdram_interface_bank0_lock;
+wire soc_sdram_interface_bank0_wdata_ready;
+wire soc_sdram_interface_bank0_rdata_valid;
+wire soc_sdram_interface_bank1_valid;
+wire soc_sdram_interface_bank1_ready;
+wire soc_sdram_interface_bank1_we;
+wire [21:0] soc_sdram_interface_bank1_addr;
+wire soc_sdram_interface_bank1_lock;
+wire soc_sdram_interface_bank1_wdata_ready;
+wire soc_sdram_interface_bank1_rdata_valid;
+wire soc_sdram_interface_bank2_valid;
+wire soc_sdram_interface_bank2_ready;
+wire soc_sdram_interface_bank2_we;
+wire [21:0] soc_sdram_interface_bank2_addr;
+wire soc_sdram_interface_bank2_lock;
+wire soc_sdram_interface_bank2_wdata_ready;
+wire soc_sdram_interface_bank2_rdata_valid;
+wire soc_sdram_interface_bank3_valid;
+wire soc_sdram_interface_bank3_ready;
+wire soc_sdram_interface_bank3_we;
+wire [21:0] soc_sdram_interface_bank3_addr;
+wire soc_sdram_interface_bank3_lock;
+wire soc_sdram_interface_bank3_wdata_ready;
+wire soc_sdram_interface_bank3_rdata_valid;
+wire soc_sdram_interface_bank4_valid;
+wire soc_sdram_interface_bank4_ready;
+wire soc_sdram_interface_bank4_we;
+wire [21:0] soc_sdram_interface_bank4_addr;
+wire soc_sdram_interface_bank4_lock;
+wire soc_sdram_interface_bank4_wdata_ready;
+wire soc_sdram_interface_bank4_rdata_valid;
+wire soc_sdram_interface_bank5_valid;
+wire soc_sdram_interface_bank5_ready;
+wire soc_sdram_interface_bank5_we;
+wire [21:0] soc_sdram_interface_bank5_addr;
+wire soc_sdram_interface_bank5_lock;
+wire soc_sdram_interface_bank5_wdata_ready;
+wire soc_sdram_interface_bank5_rdata_valid;
+wire soc_sdram_interface_bank6_valid;
+wire soc_sdram_interface_bank6_ready;
+wire soc_sdram_interface_bank6_we;
+wire [21:0] soc_sdram_interface_bank6_addr;
+wire soc_sdram_interface_bank6_lock;
+wire soc_sdram_interface_bank6_wdata_ready;
+wire soc_sdram_interface_bank6_rdata_valid;
+wire soc_sdram_interface_bank7_valid;
+wire soc_sdram_interface_bank7_ready;
+wire soc_sdram_interface_bank7_we;
+wire [21:0] soc_sdram_interface_bank7_addr;
+wire soc_sdram_interface_bank7_lock;
+wire soc_sdram_interface_bank7_wdata_ready;
+wire soc_sdram_interface_bank7_rdata_valid;
+reg [127:0] soc_sdram_interface_wdata = 128'd0;
+reg [15:0] soc_sdram_interface_wdata_we = 16'd0;
+wire [127:0] soc_sdram_interface_rdata;
+reg [14:0] soc_sdram_dfi_p0_address = 15'd0;
+reg [2:0] soc_sdram_dfi_p0_bank = 3'd0;
+reg soc_sdram_dfi_p0_cas_n = 1'd1;
+reg soc_sdram_dfi_p0_cs_n = 1'd1;
+reg soc_sdram_dfi_p0_ras_n = 1'd1;
+reg soc_sdram_dfi_p0_we_n = 1'd1;
+wire soc_sdram_dfi_p0_cke;
+wire soc_sdram_dfi_p0_odt;
+wire soc_sdram_dfi_p0_reset_n;
+reg soc_sdram_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p0_wrdata;
+reg soc_sdram_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p0_wrdata_mask;
+reg soc_sdram_dfi_p0_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p0_rddata;
+wire soc_sdram_dfi_p0_rddata_valid;
+reg [14:0] soc_sdram_dfi_p1_address = 15'd0;
+reg [2:0] soc_sdram_dfi_p1_bank = 3'd0;
+reg soc_sdram_dfi_p1_cas_n = 1'd1;
+reg soc_sdram_dfi_p1_cs_n = 1'd1;
+reg soc_sdram_dfi_p1_ras_n = 1'd1;
+reg soc_sdram_dfi_p1_we_n = 1'd1;
+wire soc_sdram_dfi_p1_cke;
+wire soc_sdram_dfi_p1_odt;
+wire soc_sdram_dfi_p1_reset_n;
+reg soc_sdram_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p1_wrdata;
+reg soc_sdram_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p1_wrdata_mask;
+reg soc_sdram_dfi_p1_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p1_rddata;
+wire soc_sdram_dfi_p1_rddata_valid;
+reg [14:0] soc_sdram_dfi_p2_address = 15'd0;
+reg [2:0] soc_sdram_dfi_p2_bank = 3'd0;
+reg soc_sdram_dfi_p2_cas_n = 1'd1;
+reg soc_sdram_dfi_p2_cs_n = 1'd1;
+reg soc_sdram_dfi_p2_ras_n = 1'd1;
+reg soc_sdram_dfi_p2_we_n = 1'd1;
+wire soc_sdram_dfi_p2_cke;
+wire soc_sdram_dfi_p2_odt;
+wire soc_sdram_dfi_p2_reset_n;
+reg soc_sdram_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p2_wrdata;
+reg soc_sdram_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p2_wrdata_mask;
+reg soc_sdram_dfi_p2_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p2_rddata;
+wire soc_sdram_dfi_p2_rddata_valid;
+reg [14:0] soc_sdram_dfi_p3_address = 15'd0;
+reg [2:0] soc_sdram_dfi_p3_bank = 3'd0;
+reg soc_sdram_dfi_p3_cas_n = 1'd1;
+reg soc_sdram_dfi_p3_cs_n = 1'd1;
+reg soc_sdram_dfi_p3_ras_n = 1'd1;
+reg soc_sdram_dfi_p3_we_n = 1'd1;
+wire soc_sdram_dfi_p3_cke;
+wire soc_sdram_dfi_p3_odt;
+wire soc_sdram_dfi_p3_reset_n;
+reg soc_sdram_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_sdram_dfi_p3_wrdata;
+reg soc_sdram_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] soc_sdram_dfi_p3_wrdata_mask;
+reg soc_sdram_dfi_p3_rddata_en = 1'd0;
+wire [31:0] soc_sdram_dfi_p3_rddata;
+wire soc_sdram_dfi_p3_rddata_valid;
+reg soc_sdram_cmd_valid = 1'd0;
+reg soc_sdram_cmd_ready = 1'd0;
+reg soc_sdram_cmd_last = 1'd0;
+reg [14:0] soc_sdram_cmd_payload_a = 15'd0;
+reg [2:0] soc_sdram_cmd_payload_ba = 3'd0;
+reg soc_sdram_cmd_payload_cas = 1'd0;
+reg soc_sdram_cmd_payload_ras = 1'd0;
+reg soc_sdram_cmd_payload_we = 1'd0;
+reg soc_sdram_cmd_payload_is_read = 1'd0;
+reg soc_sdram_cmd_payload_is_write = 1'd0;
+wire soc_sdram_wants_refresh;
+wire soc_sdram_wants_zqcs;
+wire soc_sdram_timer_wait;
+wire soc_sdram_timer_done0;
+wire [9:0] soc_sdram_timer_count0;
+wire soc_sdram_timer_done1;
+reg [9:0] soc_sdram_timer_count1 = 10'd781;
+wire soc_sdram_postponer_req_i;
+reg soc_sdram_postponer_req_o = 1'd0;
+reg soc_sdram_postponer_count = 1'd0;
+reg soc_sdram_sequencer_start0 = 1'd0;
+wire soc_sdram_sequencer_done0;
+wire soc_sdram_sequencer_start1;
+reg soc_sdram_sequencer_done1 = 1'd0;
+reg [5:0] soc_sdram_sequencer_counter = 6'd0;
+reg soc_sdram_sequencer_count = 1'd0;
+wire soc_sdram_zqcs_timer_wait;
+wire soc_sdram_zqcs_timer_done0;
+wire [26:0] soc_sdram_zqcs_timer_count0;
+wire soc_sdram_zqcs_timer_done1;
+reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999;
+reg soc_sdram_zqcs_executer_start = 1'd0;
+reg soc_sdram_zqcs_executer_done = 1'd0;
+reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0;
+wire soc_sdram_bankmachine0_req_valid;
+wire soc_sdram_bankmachine0_req_ready;
+wire soc_sdram_bankmachine0_req_we;
+wire [21:0] soc_sdram_bankmachine0_req_addr;
+wire soc_sdram_bankmachine0_req_lock;
+reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine0_refresh_req;
+reg soc_sdram_bankmachine0_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine0_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba;
+reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine0_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine0_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine0_row = 15'd0;
+reg soc_sdram_bankmachine0_row_opened = 1'd0;
+wire soc_sdram_bankmachine0_row_hit;
+reg soc_sdram_bankmachine0_row_open = 1'd0;
+reg soc_sdram_bankmachine0_row_close = 1'd0;
+reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0;
+wire soc_sdram_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0;
+wire soc_sdram_bankmachine1_req_valid;
+wire soc_sdram_bankmachine1_req_ready;
+wire soc_sdram_bankmachine1_req_we;
+wire [21:0] soc_sdram_bankmachine1_req_addr;
+wire soc_sdram_bankmachine1_req_lock;
+reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine1_refresh_req;
+reg soc_sdram_bankmachine1_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine1_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba;
+reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine1_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine1_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine1_row = 15'd0;
+reg soc_sdram_bankmachine1_row_opened = 1'd0;
+wire soc_sdram_bankmachine1_row_hit;
+reg soc_sdram_bankmachine1_row_open = 1'd0;
+reg soc_sdram_bankmachine1_row_close = 1'd0;
+reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0;
+wire soc_sdram_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0;
+wire soc_sdram_bankmachine2_req_valid;
+wire soc_sdram_bankmachine2_req_ready;
+wire soc_sdram_bankmachine2_req_we;
+wire [21:0] soc_sdram_bankmachine2_req_addr;
+wire soc_sdram_bankmachine2_req_lock;
+reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine2_refresh_req;
+reg soc_sdram_bankmachine2_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine2_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba;
+reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine2_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine2_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine2_row = 15'd0;
+reg soc_sdram_bankmachine2_row_opened = 1'd0;
+wire soc_sdram_bankmachine2_row_hit;
+reg soc_sdram_bankmachine2_row_open = 1'd0;
+reg soc_sdram_bankmachine2_row_close = 1'd0;
+reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0;
+wire soc_sdram_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0;
+wire soc_sdram_bankmachine3_req_valid;
+wire soc_sdram_bankmachine3_req_ready;
+wire soc_sdram_bankmachine3_req_we;
+wire [21:0] soc_sdram_bankmachine3_req_addr;
+wire soc_sdram_bankmachine3_req_lock;
+reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine3_refresh_req;
+reg soc_sdram_bankmachine3_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine3_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba;
+reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine3_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine3_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine3_row = 15'd0;
+reg soc_sdram_bankmachine3_row_opened = 1'd0;
+wire soc_sdram_bankmachine3_row_hit;
+reg soc_sdram_bankmachine3_row_open = 1'd0;
+reg soc_sdram_bankmachine3_row_close = 1'd0;
+reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0;
+wire soc_sdram_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0;
+wire soc_sdram_bankmachine4_req_valid;
+wire soc_sdram_bankmachine4_req_ready;
+wire soc_sdram_bankmachine4_req_we;
+wire [21:0] soc_sdram_bankmachine4_req_addr;
+wire soc_sdram_bankmachine4_req_lock;
+reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine4_refresh_req;
+reg soc_sdram_bankmachine4_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine4_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba;
+reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine4_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine4_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine4_row = 15'd0;
+reg soc_sdram_bankmachine4_row_opened = 1'd0;
+wire soc_sdram_bankmachine4_row_hit;
+reg soc_sdram_bankmachine4_row_open = 1'd0;
+reg soc_sdram_bankmachine4_row_close = 1'd0;
+reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0;
+wire soc_sdram_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0;
+wire soc_sdram_bankmachine5_req_valid;
+wire soc_sdram_bankmachine5_req_ready;
+wire soc_sdram_bankmachine5_req_we;
+wire [21:0] soc_sdram_bankmachine5_req_addr;
+wire soc_sdram_bankmachine5_req_lock;
+reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine5_refresh_req;
+reg soc_sdram_bankmachine5_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine5_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba;
+reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine5_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine5_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine5_row = 15'd0;
+reg soc_sdram_bankmachine5_row_opened = 1'd0;
+wire soc_sdram_bankmachine5_row_hit;
+reg soc_sdram_bankmachine5_row_open = 1'd0;
+reg soc_sdram_bankmachine5_row_close = 1'd0;
+reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0;
+wire soc_sdram_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0;
+wire soc_sdram_bankmachine6_req_valid;
+wire soc_sdram_bankmachine6_req_ready;
+wire soc_sdram_bankmachine6_req_we;
+wire [21:0] soc_sdram_bankmachine6_req_addr;
+wire soc_sdram_bankmachine6_req_lock;
+reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine6_refresh_req;
+reg soc_sdram_bankmachine6_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine6_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba;
+reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine6_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine6_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine6_row = 15'd0;
+reg soc_sdram_bankmachine6_row_opened = 1'd0;
+wire soc_sdram_bankmachine6_row_hit;
+reg soc_sdram_bankmachine6_row_open = 1'd0;
+reg soc_sdram_bankmachine6_row_close = 1'd0;
+reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0;
+wire soc_sdram_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0;
+wire soc_sdram_bankmachine7_req_valid;
+wire soc_sdram_bankmachine7_req_ready;
+wire soc_sdram_bankmachine7_req_we;
+wire [21:0] soc_sdram_bankmachine7_req_addr;
+wire soc_sdram_bankmachine7_req_lock;
+reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0;
+reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0;
+wire soc_sdram_bankmachine7_refresh_req;
+reg soc_sdram_bankmachine7_refresh_gnt = 1'd0;
+reg soc_sdram_bankmachine7_cmd_valid = 1'd0;
+reg soc_sdram_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] soc_sdram_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba;
+reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
+reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
+reg soc_sdram_bankmachine7_auto_precharge = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_valid;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_ready;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_first;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_last;
+wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire soc_sdram_bankmachine7_cmd_buffer_source_ready;
+reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] soc_sdram_bankmachine7_row = 15'd0;
+reg soc_sdram_bankmachine7_row_opened = 1'd0;
+wire soc_sdram_bankmachine7_row_hit;
+reg soc_sdram_bankmachine7_row_open = 1'd0;
+reg soc_sdram_bankmachine7_row_close = 1'd0;
+reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire soc_sdram_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0;
+wire soc_sdram_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0;
+wire soc_sdram_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1;
+reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0;
+wire soc_sdram_ras_allowed;
+wire soc_sdram_cas_allowed;
+reg soc_sdram_choose_cmd_want_reads = 1'd0;
+reg soc_sdram_choose_cmd_want_writes = 1'd0;
+reg soc_sdram_choose_cmd_want_cmds = 1'd0;
+reg soc_sdram_choose_cmd_want_activates = 1'd0;
+wire soc_sdram_choose_cmd_cmd_valid;
+reg soc_sdram_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] soc_sdram_choose_cmd_cmd_payload_a;
+wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba;
+reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
+reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
+reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0;
+wire soc_sdram_choose_cmd_cmd_payload_is_cmd;
+wire soc_sdram_choose_cmd_cmd_payload_is_read;
+wire soc_sdram_choose_cmd_cmd_payload_is_write;
+reg [7:0] soc_sdram_choose_cmd_valids = 8'd0;
+wire [7:0] soc_sdram_choose_cmd_request;
+reg [2:0] soc_sdram_choose_cmd_grant = 3'd0;
+wire soc_sdram_choose_cmd_ce;
+reg soc_sdram_choose_req_want_reads = 1'd0;
+reg soc_sdram_choose_req_want_writes = 1'd0;
+reg soc_sdram_choose_req_want_cmds = 1'd0;
+reg soc_sdram_choose_req_want_activates = 1'd0;
+wire soc_sdram_choose_req_cmd_valid;
+reg soc_sdram_choose_req_cmd_ready = 1'd0;
+wire [14:0] soc_sdram_choose_req_cmd_payload_a;
+wire [2:0] soc_sdram_choose_req_cmd_payload_ba;
+reg soc_sdram_choose_req_cmd_payload_cas = 1'd0;
+reg soc_sdram_choose_req_cmd_payload_ras = 1'd0;
+reg soc_sdram_choose_req_cmd_payload_we = 1'd0;
+wire soc_sdram_choose_req_cmd_payload_is_cmd;
+wire soc_sdram_choose_req_cmd_payload_is_read;
+wire soc_sdram_choose_req_cmd_payload_is_write;
+reg [7:0] soc_sdram_choose_req_valids = 8'd0;
+wire [7:0] soc_sdram_choose_req_request;
+reg [2:0] soc_sdram_choose_req_grant = 3'd0;
+wire soc_sdram_choose_req_ce;
+reg [14:0] soc_sdram_nop_a = 15'd0;
+reg [2:0] soc_sdram_nop_ba = 3'd0;
+reg [1:0] soc_sdram_steerer_sel0 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel1 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel2 = 2'd0;
+reg [1:0] soc_sdram_steerer_sel3 = 2'd0;
+reg soc_sdram_steerer0 = 1'd1;
+reg soc_sdram_steerer1 = 1'd1;
+reg soc_sdram_steerer2 = 1'd1;
+reg soc_sdram_steerer3 = 1'd1;
+reg soc_sdram_steerer4 = 1'd1;
+reg soc_sdram_steerer5 = 1'd1;
+reg soc_sdram_steerer6 = 1'd1;
+reg soc_sdram_steerer7 = 1'd1;
+wire soc_sdram_trrdcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1;
+reg soc_sdram_trrdcon_count = 1'd0;
+wire soc_sdram_tfawcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1;
+wire [2:0] soc_sdram_tfawcon_count;
+reg [4:0] soc_sdram_tfawcon_window = 5'd0;
+wire soc_sdram_tccdcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1;
+reg soc_sdram_tccdcon_count = 1'd0;
+wire soc_sdram_twtrcon_valid;
+(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1;
+reg [2:0] soc_sdram_twtrcon_count = 3'd0;
+wire soc_sdram_read_available;
+wire soc_sdram_write_available;
+reg soc_sdram_en0 = 1'd0;
+wire soc_sdram_max_time0;
+reg [4:0] soc_sdram_time0 = 5'd0;
+reg soc_sdram_en1 = 1'd0;
+wire soc_sdram_max_time1;
+reg [3:0] soc_sdram_time1 = 4'd0;
+wire soc_sdram_go_to_refresh;
+reg soc_port_cmd_valid = 1'd0;
+wire soc_port_cmd_ready;
+reg soc_port_cmd_payload_we = 1'd0;
+reg [24:0] soc_port_cmd_payload_addr = 25'd0;
+wire soc_port_wdata_valid;
+wire soc_port_wdata_ready;
+wire soc_port_wdata_first;
+wire soc_port_wdata_last;
+wire [127:0] soc_port_wdata_payload_data;
+wire [15:0] soc_port_wdata_payload_we;
+wire soc_port_rdata_valid;
+wire soc_port_rdata_ready;
+reg soc_port_rdata_first = 1'd0;
+reg soc_port_rdata_last = 1'd0;
+wire [127:0] soc_port_rdata_payload_data;
+wire [29:0] soc_wb_sdram_adr;
+wire [31:0] soc_wb_sdram_dat_w;
+reg [31:0] soc_wb_sdram_dat_r = 32'd0;
+wire [3:0] soc_wb_sdram_sel;
+wire soc_wb_sdram_cyc;
+wire soc_wb_sdram_stb;
+reg soc_wb_sdram_ack = 1'd0;
+wire soc_wb_sdram_we;
+wire [2:0] soc_wb_sdram_cti;
+wire [1:0] soc_wb_sdram_bte;
+reg soc_wb_sdram_err = 1'd0;
+wire [29:0] soc_litedram_wb_adr;
+reg [127:0] soc_litedram_wb_dat_w = 128'd0;
+wire [127:0] soc_litedram_wb_dat_r;
+reg [15:0] soc_litedram_wb_sel = 16'd0;
+reg soc_litedram_wb_cyc = 1'd0;
+reg soc_litedram_wb_stb = 1'd0;
+reg soc_litedram_wb_ack = 1'd0;
+reg soc_litedram_wb_we = 1'd0;
+wire [2:0] soc_litedram_wb_cti;
+reg soc_write = 1'd0;
+reg soc_evict = 1'd0;
+reg soc_refill = 1'd0;
+reg soc_read = 1'd0;
+wire [29:0] soc_address_d;
+reg [29:0] soc_address_q = 30'd0;
+reg soc_address_ce = 1'd0;
+reg soc_address_reset = 1'd0;
+reg [1:0] soc_counter = 2'd0;
+reg soc_counter_ce = 1'd0;
+reg soc_counter_reset = 1'd0;
+wire [1:0] soc_counter_offset;
+wire soc_counter_done;
+wire [127:0] soc_cached_data;
+wire [15:0] soc_cached_sel;
+wire soc_end_of_burst;
+wire soc_need_refill_d;
+reg soc_need_refill_q = 1'd1;
+reg soc_need_refill_ce = 1'd0;
+wire soc_need_refill_reset;
+reg [31:0] soc_cached_datas_flipflop0_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop0_q = 32'd0;
+reg soc_cached_datas_ce0 = 1'd0;
+reg soc_cached_datas_reset0 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop1_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop1_q = 32'd0;
+reg soc_cached_datas_ce1 = 1'd0;
+reg soc_cached_datas_reset1 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop2_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop2_q = 32'd0;
+reg soc_cached_datas_ce2 = 1'd0;
+reg soc_cached_datas_reset2 = 1'd0;
+reg [31:0] soc_cached_datas_flipflop3_d = 32'd0;
+reg [31:0] soc_cached_datas_flipflop3_q = 32'd0;
+reg soc_cached_datas_ce3 = 1'd0;
+reg soc_cached_datas_reset3 = 1'd0;
+wire [3:0] soc_cached_sels_flipflop0_d;
+reg [3:0] soc_cached_sels_flipflop0_q = 4'd0;
+reg soc_cached_sels_ce0 = 1'd0;
+wire soc_cached_sels_reset0;
+wire [3:0] soc_cached_sels_flipflop1_d;
+reg [3:0] soc_cached_sels_flipflop1_q = 4'd0;
+reg soc_cached_sels_ce1 = 1'd0;
+wire soc_cached_sels_reset1;
+wire [3:0] soc_cached_sels_flipflop2_d;
+reg [3:0] soc_cached_sels_flipflop2_q = 4'd0;
+reg soc_cached_sels_ce2 = 1'd0;
+wire soc_cached_sels_reset2;
+wire [3:0] soc_cached_sels_flipflop3_d;
+reg [3:0] soc_cached_sels_flipflop3_q = 4'd0;
+reg soc_cached_sels_ce3 = 1'd0;
+wire soc_cached_sels_reset3;
+reg soc_write_sel0 = 1'd0;
+reg soc_write_sel1 = 1'd0;
+reg soc_write_sel2 = 1'd0;
+reg soc_write_sel3 = 1'd0;
+wire soc_wdata_converter_sink_valid;
+wire soc_wdata_converter_sink_ready;
+reg soc_wdata_converter_sink_first = 1'd0;
+reg soc_wdata_converter_sink_last = 1'd0;
+wire [127:0] soc_wdata_converter_sink_payload_data;
+wire [15:0] soc_wdata_converter_sink_payload_we;
+wire soc_wdata_converter_source_valid;
+wire soc_wdata_converter_source_ready;
+wire soc_wdata_converter_source_first;
+wire soc_wdata_converter_source_last;
+wire [127:0] soc_wdata_converter_source_payload_data;
+wire [15:0] soc_wdata_converter_source_payload_we;
+wire soc_wdata_converter_converter_sink_valid;
+wire soc_wdata_converter_converter_sink_ready;
+wire soc_wdata_converter_converter_sink_first;
+wire soc_wdata_converter_converter_sink_last;
+wire [143:0] soc_wdata_converter_converter_sink_payload_data;
+wire soc_wdata_converter_converter_source_valid;
+wire soc_wdata_converter_converter_source_ready;
+wire soc_wdata_converter_converter_source_first;
+wire soc_wdata_converter_converter_source_last;
+wire [143:0] soc_wdata_converter_converter_source_payload_data;
+wire soc_wdata_converter_converter_source_payload_valid_token_count;
+wire soc_wdata_converter_source_source_valid;
+wire soc_wdata_converter_source_source_ready;
+wire soc_wdata_converter_source_source_first;
+wire soc_wdata_converter_source_source_last;
+wire [143:0] soc_wdata_converter_source_source_payload_data;
+wire soc_rdata_converter_sink_valid;
+wire soc_rdata_converter_sink_ready;
+wire soc_rdata_converter_sink_first;
+wire soc_rdata_converter_sink_last;
+wire [127:0] soc_rdata_converter_sink_payload_data;
+wire soc_rdata_converter_source_valid;
+wire soc_rdata_converter_source_ready;
+wire soc_rdata_converter_source_first;
+wire soc_rdata_converter_source_last;
+wire [127:0] soc_rdata_converter_source_payload_data;
+wire soc_rdata_converter_converter_sink_valid;
+wire soc_rdata_converter_converter_sink_ready;
+wire soc_rdata_converter_converter_sink_first;
+wire soc_rdata_converter_converter_sink_last;
+wire [127:0] soc_rdata_converter_converter_sink_payload_data;
+wire soc_rdata_converter_converter_source_valid;
+wire soc_rdata_converter_converter_source_ready;
+wire soc_rdata_converter_converter_source_first;
+wire soc_rdata_converter_converter_source_last;
+wire [127:0] soc_rdata_converter_converter_source_payload_data;
+wire soc_rdata_converter_converter_source_payload_valid_token_count;
+wire soc_rdata_converter_source_source_valid;
+wire soc_rdata_converter_source_source_ready;
+wire soc_rdata_converter_source_source_first;
+wire soc_rdata_converter_source_source_last;
+wire [127:0] soc_rdata_converter_source_source_payload_data;
+reg soc_count = 1'd0;
+reg soc_init_done_storage = 1'd0;
+reg soc_init_done_re = 1'd0;
+reg soc_init_error_storage = 1'd0;
+reg soc_init_error_re = 1'd0;
+wire soc_cmd_valid;
+wire soc_cmd_ready;
+wire soc_cmd_payload_we;
+wire [24:0] soc_cmd_payload_addr;
+wire soc_wdata_valid;
+wire soc_wdata_ready;
+wire [127:0] soc_wdata_payload_data;
+wire [15:0] soc_wdata_payload_we;
+wire soc_rdata_valid;
+wire soc_rdata_ready;
+wire [127:0] soc_rdata_payload_data;
+reg vns_wb2csr_state = 1'd0;
+reg vns_wb2csr_next_state = 1'd0;
+wire vns_pll_fb0;
+wire vns_pll_fb1;
+reg [1:0] vns_refresher_state = 2'd0;
+reg [1:0] vns_refresher_next_state = 2'd0;
+reg [3:0] vns_bankmachine0_state = 4'd0;
+reg [3:0] vns_bankmachine0_next_state = 4'd0;
+reg [3:0] vns_bankmachine1_state = 4'd0;
+reg [3:0] vns_bankmachine1_next_state = 4'd0;
+reg [3:0] vns_bankmachine2_state = 4'd0;
+reg [3:0] vns_bankmachine2_next_state = 4'd0;
+reg [3:0] vns_bankmachine3_state = 4'd0;
+reg [3:0] vns_bankmachine3_next_state = 4'd0;
+reg [3:0] vns_bankmachine4_state = 4'd0;
+reg [3:0] vns_bankmachine4_next_state = 4'd0;
+reg [3:0] vns_bankmachine5_state = 4'd0;
+reg [3:0] vns_bankmachine5_next_state = 4'd0;
+reg [3:0] vns_bankmachine6_state = 4'd0;
+reg [3:0] vns_bankmachine6_next_state = 4'd0;
+reg [3:0] vns_bankmachine7_state = 4'd0;
+reg [3:0] vns_bankmachine7_next_state = 4'd0;
+reg [3:0] vns_multiplexer_state = 4'd0;
+reg [3:0] vns_multiplexer_next_state = 4'd0;
+wire [1:0] vns_roundrobin0_request;
+reg vns_roundrobin0_grant = 1'd0;
+wire vns_roundrobin0_ce;
+wire [1:0] vns_roundrobin1_request;
+reg vns_roundrobin1_grant = 1'd0;
+wire vns_roundrobin1_ce;
+wire [1:0] vns_roundrobin2_request;
+reg vns_roundrobin2_grant = 1'd0;
+wire vns_roundrobin2_ce;
+wire [1:0] vns_roundrobin3_request;
+reg vns_roundrobin3_grant = 1'd0;
+wire vns_roundrobin3_ce;
+wire [1:0] vns_roundrobin4_request;
+reg vns_roundrobin4_grant = 1'd0;
+wire vns_roundrobin4_ce;
+wire [1:0] vns_roundrobin5_request;
+reg vns_roundrobin5_grant = 1'd0;
+wire vns_roundrobin5_ce;
+wire [1:0] vns_roundrobin6_request;
+reg vns_roundrobin6_grant = 1'd0;
+wire vns_roundrobin6_ce;
+wire [1:0] vns_roundrobin7_request;
+reg vns_roundrobin7_grant = 1'd0;
+wire vns_roundrobin7_ce;
+reg vns_locked0 = 1'd0;
+reg vns_locked1 = 1'd0;
+reg vns_locked2 = 1'd0;
+reg vns_locked3 = 1'd0;
+reg vns_locked4 = 1'd0;
+reg vns_locked5 = 1'd0;
+reg vns_locked6 = 1'd0;
+reg vns_locked7 = 1'd0;
+reg vns_locked8 = 1'd0;
+reg vns_locked9 = 1'd0;
+reg vns_locked10 = 1'd0;
+reg vns_locked11 = 1'd0;
+reg vns_locked12 = 1'd0;
+reg vns_locked13 = 1'd0;
+reg vns_locked14 = 1'd0;
+reg vns_locked15 = 1'd0;
+reg vns_new_master_wdata_ready0 = 1'd0;
+reg vns_new_master_wdata_ready1 = 1'd0;
+reg vns_new_master_wdata_ready2 = 1'd0;
+reg vns_new_master_wdata_ready3 = 1'd0;
+reg vns_new_master_wdata_ready4 = 1'd0;
+reg vns_new_master_wdata_ready5 = 1'd0;
+reg vns_new_master_rdata_valid0 = 1'd0;
+reg vns_new_master_rdata_valid1 = 1'd0;
+reg vns_new_master_rdata_valid2 = 1'd0;
+reg vns_new_master_rdata_valid3 = 1'd0;
+reg vns_new_master_rdata_valid4 = 1'd0;
+reg vns_new_master_rdata_valid5 = 1'd0;
+reg vns_new_master_rdata_valid6 = 1'd0;
+reg vns_new_master_rdata_valid7 = 1'd0;
+reg vns_new_master_rdata_valid8 = 1'd0;
+reg vns_new_master_rdata_valid9 = 1'd0;
+reg vns_new_master_rdata_valid10 = 1'd0;
+reg vns_new_master_rdata_valid11 = 1'd0;
+reg vns_new_master_rdata_valid12 = 1'd0;
+reg vns_new_master_rdata_valid13 = 1'd0;
+reg vns_new_master_rdata_valid14 = 1'd0;
+reg vns_new_master_rdata_valid15 = 1'd0;
+reg vns_new_master_rdata_valid16 = 1'd0;
+reg vns_new_master_rdata_valid17 = 1'd0;
+reg [2:0] vns_converter_state = 3'd0;
+reg [2:0] vns_converter_next_state = 3'd0;
+reg [1:0] vns_litedramwishbone2native_state = 2'd0;
+reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
+reg soc_count_next_value = 1'd0;
+reg soc_count_next_value_ce = 1'd0;
+wire [29:0] vns_shared_adr;
+wire [31:0] vns_shared_dat_w;
+reg [31:0] vns_shared_dat_r = 32'd0;
+wire [3:0] vns_shared_sel;
+wire vns_shared_cyc;
+wire vns_shared_stb;
+reg vns_shared_ack = 1'd0;
+wire vns_shared_we;
+wire [2:0] vns_shared_cti;
+wire [1:0] vns_shared_bte;
+wire vns_shared_err;
+wire [1:0] vns_request;
+reg vns_grant = 1'd0;
+reg [3:0] vns_slave_sel = 4'd0;
+reg [3:0] vns_slave_sel_r = 4'd0;
+reg vns_error = 1'd0;
+wire vns_wait;
+wire vns_done;
+reg [19:0] vns_count = 20'd1000000;
+wire [13:0] vns_interface0_bank_bus_adr;
+wire vns_interface0_bank_bus_we;
+wire [7:0] vns_interface0_bank_bus_dat_w;
+reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0;
+wire vns_csrbank0_reset0_re;
+wire vns_csrbank0_reset0_r;
+wire vns_csrbank0_reset0_we;
+wire vns_csrbank0_reset0_w;
+wire vns_csrbank0_scratch3_re;
+wire [7:0] vns_csrbank0_scratch3_r;
+wire vns_csrbank0_scratch3_we;
+wire [7:0] vns_csrbank0_scratch3_w;
+wire vns_csrbank0_scratch2_re;
+wire [7:0] vns_csrbank0_scratch2_r;
+wire vns_csrbank0_scratch2_we;
+wire [7:0] vns_csrbank0_scratch2_w;
+wire vns_csrbank0_scratch1_re;
+wire [7:0] vns_csrbank0_scratch1_r;
+wire vns_csrbank0_scratch1_we;
+wire [7:0] vns_csrbank0_scratch1_w;
+wire vns_csrbank0_scratch0_re;
+wire [7:0] vns_csrbank0_scratch0_r;
+wire vns_csrbank0_scratch0_we;
+wire [7:0] vns_csrbank0_scratch0_w;
+wire vns_csrbank0_bus_errors3_re;
+wire [7:0] vns_csrbank0_bus_errors3_r;
+wire vns_csrbank0_bus_errors3_we;
+wire [7:0] vns_csrbank0_bus_errors3_w;
+wire vns_csrbank0_bus_errors2_re;
+wire [7:0] vns_csrbank0_bus_errors2_r;
+wire vns_csrbank0_bus_errors2_we;
+wire [7:0] vns_csrbank0_bus_errors2_w;
+wire vns_csrbank0_bus_errors1_re;
+wire [7:0] vns_csrbank0_bus_errors1_r;
+wire vns_csrbank0_bus_errors1_we;
+wire [7:0] vns_csrbank0_bus_errors1_w;
+wire vns_csrbank0_bus_errors0_re;
+wire [7:0] vns_csrbank0_bus_errors0_r;
+wire vns_csrbank0_bus_errors0_we;
+wire [7:0] vns_csrbank0_bus_errors0_w;
+wire vns_csrbank0_sel;
+wire [13:0] vns_interface1_bank_bus_adr;
+wire vns_interface1_bank_bus_we;
+wire [7:0] vns_interface1_bank_bus_dat_w;
+reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0;
+wire vns_csrbank1_init_done0_re;
+wire vns_csrbank1_init_done0_r;
+wire vns_csrbank1_init_done0_we;
+wire vns_csrbank1_init_done0_w;
+wire vns_csrbank1_init_error0_re;
+wire vns_csrbank1_init_error0_r;
+wire vns_csrbank1_init_error0_we;
+wire vns_csrbank1_init_error0_w;
+wire vns_csrbank1_sel;
+wire [13:0] vns_interface2_bank_bus_adr;
+wire vns_interface2_bank_bus_we;
+wire [7:0] vns_interface2_bank_bus_dat_w;
+reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0;
+wire vns_csrbank2_half_sys8x_taps0_re;
+wire [4:0] vns_csrbank2_half_sys8x_taps0_r;
+wire vns_csrbank2_half_sys8x_taps0_we;
+wire [4:0] vns_csrbank2_half_sys8x_taps0_w;
+wire vns_csrbank2_wlevel_en0_re;
+wire vns_csrbank2_wlevel_en0_r;
+wire vns_csrbank2_wlevel_en0_we;
+wire vns_csrbank2_wlevel_en0_w;
+wire vns_csrbank2_dly_sel0_re;
+wire [1:0] vns_csrbank2_dly_sel0_r;
+wire vns_csrbank2_dly_sel0_we;
+wire [1:0] vns_csrbank2_dly_sel0_w;
+wire vns_csrbank2_sel;
+wire [13:0] vns_interface3_bank_bus_adr;
+wire vns_interface3_bank_bus_we;
+wire [7:0] vns_interface3_bank_bus_dat_w;
+reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0;
+wire vns_csrbank3_dfii_control0_re;
+wire [3:0] vns_csrbank3_dfii_control0_r;
+wire vns_csrbank3_dfii_control0_we;
+wire [3:0] vns_csrbank3_dfii_control0_w;
+wire vns_csrbank3_dfii_pi0_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi0_command0_r;
+wire vns_csrbank3_dfii_pi0_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi0_command0_w;
+wire vns_csrbank3_dfii_pi0_address1_re;
+wire [6:0] vns_csrbank3_dfii_pi0_address1_r;
+wire vns_csrbank3_dfii_pi0_address1_we;
+wire [6:0] vns_csrbank3_dfii_pi0_address1_w;
+wire vns_csrbank3_dfii_pi0_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_address0_r;
+wire vns_csrbank3_dfii_pi0_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_address0_w;
+wire vns_csrbank3_dfii_pi0_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r;
+wire vns_csrbank3_dfii_pi0_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w;
+wire vns_csrbank3_dfii_pi0_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r;
+wire vns_csrbank3_dfii_pi0_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w;
+wire vns_csrbank3_dfii_pi0_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r;
+wire vns_csrbank3_dfii_pi0_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w;
+wire vns_csrbank3_dfii_pi0_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r;
+wire vns_csrbank3_dfii_pi0_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w;
+wire vns_csrbank3_dfii_pi0_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r;
+wire vns_csrbank3_dfii_pi0_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w;
+wire vns_csrbank3_dfii_pi0_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r;
+wire vns_csrbank3_dfii_pi0_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w;
+wire vns_csrbank3_dfii_pi0_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r;
+wire vns_csrbank3_dfii_pi0_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w;
+wire vns_csrbank3_dfii_pi0_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r;
+wire vns_csrbank3_dfii_pi0_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w;
+wire vns_csrbank3_dfii_pi0_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r;
+wire vns_csrbank3_dfii_pi0_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w;
+wire vns_csrbank3_dfii_pi1_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi1_command0_r;
+wire vns_csrbank3_dfii_pi1_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi1_command0_w;
+wire vns_csrbank3_dfii_pi1_address1_re;
+wire [6:0] vns_csrbank3_dfii_pi1_address1_r;
+wire vns_csrbank3_dfii_pi1_address1_we;
+wire [6:0] vns_csrbank3_dfii_pi1_address1_w;
+wire vns_csrbank3_dfii_pi1_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_address0_r;
+wire vns_csrbank3_dfii_pi1_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_address0_w;
+wire vns_csrbank3_dfii_pi1_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r;
+wire vns_csrbank3_dfii_pi1_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w;
+wire vns_csrbank3_dfii_pi1_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r;
+wire vns_csrbank3_dfii_pi1_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w;
+wire vns_csrbank3_dfii_pi1_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r;
+wire vns_csrbank3_dfii_pi1_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w;
+wire vns_csrbank3_dfii_pi1_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r;
+wire vns_csrbank3_dfii_pi1_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w;
+wire vns_csrbank3_dfii_pi1_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r;
+wire vns_csrbank3_dfii_pi1_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w;
+wire vns_csrbank3_dfii_pi1_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r;
+wire vns_csrbank3_dfii_pi1_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w;
+wire vns_csrbank3_dfii_pi1_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r;
+wire vns_csrbank3_dfii_pi1_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w;
+wire vns_csrbank3_dfii_pi1_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r;
+wire vns_csrbank3_dfii_pi1_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w;
+wire vns_csrbank3_dfii_pi1_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r;
+wire vns_csrbank3_dfii_pi1_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w;
+wire vns_csrbank3_dfii_pi2_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi2_command0_r;
+wire vns_csrbank3_dfii_pi2_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi2_command0_w;
+wire vns_csrbank3_dfii_pi2_address1_re;
+wire [6:0] vns_csrbank3_dfii_pi2_address1_r;
+wire vns_csrbank3_dfii_pi2_address1_we;
+wire [6:0] vns_csrbank3_dfii_pi2_address1_w;
+wire vns_csrbank3_dfii_pi2_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_address0_r;
+wire vns_csrbank3_dfii_pi2_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_address0_w;
+wire vns_csrbank3_dfii_pi2_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r;
+wire vns_csrbank3_dfii_pi2_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w;
+wire vns_csrbank3_dfii_pi2_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r;
+wire vns_csrbank3_dfii_pi2_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w;
+wire vns_csrbank3_dfii_pi2_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r;
+wire vns_csrbank3_dfii_pi2_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w;
+wire vns_csrbank3_dfii_pi2_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r;
+wire vns_csrbank3_dfii_pi2_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w;
+wire vns_csrbank3_dfii_pi2_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r;
+wire vns_csrbank3_dfii_pi2_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w;
+wire vns_csrbank3_dfii_pi2_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r;
+wire vns_csrbank3_dfii_pi2_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w;
+wire vns_csrbank3_dfii_pi2_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r;
+wire vns_csrbank3_dfii_pi2_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w;
+wire vns_csrbank3_dfii_pi2_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r;
+wire vns_csrbank3_dfii_pi2_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w;
+wire vns_csrbank3_dfii_pi2_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r;
+wire vns_csrbank3_dfii_pi2_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w;
+wire vns_csrbank3_dfii_pi3_command0_re;
+wire [5:0] vns_csrbank3_dfii_pi3_command0_r;
+wire vns_csrbank3_dfii_pi3_command0_we;
+wire [5:0] vns_csrbank3_dfii_pi3_command0_w;
+wire vns_csrbank3_dfii_pi3_address1_re;
+wire [6:0] vns_csrbank3_dfii_pi3_address1_r;
+wire vns_csrbank3_dfii_pi3_address1_we;
+wire [6:0] vns_csrbank3_dfii_pi3_address1_w;
+wire vns_csrbank3_dfii_pi3_address0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_address0_r;
+wire vns_csrbank3_dfii_pi3_address0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_address0_w;
+wire vns_csrbank3_dfii_pi3_baddress0_re;
+wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r;
+wire vns_csrbank3_dfii_pi3_baddress0_we;
+wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w;
+wire vns_csrbank3_dfii_pi3_wrdata3_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r;
+wire vns_csrbank3_dfii_pi3_wrdata3_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w;
+wire vns_csrbank3_dfii_pi3_wrdata2_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r;
+wire vns_csrbank3_dfii_pi3_wrdata2_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w;
+wire vns_csrbank3_dfii_pi3_wrdata1_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r;
+wire vns_csrbank3_dfii_pi3_wrdata1_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w;
+wire vns_csrbank3_dfii_pi3_wrdata0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r;
+wire vns_csrbank3_dfii_pi3_wrdata0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w;
+wire vns_csrbank3_dfii_pi3_rddata3_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r;
+wire vns_csrbank3_dfii_pi3_rddata3_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w;
+wire vns_csrbank3_dfii_pi3_rddata2_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r;
+wire vns_csrbank3_dfii_pi3_rddata2_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w;
+wire vns_csrbank3_dfii_pi3_rddata1_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r;
+wire vns_csrbank3_dfii_pi3_rddata1_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w;
+wire vns_csrbank3_dfii_pi3_rddata0_re;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r;
+wire vns_csrbank3_dfii_pi3_rddata0_we;
+wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w;
+wire vns_csrbank3_sel;
+wire [13:0] vns_interface4_bank_bus_adr;
+wire vns_interface4_bank_bus_we;
+wire [7:0] vns_interface4_bank_bus_dat_w;
+reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0;
+wire vns_csrbank4_load3_re;
+wire [7:0] vns_csrbank4_load3_r;
+wire vns_csrbank4_load3_we;
+wire [7:0] vns_csrbank4_load3_w;
+wire vns_csrbank4_load2_re;
+wire [7:0] vns_csrbank4_load2_r;
+wire vns_csrbank4_load2_we;
+wire [7:0] vns_csrbank4_load2_w;
+wire vns_csrbank4_load1_re;
+wire [7:0] vns_csrbank4_load1_r;
+wire vns_csrbank4_load1_we;
+wire [7:0] vns_csrbank4_load1_w;
+wire vns_csrbank4_load0_re;
+wire [7:0] vns_csrbank4_load0_r;
+wire vns_csrbank4_load0_we;
+wire [7:0] vns_csrbank4_load0_w;
+wire vns_csrbank4_reload3_re;
+wire [7:0] vns_csrbank4_reload3_r;
+wire vns_csrbank4_reload3_we;
+wire [7:0] vns_csrbank4_reload3_w;
+wire vns_csrbank4_reload2_re;
+wire [7:0] vns_csrbank4_reload2_r;
+wire vns_csrbank4_reload2_we;
+wire [7:0] vns_csrbank4_reload2_w;
+wire vns_csrbank4_reload1_re;
+wire [7:0] vns_csrbank4_reload1_r;
+wire vns_csrbank4_reload1_we;
+wire [7:0] vns_csrbank4_reload1_w;
+wire vns_csrbank4_reload0_re;
+wire [7:0] vns_csrbank4_reload0_r;
+wire vns_csrbank4_reload0_we;
+wire [7:0] vns_csrbank4_reload0_w;
+wire vns_csrbank4_en0_re;
+wire vns_csrbank4_en0_r;
+wire vns_csrbank4_en0_we;
+wire vns_csrbank4_en0_w;
+wire vns_csrbank4_update_value0_re;
+wire vns_csrbank4_update_value0_r;
+wire vns_csrbank4_update_value0_we;
+wire vns_csrbank4_update_value0_w;
+wire vns_csrbank4_value3_re;
+wire [7:0] vns_csrbank4_value3_r;
+wire vns_csrbank4_value3_we;
+wire [7:0] vns_csrbank4_value3_w;
+wire vns_csrbank4_value2_re;
+wire [7:0] vns_csrbank4_value2_r;
+wire vns_csrbank4_value2_we;
+wire [7:0] vns_csrbank4_value2_w;
+wire vns_csrbank4_value1_re;
+wire [7:0] vns_csrbank4_value1_r;
+wire vns_csrbank4_value1_we;
+wire [7:0] vns_csrbank4_value1_w;
+wire vns_csrbank4_value0_re;
+wire [7:0] vns_csrbank4_value0_r;
+wire vns_csrbank4_value0_we;
+wire [7:0] vns_csrbank4_value0_w;
+wire vns_csrbank4_ev_enable0_re;
+wire vns_csrbank4_ev_enable0_r;
+wire vns_csrbank4_ev_enable0_we;
+wire vns_csrbank4_ev_enable0_w;
+wire vns_csrbank4_sel;
+wire [13:0] vns_interface5_bank_bus_adr;
+wire vns_interface5_bank_bus_we;
+wire [7:0] vns_interface5_bank_bus_dat_w;
+reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0;
+wire vns_csrbank5_txfull_re;
+wire vns_csrbank5_txfull_r;
+wire vns_csrbank5_txfull_we;
+wire vns_csrbank5_txfull_w;
+wire vns_csrbank5_rxempty_re;
+wire vns_csrbank5_rxempty_r;
+wire vns_csrbank5_rxempty_we;
+wire vns_csrbank5_rxempty_w;
+wire vns_csrbank5_ev_enable0_re;
+wire [1:0] vns_csrbank5_ev_enable0_r;
+wire vns_csrbank5_ev_enable0_we;
+wire [1:0] vns_csrbank5_ev_enable0_w;
+wire vns_csrbank5_sel;
+wire [13:0] vns_interface6_bank_bus_adr;
+wire vns_interface6_bank_bus_we;
+wire [7:0] vns_interface6_bank_bus_dat_w;
+reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0;
+wire vns_csrbank6_tuning_word3_re;
+wire [7:0] vns_csrbank6_tuning_word3_r;
+wire vns_csrbank6_tuning_word3_we;
+wire [7:0] vns_csrbank6_tuning_word3_w;
+wire vns_csrbank6_tuning_word2_re;
+wire [7:0] vns_csrbank6_tuning_word2_r;
+wire vns_csrbank6_tuning_word2_we;
+wire [7:0] vns_csrbank6_tuning_word2_w;
+wire vns_csrbank6_tuning_word1_re;
+wire [7:0] vns_csrbank6_tuning_word1_r;
+wire vns_csrbank6_tuning_word1_we;
+wire [7:0] vns_csrbank6_tuning_word1_w;
+wire vns_csrbank6_tuning_word0_re;
+wire [7:0] vns_csrbank6_tuning_word0_r;
+wire vns_csrbank6_tuning_word0_we;
+wire [7:0] vns_csrbank6_tuning_word0_w;
+wire vns_csrbank6_sel;
+wire [13:0] vns_adr;
+wire vns_we;
+wire [7:0] vns_dat_w;
+wire [7:0] vns_dat_r;
+reg vns_rhs_array_muxed0 = 1'd0;
+reg [14:0] vns_rhs_array_muxed1 = 15'd0;
+reg [2:0] vns_rhs_array_muxed2 = 3'd0;
+reg vns_rhs_array_muxed3 = 1'd0;
+reg vns_rhs_array_muxed4 = 1'd0;
+reg vns_rhs_array_muxed5 = 1'd0;
+reg vns_t_array_muxed0 = 1'd0;
+reg vns_t_array_muxed1 = 1'd0;
+reg vns_t_array_muxed2 = 1'd0;
+reg vns_rhs_array_muxed6 = 1'd0;
+reg [14:0] vns_rhs_array_muxed7 = 15'd0;
+reg [2:0] vns_rhs_array_muxed8 = 3'd0;
+reg vns_rhs_array_muxed9 = 1'd0;
+reg vns_rhs_array_muxed10 = 1'd0;
+reg vns_rhs_array_muxed11 = 1'd0;
+reg vns_t_array_muxed3 = 1'd0;
+reg vns_t_array_muxed4 = 1'd0;
+reg vns_t_array_muxed5 = 1'd0;
+reg [21:0] vns_rhs_array_muxed12 = 22'd0;
+reg vns_rhs_array_muxed13 = 1'd0;
+reg vns_rhs_array_muxed14 = 1'd0;
+reg [21:0] vns_rhs_array_muxed15 = 22'd0;
+reg vns_rhs_array_muxed16 = 1'd0;
+reg vns_rhs_array_muxed17 = 1'd0;
+reg [21:0] vns_rhs_array_muxed18 = 22'd0;
+reg vns_rhs_array_muxed19 = 1'd0;
+reg vns_rhs_array_muxed20 = 1'd0;
+reg [21:0] vns_rhs_array_muxed21 = 22'd0;
+reg vns_rhs_array_muxed22 = 1'd0;
+reg vns_rhs_array_muxed23 = 1'd0;
+reg [21:0] vns_rhs_array_muxed24 = 22'd0;
+reg vns_rhs_array_muxed25 = 1'd0;
+reg vns_rhs_array_muxed26 = 1'd0;
+reg [21:0] vns_rhs_array_muxed27 = 22'd0;
+reg vns_rhs_array_muxed28 = 1'd0;
+reg vns_rhs_array_muxed29 = 1'd0;
+reg [21:0] vns_rhs_array_muxed30 = 22'd0;
+reg vns_rhs_array_muxed31 = 1'd0;
+reg vns_rhs_array_muxed32 = 1'd0;
+reg [21:0] vns_rhs_array_muxed33 = 22'd0;
+reg vns_rhs_array_muxed34 = 1'd0;
+reg vns_rhs_array_muxed35 = 1'd0;
+reg [29:0] vns_rhs_array_muxed36 = 30'd0;
+reg [31:0] vns_rhs_array_muxed37 = 32'd0;
+reg [3:0] vns_rhs_array_muxed38 = 4'd0;
+reg vns_rhs_array_muxed39 = 1'd0;
+reg vns_rhs_array_muxed40 = 1'd0;
+reg vns_rhs_array_muxed41 = 1'd0;
+reg [2:0] vns_rhs_array_muxed42 = 3'd0;
+reg [1:0] vns_rhs_array_muxed43 = 2'd0;
+reg [2:0] vns_array_muxed0 = 3'd0;
+reg [14:0] vns_array_muxed1 = 15'd0;
+reg vns_array_muxed2 = 1'd0;
+reg vns_array_muxed3 = 1'd0;
+reg vns_array_muxed4 = 1'd0;
+reg vns_array_muxed5 = 1'd0;
+reg vns_array_muxed6 = 1'd0;
+reg [2:0] vns_array_muxed7 = 3'd0;
+reg [14:0] vns_array_muxed8 = 15'd0;
+reg vns_array_muxed9 = 1'd0;
+reg vns_array_muxed10 = 1'd0;
+reg vns_array_muxed11 = 1'd0;
+reg vns_array_muxed12 = 1'd0;
+reg vns_array_muxed13 = 1'd0;
+reg [2:0] vns_array_muxed14 = 3'd0;
+reg [14:0] vns_array_muxed15 = 15'd0;
+reg vns_array_muxed16 = 1'd0;
+reg vns_array_muxed17 = 1'd0;
+reg vns_array_muxed18 = 1'd0;
+reg vns_array_muxed19 = 1'd0;
+reg vns_array_muxed20 = 1'd0;
+reg [2:0] vns_array_muxed21 = 3'd0;
+reg [14:0] vns_array_muxed22 = 15'd0;
+reg vns_array_muxed23 = 1'd0;
+reg vns_array_muxed24 = 1'd0;
+reg vns_array_muxed25 = 1'd0;
+reg vns_array_muxed26 = 1'd0;
+reg vns_array_muxed27 = 1'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0;
+wire vns_xilinxasyncresetsynchronizerimpl0;
+wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1;
+wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl1_expr;
+wire vns_xilinxasyncresetsynchronizerimpl2;
+wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire vns_xilinxasyncresetsynchronizerimpl2_expr;
+wire vns_xilinxasyncresetsynchronizerimpl3;
+wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset;
+assign init_done = soc_init_done_storage;
+assign init_error = soc_init_error_storage;
+assign user_clk = sys_clk;
+assign user_rst = sys_rst;
+assign soc_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = soc_cmd_ready;
+assign soc_cmd_payload_we = user_port_native_0_cmd_we;
+assign soc_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign soc_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = soc_wdata_ready;
+assign soc_wdata_payload_we = user_port_native_0_wdata_we;
+assign soc_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = soc_rdata_valid;
+assign soc_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = soc_rdata_payload_data;
+assign soc_litedramcore_soccontroller_bus_error = vns_error;
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_cpu_interrupt <= 32'd0;
+ soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq;
+ soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq;
+// synthesis translate_off
+ dummy_d = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re;
+assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors;
+assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0];
+assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r;
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_ram_we <= 4'd0;
+ soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]);
+ soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]);
+ soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]);
+ soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]);
+// synthesis translate_off
+ dummy_d_1 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0];
+assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r;
+assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w;
+assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid;
+assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready;
+assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first;
+assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last;
+assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data;
+assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid;
+assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready;
+assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first;
+assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last;
+assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data;
+assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re;
+assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r;
+assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready);
+assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid;
+assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready;
+assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first;
+assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last;
+assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data;
+assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready);
+assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid;
+assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready;
+assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first;
+assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last;
+assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data;
+assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid);
+assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data;
+assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we));
+assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid);
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_eventmanager_status_w <= 2'd0;
+ soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status;
+ soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status;
+// synthesis translate_off
+ dummy_d_2 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_tx_clear <= 1'd0;
+ if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin
+ soc_litedramcore_uart_tx_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_3 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_4;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_eventmanager_pending_w <= 2'd0;
+ soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending;
+ soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending;
+// synthesis translate_off
+ dummy_d_4 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_5;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_rx_clear <= 1'd0;
+ if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin
+ soc_litedramcore_uart_rx_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_5 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1]));
+assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger;
+assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data};
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
+assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last;
+assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data;
+assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable;
+assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first;
+assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last;
+assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
+assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re));
+assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable);
+
+// synthesis translate_off
+reg dummy_d_6;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0;
+ if (soc_litedramcore_uart_tx_fifo_replace) begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1);
+ end else begin
+ soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce;
+ end
+// synthesis translate_off
+ dummy_d_6 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din;
+assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace));
+assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re);
+assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r;
+assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read;
+assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16);
+assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0);
+assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data};
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
+assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last;
+assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data;
+assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable;
+assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first;
+assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last;
+assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
+assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re));
+assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable);
+
+// synthesis translate_off
+reg dummy_d_7;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0;
+ if (soc_litedramcore_uart_rx_fifo_replace) begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1);
+ end else begin
+ soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce;
+ end
+// synthesis translate_off
+ dummy_d_7 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din;
+assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace));
+assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re);
+assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r;
+assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read;
+assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16);
+assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0);
+assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0);
+assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status;
+
+// synthesis translate_off
+reg dummy_d_8;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_timer_zero_clear <= 1'd0;
+ if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin
+ soc_litedramcore_timer_zero_clear <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_8 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending;
+assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage);
+assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger;
+assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w;
+assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r;
+
+// synthesis translate_off
+reg dummy_d_9;
+// synthesis translate_on
+always @(*) begin
+ vns_wb2csr_next_state <= 1'd0;
+ vns_wb2csr_next_state <= vns_wb2csr_state;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ vns_wb2csr_next_state <= 1'd0;
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ vns_wb2csr_next_state <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_9 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_10;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_interface_adr <= 14'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_10 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_11;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_interface_we <= 1'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
+ soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_11 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_12;
+// synthesis translate_on
+always @(*) begin
+ soc_litedramcore_bus_wishbone_ack <= 1'd0;
+ case (vns_wb2csr_state)
+ 1'd1: begin
+ soc_litedramcore_bus_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_12 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sys_pll_reset = rst;
+assign pll_locked = soc_sys_pll_locked;
+assign soc_iodelay_pll_reset = rst;
+assign soc_s7pll0_clkin = clk;
+assign sys_clk = soc_s7pll0_clkout_buf0;
+assign sys4x_clk = soc_s7pll0_clkout_buf1;
+assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2;
+assign soc_s7pll1_clkin = clk;
+assign iodelay_clk = soc_s7pll1_clkout_buf;
+assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
+
+// synthesis translate_off
+reg dummy_d_13;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
+ soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
+ soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
+// synthesis translate_off
+ dummy_d_13 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_14;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
+ soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
+ soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
+// synthesis translate_off
+ dummy_d_14 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_15;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
+ soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
+ soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
+// synthesis translate_off
+ dummy_d_15 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_16;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
+ soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
+ soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
+ soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
+// synthesis translate_off
+ dummy_d_16 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
+assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
+assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
+assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
+assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
+assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
+assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
+assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
+assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
+assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
+assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
+assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
+assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
+assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
+assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
+assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
+assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
+assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
+
+// synthesis translate_off
+reg dummy_d_17;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dqs_oe <= 1'd0;
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
+ end
+// synthesis translate_off
+ dummy_d_17 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
+assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
+
+// synthesis translate_off
+reg dummy_d_18;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_dqspattern_o0 <= 8'd0;
+ soc_a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (soc_a7ddrphy_dqspattern0) begin
+ soc_a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (soc_a7ddrphy_dqspattern1) begin
+ soc_a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (soc_a7ddrphy_wlevel_en_storage) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (soc_a7ddrphy_wlevel_strobe_re) begin
+ soc_a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+// synthesis translate_off
+ dummy_d_18 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_19;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip0_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip0_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_19 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_20;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip1_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip1_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_20 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_21;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip2_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip2_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_21 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_22;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip3_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip3_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_22 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_23;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip4_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip4_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_23 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_24;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip5_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip5_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_24 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_25;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip6_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip6_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_25 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_26;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip7_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip7_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_26 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_27;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip8_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip8_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_27 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_28;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip9_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip9_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_28 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_29;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip10_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip10_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_29 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_30;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip11_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip11_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_30 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_31;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip12_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip12_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_31 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_32;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip13_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip13_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_32 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_33;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip14_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip14_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_33 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_34;
+// synthesis translate_on
+always @(*) begin
+ soc_a7ddrphy_bitslip15_o <= 8'd0;
+ case (soc_a7ddrphy_bitslip15_value)
+ 1'd0: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
+ end
+ 1'd1: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
+ end
+ 2'd2: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
+ end
+ 2'd3: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
+ end
+ 3'd4: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
+ end
+ 3'd5: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
+ end
+ 3'd6: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
+ end
+ 3'd7: begin
+ soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_34 = dummy_s;
+// synthesis translate_on
+end
+assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address;
+assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank;
+assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n;
+assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n;
+assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n;
+assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n;
+assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke;
+assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt;
+assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n;
+assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n;
+assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata;
+assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en;
+assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask;
+assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en;
+assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
+assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
+assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address;
+assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank;
+assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n;
+assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n;
+assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n;
+assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n;
+assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke;
+assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt;
+assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n;
+assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n;
+assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata;
+assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en;
+assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask;
+assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en;
+assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
+assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
+assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address;
+assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank;
+assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n;
+assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n;
+assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n;
+assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n;
+assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke;
+assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt;
+assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n;
+assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n;
+assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata;
+assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en;
+assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask;
+assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en;
+assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
+assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
+assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address;
+assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank;
+assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n;
+assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n;
+assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n;
+assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n;
+assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke;
+assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt;
+assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n;
+assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n;
+assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata;
+assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en;
+assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask;
+assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en;
+assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
+assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
+assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address;
+assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank;
+assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n;
+assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n;
+assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n;
+assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n;
+assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke;
+assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt;
+assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n;
+assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n;
+assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata;
+assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en;
+assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask;
+assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en;
+assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata;
+assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid;
+assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address;
+assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank;
+assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n;
+assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n;
+assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n;
+assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n;
+assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke;
+assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt;
+assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n;
+assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n;
+assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata;
+assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en;
+assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask;
+assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en;
+assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata;
+assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid;
+assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address;
+assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank;
+assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n;
+assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n;
+assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n;
+assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n;
+assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke;
+assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt;
+assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n;
+assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n;
+assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata;
+assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en;
+assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask;
+assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en;
+assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata;
+assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid;
+assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address;
+assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank;
+assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n;
+assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n;
+assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n;
+assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n;
+assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke;
+assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt;
+assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n;
+assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n;
+assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata;
+assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en;
+assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask;
+assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en;
+assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata;
+assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid;
+
+// synthesis translate_off
+reg dummy_d_35;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n;
+ end else begin
+ soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_35 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_36;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n;
+ end else begin
+ soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_36 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_37;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n;
+ end else begin
+ soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_37 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_38;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p2_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_38 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_39;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n;
+ end else begin
+ soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n;
+ end
+// synthesis translate_off
+ dummy_d_39 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_40;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p2_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_40 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_41;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke;
+ end else begin
+ soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke;
+ end
+// synthesis translate_off
+ dummy_d_41 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_42;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt;
+ end else begin
+ soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt;
+ end
+// synthesis translate_off
+ dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n;
+ end else begin
+ soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n;
+ end else begin
+ soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n;
+ end
+// synthesis translate_off
+ dummy_d_44 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_45;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata;
+ end else begin
+ soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_45 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_46;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata;
+ end
+// synthesis translate_off
+ dummy_d_46 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_47;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en;
+ end else begin
+ soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_47 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_48;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_48 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_49;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask;
+ end else begin
+ soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_49 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_50;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en;
+ end else begin
+ soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_50 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_51;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_address <= 15'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_address <= soc_sdram_slave_p3_address;
+ end else begin
+ soc_sdram_master_p3_address <= soc_sdram_inti_p3_address;
+ end
+// synthesis translate_off
+ dummy_d_51 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_52;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank;
+ end else begin
+ soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank;
+ end
+// synthesis translate_off
+ dummy_d_52 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_53;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n;
+ end else begin
+ soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_53 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_54;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n;
+ end else begin
+ soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_54 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_55;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n;
+ end else begin
+ soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_55 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_56;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p3_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_56 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_57;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n;
+ end else begin
+ soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n;
+ end
+// synthesis translate_off
+ dummy_d_57 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_58;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p3_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_58 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_59;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke;
+ end else begin
+ soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke;
+ end
+// synthesis translate_off
+ dummy_d_59 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_60;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt;
+ end else begin
+ soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt;
+ end
+// synthesis translate_off
+ dummy_d_60 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_61;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n;
+ end else begin
+ soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_61 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_62;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n;
+ end else begin
+ soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n;
+ end
+// synthesis translate_off
+ dummy_d_62 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_63;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata;
+ end else begin
+ soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_63 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_64;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata;
+ end
+// synthesis translate_off
+ dummy_d_64 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_65;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en;
+ end else begin
+ soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_65 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_66;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_66 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_67;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask;
+ end else begin
+ soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_67 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_68;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p3_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en;
+ end else begin
+ soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_68 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_69;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_address <= 15'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_address <= soc_sdram_slave_p0_address;
+ end else begin
+ soc_sdram_master_p0_address <= soc_sdram_inti_p0_address;
+ end
+// synthesis translate_off
+ dummy_d_69 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_70;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank;
+ end else begin
+ soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank;
+ end
+// synthesis translate_off
+ dummy_d_70 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_71;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n;
+ end else begin
+ soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_71 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_72;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n;
+ end else begin
+ soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_72 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_73;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n;
+ end else begin
+ soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_73 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_74;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p0_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_74 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_75;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n;
+ end else begin
+ soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n;
+ end
+// synthesis translate_off
+ dummy_d_75 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_76;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p0_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_76 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_77;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke;
+ end else begin
+ soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke;
+ end
+// synthesis translate_off
+ dummy_d_77 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_78;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt;
+ end else begin
+ soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt;
+ end
+// synthesis translate_off
+ dummy_d_78 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_79;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n;
+ end else begin
+ soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_79 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_80;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n;
+ end else begin
+ soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n;
+ end
+// synthesis translate_off
+ dummy_d_80 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_81;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata;
+ end else begin
+ soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_81 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_82;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata;
+ end
+// synthesis translate_off
+ dummy_d_82 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_83;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en;
+ end else begin
+ soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_83 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_84;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_84 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_85;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask;
+ end else begin
+ soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_85 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_86;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p0_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en;
+ end else begin
+ soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_86 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_87;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_address <= 15'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_address <= soc_sdram_slave_p1_address;
+ end else begin
+ soc_sdram_master_p1_address <= soc_sdram_inti_p1_address;
+ end
+// synthesis translate_off
+ dummy_d_87 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_88;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank;
+ end else begin
+ soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank;
+ end
+// synthesis translate_off
+ dummy_d_88 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_89;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cas_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n;
+ end else begin
+ soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_89 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_90;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cs_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n;
+ end else begin
+ soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_90 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_91;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_ras_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n;
+ end else begin
+ soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_91 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_92;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p1_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_92 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_93;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_we_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n;
+ end else begin
+ soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n;
+ end
+// synthesis translate_off
+ dummy_d_93 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_slave_p1_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_cke <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke;
+ end else begin
+ soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke;
+ end
+// synthesis translate_off
+ dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_odt <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt;
+ end else begin
+ soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt;
+ end
+// synthesis translate_off
+ dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_reset_n <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n;
+ end else begin
+ soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_97 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_98;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_act_n <= 1'd1;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n;
+ end else begin
+ soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n;
+ end
+// synthesis translate_off
+ dummy_d_98 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_99;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata;
+ end else begin
+ soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_99 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_100;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_rddata <= 32'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata;
+ end
+// synthesis translate_off
+ dummy_d_100 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_101;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en;
+ end else begin
+ soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_101 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_102;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_rddata_valid <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ end else begin
+ soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_102 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_103;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_wrdata_mask <= 4'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask;
+ end else begin
+ soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_103 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_104;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p1_rddata_en <= 1'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en;
+ end else begin
+ soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en;
+ end
+// synthesis translate_off
+ dummy_d_104 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_105;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_address <= 15'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_address <= soc_sdram_slave_p2_address;
+ end else begin
+ soc_sdram_master_p2_address <= soc_sdram_inti_p2_address;
+ end
+// synthesis translate_off
+ dummy_d_105 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_106;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_master_p2_bank <= 3'd0;
+ if (soc_sdram_storage[0]) begin
+ soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank;
+ end else begin
+ soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank;
+ end
+// synthesis translate_off
+ dummy_d_106 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p0_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p1_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p2_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p3_cke = soc_sdram_storage[1];
+assign soc_sdram_inti_p0_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p1_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p2_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p3_odt = soc_sdram_storage[2];
+assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3];
+assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3];
+
+// synthesis translate_off
+reg dummy_d_107;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p0_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_107 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_108;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p0_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_108 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_109;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p0_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_109 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_110;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p0_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector0_command_issue_re) begin
+ soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p0_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_110 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage;
+assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage;
+assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]);
+assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]);
+assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage;
+assign soc_sdram_inti_p0_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_111;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p1_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_111 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_112;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p1_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_112 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_113;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p1_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_113 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_114;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p1_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector1_command_issue_re) begin
+ soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p1_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_114 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage;
+assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage;
+assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]);
+assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]);
+assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage;
+assign soc_sdram_inti_p1_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_115;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p2_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_115 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_116;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p2_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_116 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_117;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p2_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_117 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_118;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p2_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector2_command_issue_re) begin
+ soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p2_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_118 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage;
+assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage;
+assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]);
+assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]);
+assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage;
+assign soc_sdram_inti_p2_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_119;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_cas_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]);
+ end else begin
+ soc_sdram_inti_p3_cas_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_119 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_120;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_cs_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}};
+ end else begin
+ soc_sdram_inti_p3_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_120 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_121;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_ras_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]);
+ end else begin
+ soc_sdram_inti_p3_ras_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_121 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_122;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_inti_p3_we_n <= 1'd1;
+ if (soc_sdram_phaseinjector3_command_issue_re) begin
+ soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]);
+ end else begin
+ soc_sdram_inti_p3_we_n <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_122 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage;
+assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage;
+assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]);
+assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]);
+assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage;
+assign soc_sdram_inti_p3_wrdata_mask = 1'd0;
+assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid;
+assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready;
+assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we;
+assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr;
+assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock;
+assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready;
+assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid;
+assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid;
+assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready;
+assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we;
+assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr;
+assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock;
+assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready;
+assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid;
+assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid;
+assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready;
+assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we;
+assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr;
+assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock;
+assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready;
+assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid;
+assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid;
+assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready;
+assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we;
+assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr;
+assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock;
+assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready;
+assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid;
+assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid;
+assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready;
+assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we;
+assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr;
+assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock;
+assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready;
+assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid;
+assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid;
+assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready;
+assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we;
+assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr;
+assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock;
+assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready;
+assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid;
+assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid;
+assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready;
+assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we;
+assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr;
+assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock;
+assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready;
+assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid;
+assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid;
+assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready;
+assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we;
+assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr;
+assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock;
+assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready;
+assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid;
+assign soc_sdram_timer_wait = (~soc_sdram_timer_done0);
+assign soc_sdram_postponer_req_i = soc_sdram_timer_done0;
+assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o;
+assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0;
+assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done);
+assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0);
+assign soc_sdram_timer_done0 = soc_sdram_timer_done1;
+assign soc_sdram_timer_count0 = soc_sdram_timer_count1;
+assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0));
+assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0));
+assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0);
+assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1;
+assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1;
+
+// synthesis translate_off
+reg dummy_d_123;
+// synthesis translate_on
+always @(*) begin
+ vns_refresher_next_state <= 2'd0;
+ vns_refresher_next_state <= vns_refresher_state;
+ case (vns_refresher_state)
+ 1'd1: begin
+ if (soc_sdram_cmd_ready) begin
+ vns_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ vns_refresher_next_state <= 2'd3;
+ end else begin
+ vns_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_zqcs_executer_done) begin
+ vns_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (soc_sdram_wants_refresh) begin
+ vns_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_123 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_124;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_sequencer_start0 <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ if (soc_sdram_cmd_ready) begin
+ soc_sdram_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_124 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_125;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_valid <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ end else begin
+ soc_sdram_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ soc_sdram_cmd_valid <= 1'd1;
+ if (soc_sdram_zqcs_executer_done) begin
+ soc_sdram_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_125 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_126;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_zqcs_executer_start <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ soc_sdram_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_126 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_127;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_last <= 1'd0;
+ case (vns_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_sdram_sequencer_done0) begin
+ if (soc_sdram_wants_zqcs) begin
+ end else begin
+ soc_sdram_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_zqcs_executer_done) begin
+ soc_sdram_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_127 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid;
+assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid);
+assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_128;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_128 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write);
+assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
+assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
+
+// synthesis translate_off
+reg dummy_d_129;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_129 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_130;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_130 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_131;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine0_next_state <= 4'd0;
+ vns_bankmachine0_next_state <= vns_bankmachine0_state;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ if (soc_sdram_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ vns_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ if (soc_sdram_bankmachine0_cmd_ready) begin
+ vns_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine0_refresh_req)) begin
+ vns_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ vns_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin
+ vns_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_131 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_132;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_132 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_133;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_133 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_134;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_135 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_136;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_136 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_137;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_137 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_138;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_138 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_139;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_refresh_gnt <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine0_twtpcon_ready) begin
+ soc_sdram_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_139 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_140;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_140 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_141;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_open <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_141 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_142;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_row_close <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_142 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_143;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine0_row_opened) begin
+ if (soc_sdram_bankmachine0_row_hit) begin
+ soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_143 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_144;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine0_trccon_ready) begin
+ soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_144 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid;
+assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid);
+assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
+
+// synthesis translate_off
+reg dummy_d_145;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_145 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write);
+assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
+assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
+
+// synthesis translate_off
+reg dummy_d_146;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_146 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_147;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_147 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_148;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine1_next_state <= 4'd0;
+ vns_bankmachine1_next_state <= vns_bankmachine1_state;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ if (soc_sdram_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ vns_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ if (soc_sdram_bankmachine1_cmd_ready) begin
+ vns_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine1_refresh_req)) begin
+ vns_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ vns_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin
+ vns_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_148 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_149;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_149 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_150;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_150 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_151;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_151 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_152;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_152 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_153;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_153 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_154;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_154 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_155;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_155 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_156;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_refresh_gnt <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine1_twtpcon_ready) begin
+ soc_sdram_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_156 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_157;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_157 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_158;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_open <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_158 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_159;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_row_close <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_159 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_160;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine1_row_opened) begin
+ if (soc_sdram_bankmachine1_row_hit) begin
+ soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_160 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_161;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine1_trccon_ready) begin
+ soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_161 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid;
+assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid);
+assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
+
+// synthesis translate_off
+reg dummy_d_162;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_162 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write);
+assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
+assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
+
+// synthesis translate_off
+reg dummy_d_163;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_163 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_164;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_164 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_165;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine2_next_state <= 4'd0;
+ vns_bankmachine2_next_state <= vns_bankmachine2_state;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ if (soc_sdram_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ vns_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ if (soc_sdram_bankmachine2_cmd_ready) begin
+ vns_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine2_refresh_req)) begin
+ vns_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ vns_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin
+ vns_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_165 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_166;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_166 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_167;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_167 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_168;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_168 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_169;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_169 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_170;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_170 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_171;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_171 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_172;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_172 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_173;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_refresh_gnt <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine2_twtpcon_ready) begin
+ soc_sdram_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_173 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_174;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_174 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_175;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_open <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_175 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_176;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_row_close <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_176 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_177;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine2_row_opened) begin
+ if (soc_sdram_bankmachine2_row_hit) begin
+ soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_177 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_178;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine2_trccon_ready) begin
+ soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_178 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid;
+assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid);
+assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
+
+// synthesis translate_off
+reg dummy_d_179;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_179 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write);
+assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
+assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
+
+// synthesis translate_off
+reg dummy_d_180;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_180 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_181;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_181 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_182;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine3_next_state <= 4'd0;
+ vns_bankmachine3_next_state <= vns_bankmachine3_state;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ if (soc_sdram_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ vns_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ if (soc_sdram_bankmachine3_cmd_ready) begin
+ vns_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine3_refresh_req)) begin
+ vns_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ vns_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin
+ vns_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_182 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_183;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_183 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_184;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_184 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_185;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_185 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_186;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_186 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_187;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_187 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_188;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_188 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_189;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_189 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_190;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_refresh_gnt <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine3_twtpcon_ready) begin
+ soc_sdram_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_190 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_191;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_191 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_192;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_open <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_192 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_193;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_row_close <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_193 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_194;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine3_row_opened) begin
+ if (soc_sdram_bankmachine3_row_hit) begin
+ soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_194 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_195;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine3_trccon_ready) begin
+ soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_195 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid;
+assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid);
+assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
+
+// synthesis translate_off
+reg dummy_d_196;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_196 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write);
+assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
+assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
+
+// synthesis translate_off
+reg dummy_d_197;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_197 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_198;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_198 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_199;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine4_next_state <= 4'd0;
+ vns_bankmachine4_next_state <= vns_bankmachine4_state;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ if (soc_sdram_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ vns_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ if (soc_sdram_bankmachine4_cmd_ready) begin
+ vns_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine4_refresh_req)) begin
+ vns_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ vns_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin
+ vns_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_199 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_200;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_200 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_201;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_201 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_202;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_202 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_203;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_203 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_204;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_204 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_205;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_205 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_206;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_206 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_207;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_refresh_gnt <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine4_twtpcon_ready) begin
+ soc_sdram_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_207 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_208;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_208 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_209;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_open <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_209 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_210;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_row_close <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_210 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_211;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine4_row_opened) begin
+ if (soc_sdram_bankmachine4_row_hit) begin
+ soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_211 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_212;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine4_trccon_ready) begin
+ soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_212 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid;
+assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid);
+assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
+
+// synthesis translate_off
+reg dummy_d_213;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write);
+assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
+assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_214 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_215;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_215 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_216;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine5_next_state <= 4'd0;
+ vns_bankmachine5_next_state <= vns_bankmachine5_state;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ if (soc_sdram_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ vns_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ if (soc_sdram_bankmachine5_cmd_ready) begin
+ vns_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine5_refresh_req)) begin
+ vns_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ vns_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin
+ vns_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_216 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_217;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_217 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_218;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_218 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_219;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_219 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_220;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_220 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_221;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_221 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_222;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_222 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_223;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_223 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_224;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_refresh_gnt <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine5_twtpcon_ready) begin
+ soc_sdram_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_224 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_225;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_225 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_226;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_open <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_226 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_227;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_row_close <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_227 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_228;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine5_row_opened) begin
+ if (soc_sdram_bankmachine5_row_hit) begin
+ soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_228 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_229;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine5_trccon_ready) begin
+ soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_229 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid;
+assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid);
+assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
+
+// synthesis translate_off
+reg dummy_d_230;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_230 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write);
+assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
+assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
+
+// synthesis translate_off
+reg dummy_d_231;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_231 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_232;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_232 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_233;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine6_next_state <= 4'd0;
+ vns_bankmachine6_next_state <= vns_bankmachine6_state;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ if (soc_sdram_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ vns_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ if (soc_sdram_bankmachine6_cmd_ready) begin
+ vns_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine6_refresh_req)) begin
+ vns_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ vns_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin
+ vns_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_233 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_234;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_234 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_235;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_235 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_236;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_236 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_237;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_237 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_238;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_238 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_239;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_239 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_240;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_240 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_241;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_refresh_gnt <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine6_twtpcon_ready) begin
+ soc_sdram_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_241 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_242;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_242 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_243;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_open <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_243 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_244;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_row_close <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_244 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_245;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine6_row_opened) begin
+ if (soc_sdram_bankmachine6_row_hit) begin
+ soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_245 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_246;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine6_trccon_ready) begin
+ soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_246 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid;
+assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid);
+assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid);
+assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
+
+// synthesis translate_off
+reg dummy_d_247;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_a <= 15'd0;
+ if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin
+ soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ end else begin
+ soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+ end
+// synthesis translate_off
+ dummy_d_247 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write);
+assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
+assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
+
+// synthesis translate_off
+reg dummy_d_248;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_auto_precharge <= 1'd0;
+ if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
+ if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+ soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0);
+ end
+ end
+// synthesis translate_off
+ dummy_d_248 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_249;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+ end else begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
+ end
+// synthesis translate_off
+ dummy_d_249 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_250;
+// synthesis translate_on
+always @(*) begin
+ vns_bankmachine7_next_state <= 4'd0;
+ vns_bankmachine7_next_state <= vns_bankmachine7_state;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ if (soc_sdram_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ vns_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ if (soc_sdram_bankmachine7_cmd_ready) begin
+ vns_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_sdram_bankmachine7_refresh_req)) begin
+ vns_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ vns_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ vns_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ vns_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin
+ vns_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ vns_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ vns_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_250 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_251;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_251 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_252;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_252 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_253;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_253 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_254 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_255;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_255 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_256;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_256 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_257;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_257 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_258;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_refresh_gnt <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_sdram_bankmachine7_twtpcon_ready) begin
+ soc_sdram_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_258 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_259;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_259 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_260;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_open <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_260 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_261;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_row_close <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_sdram_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_261 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_262;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_sdram_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
+ if (soc_sdram_bankmachine7_row_opened) begin
+ if (soc_sdram_bankmachine7_row_hit) begin
+ soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_262 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_263;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (vns_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_sdram_bankmachine7_trccon_ready) begin
+ soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_263 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
+assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
+assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready);
+assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read));
+assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready;
+assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read));
+assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write));
+assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0);
+assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0);
+assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid;
+assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt);
+assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata};
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
+
+// synthesis translate_off
+reg dummy_d_264;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_valids <= 8'd0;
+ soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+ soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+// synthesis translate_off
+ dummy_d_264 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids;
+assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
+assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
+assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
+assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
+assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
+assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
+
+// synthesis translate_off
+reg dummy_d_265;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
+ end
+// synthesis translate_off
+ dummy_d_265 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_266;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
+ end
+// synthesis translate_off
+ dummy_d_266 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_267;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
+ if (soc_sdram_choose_cmd_cmd_valid) begin
+ soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
+ end
+// synthesis translate_off
+ dummy_d_267 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_268;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin
+ soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_268 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_269;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin
+ soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_269 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_270;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin
+ soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_270 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_271;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin
+ soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_271 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_272;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin
+ soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_272 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_273;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin
+ soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_273 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_274;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin
+ soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_274 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_275;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd0;
+ if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin
+ soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_275 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid));
+
+// synthesis translate_off
+reg dummy_d_276;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_valids <= 8'd0;
+ soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+ soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+// synthesis translate_off
+ dummy_d_276 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids;
+assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
+assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
+assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
+assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
+assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
+assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
+
+// synthesis translate_off
+reg dummy_d_277;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_cas <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
+ end
+// synthesis translate_off
+ dummy_d_277 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_278;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_ras <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
+ end
+// synthesis translate_off
+ dummy_d_278 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_279;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_payload_we <= 1'd0;
+ if (soc_sdram_choose_req_cmd_valid) begin
+ soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
+ end
+// synthesis translate_off
+ dummy_d_279 = dummy_s;
+// synthesis translate_on
+end
+assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid));
+assign soc_sdram_dfi_p0_reset_n = 1'd1;
+assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}};
+assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}};
+assign soc_sdram_dfi_p1_reset_n = 1'd1;
+assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}};
+assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}};
+assign soc_sdram_dfi_p2_reset_n = 1'd1;
+assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}};
+assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}};
+assign soc_sdram_dfi_p3_reset_n = 1'd1;
+assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}};
+assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}};
+assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]);
+
+// synthesis translate_off
+reg dummy_d_280;
+// synthesis translate_on
+always @(*) begin
+ vns_multiplexer_next_state <= 4'd0;
+ vns_multiplexer_next_state <= vns_multiplexer_state;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (soc_sdram_read_available) begin
+ if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin
+ vns_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (soc_sdram_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_cmd_last) begin
+ vns_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_twtrcon_ready) begin
+ vns_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ vns_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ vns_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ vns_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ vns_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ vns_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ vns_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ vns_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (soc_sdram_write_available) begin
+ if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin
+ vns_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (soc_sdram_go_to_refresh) begin
+ vns_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_280 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_281;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel0 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel0 <= 1'd0;
+ end
+ 2'd2: begin
+ soc_sdram_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel0 <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_281 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_282;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel1 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel1 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_282 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_283;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel2 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel2 <= 2'd2;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_283 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_284;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_want_activates <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_284 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_285;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_steerer_sel3 <= 2'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_steerer_sel3 <= 2'd2;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_steerer_sel3 <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_285 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_286;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_en0 <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_en0 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_286 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_287;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_sdram_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_287 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_288;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_cmd_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_288 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_289;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_want_reads <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_sdram_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_289 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_290;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_want_writes <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_290 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_291;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_choose_req_cmd_ready <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
+ end else begin
+ soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
+ end else begin
+ soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_291 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_292;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_en1 <= 1'd0;
+ case (vns_multiplexer_state)
+ 1'd1: begin
+ soc_sdram_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_292 = dummy_s;
+// synthesis translate_on
+end
+assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock));
+assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
+assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
+assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
+assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock));
+assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
+assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
+assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
+assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock));
+assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
+assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
+assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
+assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock));
+assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
+assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
+assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
+assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock));
+assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
+assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
+assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
+assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock));
+assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
+assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
+assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
+assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock));
+assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
+assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
+assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
+assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)};
+assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock));
+assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
+assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
+assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
+assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready));
+assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready));
+assign soc_port_wdata_ready = vns_new_master_wdata_ready2;
+assign soc_wdata_ready = vns_new_master_wdata_ready5;
+assign soc_port_rdata_valid = vns_new_master_rdata_valid8;
+assign soc_rdata_valid = vns_new_master_rdata_valid17;
+
+// synthesis translate_off
+reg dummy_d_293;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_interface_wdata_we <= 16'd0;
+ case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
+ 1'd1: begin
+ soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we;
+ end
+ 2'd2: begin
+ soc_sdram_interface_wdata_we <= soc_wdata_payload_we;
+ end
+ default: begin
+ soc_sdram_interface_wdata_we <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_293 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_294;
+// synthesis translate_on
+always @(*) begin
+ soc_sdram_interface_wdata <= 128'd0;
+ case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
+ 1'd1: begin
+ soc_sdram_interface_wdata <= soc_port_wdata_payload_data;
+ end
+ 2'd2: begin
+ soc_sdram_interface_wdata <= soc_wdata_payload_data;
+ end
+ default: begin
+ soc_sdram_interface_wdata <= 1'd0;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_294 = dummy_s;
+// synthesis translate_on
+end
+assign soc_port_rdata_payload_data = soc_sdram_interface_rdata;
+assign soc_rdata_payload_data = soc_sdram_interface_rdata;
+assign soc_address_d = soc_wb_sdram_adr;
+assign soc_counter_offset = soc_address_q;
+assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3);
+assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done)));
+assign soc_need_refill_reset = soc_end_of_burst;
+assign soc_need_refill_d = 1'd0;
+assign soc_litedram_wb_cti = 3'd7;
+assign soc_litedram_wb_adr = soc_address_q[29:2];
+assign soc_cached_sels_reset0 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_295;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop0_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0];
+ end
+// synthesis translate_off
+ dummy_d_295 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_296;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce0 <= 1'd0;
+ if (((soc_write & soc_write_sel0) | soc_refill)) begin
+ soc_cached_sels_ce0 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_296 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_297;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce0 <= 1'd0;
+ if (((soc_write & soc_write_sel0) | soc_refill)) begin
+ soc_cached_datas_ce0 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_297 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset1 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_298;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop1_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32];
+ end
+// synthesis translate_off
+ dummy_d_298 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_299;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce1 <= 1'd0;
+ if (((soc_write & soc_write_sel1) | soc_refill)) begin
+ soc_cached_sels_ce1 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_299 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_300;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce1 <= 1'd0;
+ if (((soc_write & soc_write_sel1) | soc_refill)) begin
+ soc_cached_datas_ce1 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_300 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset2 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_301;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop2_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64];
+ end
+// synthesis translate_off
+ dummy_d_301 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_302;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce2 <= 1'd0;
+ if (((soc_write & soc_write_sel2) | soc_refill)) begin
+ soc_cached_sels_ce2 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_302 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_303;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce2 <= 1'd0;
+ if (((soc_write & soc_write_sel2) | soc_refill)) begin
+ soc_cached_datas_ce2 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_303 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_reset3 = soc_counter_reset;
+
+// synthesis translate_off
+reg dummy_d_304;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_flipflop3_d <= 32'd0;
+ if (soc_write) begin
+ soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w;
+ end else begin
+ soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96];
+ end
+// synthesis translate_off
+ dummy_d_304 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel;
+
+// synthesis translate_off
+reg dummy_d_305;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_sels_ce3 <= 1'd0;
+ if (((soc_write & soc_write_sel3) | soc_refill)) begin
+ soc_cached_sels_ce3 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_305 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_306;
+// synthesis translate_on
+always @(*) begin
+ soc_cached_datas_ce3 <= 1'd0;
+ if (((soc_write & soc_write_sel3) | soc_refill)) begin
+ soc_cached_datas_ce3 <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_306 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_307;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel1 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ soc_write_sel1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_307 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_308;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel0 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ soc_write_sel0 <= 1'd1;
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_308 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_309;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel2 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_write_sel2 <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_309 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_310;
+// synthesis translate_on
+always @(*) begin
+ soc_write_sel3 <= 1'd0;
+ case ((soc_counter + soc_counter_offset))
+ 1'd0: begin
+ end
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ soc_write_sel3 <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_310 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_311;
+// synthesis translate_on
+always @(*) begin
+ soc_wb_sdram_dat_r <= 32'd0;
+ case (soc_address_q[1:0])
+ 1'd0: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q;
+ end
+ 1'd1: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q;
+ end
+ 2'd2: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q;
+ end
+ 2'd3: begin
+ soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_311 = dummy_s;
+// synthesis translate_on
+end
+assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q};
+assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q};
+
+// synthesis translate_off
+reg dummy_d_312;
+// synthesis translate_on
+always @(*) begin
+ vns_converter_next_state <= 3'd0;
+ vns_converter_next_state <= vns_converter_state;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ if (soc_counter_done) begin
+ vns_converter_next_state <= 2'd2;
+ end
+ end else begin
+ if ((~soc_wb_sdram_cyc)) begin
+ vns_converter_next_state <= 2'd2;
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_litedram_wb_ack) begin
+ vns_converter_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedram_wb_ack) begin
+ vns_converter_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ vns_converter_next_state <= 1'd0;
+ end
+ default: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ if (soc_wb_sdram_we) begin
+ vns_converter_next_state <= 1'd1;
+ end else begin
+ if (soc_need_refill_q) begin
+ vns_converter_next_state <= 2'd3;
+ end else begin
+ vns_converter_next_state <= 3'd4;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_312 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_313;
+// synthesis translate_on
+always @(*) begin
+ soc_address_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_address_ce <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_313 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_314;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_dat_w <= 128'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_dat_w <= soc_cached_data;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_314 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_315;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_sel <= 16'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_sel <= soc_cached_sel;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_315 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_316;
+// synthesis translate_on
+always @(*) begin
+ soc_counter_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_counter_ce <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_316 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_317;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_cyc <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_cyc <= 1'd1;
+ end
+ 2'd3: begin
+ soc_litedram_wb_cyc <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_317 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_318;
+// synthesis translate_on
+always @(*) begin
+ soc_counter_reset <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ soc_counter_reset <= 1'd1;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_318 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_319;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_stb <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_stb <= 1'd1;
+ end
+ 2'd3: begin
+ soc_litedram_wb_stb <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_319 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_320;
+// synthesis translate_on
+always @(*) begin
+ soc_need_refill_ce <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedram_wb_ack) begin
+ soc_need_refill_ce <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_320 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_321;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_we <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedram_wb_we <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_321 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_322;
+// synthesis translate_on
+always @(*) begin
+ soc_write <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_write <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_322 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_323;
+// synthesis translate_on
+always @(*) begin
+ soc_wb_sdram_ack <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_wb_sdram_ack <= 1'd1;
+ end else begin
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
+ soc_wb_sdram_ack <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_323 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_324;
+// synthesis translate_on
+always @(*) begin
+ soc_evict <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_evict <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_324 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_325;
+// synthesis translate_on
+always @(*) begin
+ soc_refill <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ soc_refill <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_325 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_326;
+// synthesis translate_on
+always @(*) begin
+ soc_read <= 1'd0;
+ case (vns_converter_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_read <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_326 = dummy_s;
+// synthesis translate_on
+end
+assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we);
+assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w;
+assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel;
+assign soc_port_wdata_valid = soc_wdata_converter_source_valid;
+assign soc_wdata_converter_source_ready = soc_port_wdata_ready;
+assign soc_port_wdata_first = soc_wdata_converter_source_first;
+assign soc_port_wdata_last = soc_wdata_converter_source_last;
+assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data;
+assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we;
+assign soc_rdata_converter_sink_valid = soc_port_rdata_valid;
+assign soc_port_rdata_ready = soc_rdata_converter_sink_ready;
+assign soc_rdata_converter_sink_first = soc_port_rdata_first;
+assign soc_rdata_converter_sink_last = soc_port_rdata_last;
+assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data;
+assign soc_rdata_converter_source_ready = 1'd1;
+assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data;
+assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid;
+assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first;
+assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last;
+assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready;
+assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data};
+assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid;
+assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first;
+assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last;
+assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready;
+assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
+assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
+assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid;
+assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready;
+assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first;
+assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last;
+assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data;
+assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid;
+assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready;
+assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first;
+assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last;
+assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data;
+assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
+assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid;
+assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first;
+assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last;
+assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready;
+assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data};
+assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid;
+assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first;
+assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last;
+assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready;
+assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data;
+assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid;
+assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready;
+assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first;
+assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last;
+assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data;
+assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid;
+assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready;
+assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first;
+assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last;
+assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data;
+assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
+
+// synthesis translate_off
+reg dummy_d_327;
+// synthesis translate_on
+always @(*) begin
+ vns_litedramwishbone2native_next_state <= 2'd0;
+ vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ if (soc_wdata_converter_sink_ready) begin
+ vns_litedramwishbone2native_next_state <= 1'd0;
+ end
+ end
+ 2'd2: begin
+ if (soc_rdata_converter_source_valid) begin
+ vns_litedramwishbone2native_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ if ((soc_count == 1'd0)) begin
+ if (soc_litedram_wb_we) begin
+ vns_litedramwishbone2native_next_state <= 1'd1;
+ end else begin
+ vns_litedramwishbone2native_next_state <= 2'd2;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_327 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_328;
+// synthesis translate_on
+always @(*) begin
+ soc_count_next_value_ce <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ soc_count_next_value_ce <= 1'd1;
+ if ((soc_count == 1'd0)) begin
+ soc_count_next_value_ce <= 1'd1;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_328 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_329;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_valid <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_329 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_330;
+// synthesis translate_on
+always @(*) begin
+ soc_litedram_wb_ack <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ if (soc_wdata_converter_sink_ready) begin
+ soc_litedram_wb_ack <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ if (soc_rdata_converter_source_valid) begin
+ soc_litedram_wb_ack <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_330 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_331;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_payload_we <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_payload_we <= soc_litedram_wb_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_331 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_332;
+// synthesis translate_on
+always @(*) begin
+ soc_port_cmd_payload_addr <= 25'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_332 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_333;
+// synthesis translate_on
+always @(*) begin
+ soc_count_next_value <= 1'd0;
+ case (vns_litedramwishbone2native_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
+ soc_count_next_value <= (soc_count + 1'd1);
+ if ((soc_count == 1'd0)) begin
+ soc_count_next_value <= 1'd0;
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_333 = dummy_s;
+// synthesis translate_on
+end
+assign vns_shared_adr = vns_rhs_array_muxed36;
+assign vns_shared_dat_w = vns_rhs_array_muxed37;
+assign vns_shared_sel = vns_rhs_array_muxed38;
+assign vns_shared_cyc = vns_rhs_array_muxed39;
+assign vns_shared_stb = vns_rhs_array_muxed40;
+assign vns_shared_we = vns_rhs_array_muxed41;
+assign vns_shared_cti = vns_rhs_array_muxed42;
+assign vns_shared_bte = vns_rhs_array_muxed43;
+assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r;
+assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r;
+assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0));
+assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1));
+assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0));
+assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1));
+assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc};
+
+// synthesis translate_off
+reg dummy_d_334;
+// synthesis translate_on
+always @(*) begin
+ vns_slave_sel <= 4'd0;
+ vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0);
+ vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096);
+ vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280);
+ vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64);
+// synthesis translate_off
+ dummy_d_334 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr;
+assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel;
+assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb;
+assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we;
+assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti;
+assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte;
+assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr;
+assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel;
+assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb;
+assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we;
+assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti;
+assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte;
+assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr;
+assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w;
+assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel;
+assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb;
+assign soc_litedramcore_bus_wishbone_we = vns_shared_we;
+assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti;
+assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte;
+assign soc_wb_sdram_adr = vns_shared_adr;
+assign soc_wb_sdram_dat_w = vns_shared_dat_w;
+assign soc_wb_sdram_sel = vns_shared_sel;
+assign soc_wb_sdram_stb = vns_shared_stb;
+assign soc_wb_sdram_we = vns_shared_we;
+assign soc_wb_sdram_cti = vns_shared_cti;
+assign soc_wb_sdram_bte = vns_shared_bte;
+assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]);
+assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]);
+assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]);
+assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]);
+
+// synthesis translate_off
+reg dummy_d_335;
+// synthesis translate_on
+always @(*) begin
+ vns_shared_ack <= 1'd0;
+ vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack);
+ if (vns_done) begin
+ vns_shared_ack <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_335 = dummy_s;
+// synthesis translate_on
+end
+assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err);
+
+// synthesis translate_off
+reg dummy_d_336;
+// synthesis translate_on
+always @(*) begin
+ vns_shared_dat_r <= 32'd0;
+ vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r));
+ if (vns_done) begin
+ vns_shared_dat_r <= 32'd4294967295;
+ end
+// synthesis translate_off
+ dummy_d_336 = dummy_s;
+// synthesis translate_on
+end
+assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack));
+
+// synthesis translate_off
+reg dummy_d_337;
+// synthesis translate_on
+always @(*) begin
+ vns_error <= 1'd0;
+ if (vns_done) begin
+ vns_error <= 1'd1;
+ end
+// synthesis translate_off
+ dummy_d_337 = dummy_s;
+// synthesis translate_on
+end
+assign vns_done = (vns_count == 1'd0);
+assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0);
+assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0];
+assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
+assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
+assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
+assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
+assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
+assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
+assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
+assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
+assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0];
+assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
+assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
+assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage;
+assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24];
+assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16];
+assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8];
+assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0];
+assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24];
+assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16];
+assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8];
+assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0];
+assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we;
+assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7);
+assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0));
+assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0];
+assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1));
+assign vns_csrbank1_init_done0_w = soc_init_done_storage;
+assign vns_csrbank1_init_error0_w = soc_init_error_storage;
+assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5);
+assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0];
+assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
+assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0];
+assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
+assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
+assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
+assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
+assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
+assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
+assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0];
+assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
+assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
+assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
+assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
+assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0];
+assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
+assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
+assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
+assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
+assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6);
+assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0];
+assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
+assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
+assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
+assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
+assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
+assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
+assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[6:0];
+assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
+assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
+assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
+assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
+assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
+assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
+assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
+assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
+assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
+assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
+assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
+assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
+assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
+assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
+assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
+assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
+assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
+assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
+assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
+assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
+assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
+assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
+assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
+assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
+assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
+assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
+assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[6:0];
+assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
+assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
+assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
+assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
+assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
+assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
+assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
+assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
+assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
+assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
+assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
+assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
+assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
+assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
+assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
+assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
+assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
+assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
+assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
+assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
+assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
+assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
+assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
+assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
+assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
+assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
+assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[6:0];
+assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
+assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
+assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
+assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
+assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
+assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
+assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
+assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
+assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
+assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
+assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
+assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
+assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
+assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
+assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
+assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
+assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
+assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
+assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
+assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
+assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
+assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
+assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0];
+assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
+assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
+assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0];
+assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
+assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
+assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[6:0];
+assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
+assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
+assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
+assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
+assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
+assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
+assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
+assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
+assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
+assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
+assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
+assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
+assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
+assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
+assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
+assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
+assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
+assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
+assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
+assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
+assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
+assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
+assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
+assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
+assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0];
+assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0];
+assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[14:8];
+assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0];
+assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24];
+assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16];
+assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8];
+assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0];
+assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we;
+assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0];
+assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[14:8];
+assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0];
+assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24];
+assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16];
+assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8];
+assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0];
+assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we;
+assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0];
+assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[14:8];
+assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0];
+assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24];
+assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16];
+assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8];
+assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0];
+assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we;
+assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0];
+assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[14:8];
+assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0];
+assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0];
+assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24];
+assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16];
+assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8];
+assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0];
+assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24];
+assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16];
+assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8];
+assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0];
+assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we;
+assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4);
+assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
+assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
+assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
+assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
+assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
+assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
+assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
+assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
+assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
+assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
+assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
+assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
+assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
+assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0];
+assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
+assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
+assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0];
+assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
+assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0];
+assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
+assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
+assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0];
+assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
+assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24];
+assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16];
+assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8];
+assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0];
+assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24];
+assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16];
+assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8];
+assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0];
+assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage;
+assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage;
+assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24];
+assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16];
+assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8];
+assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0];
+assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we;
+assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage;
+assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3);
+assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0];
+assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
+assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
+assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0];
+assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
+assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
+assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0];
+assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
+assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
+assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0];
+assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
+assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
+assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0];
+assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
+assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
+assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0];
+assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
+assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
+assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status;
+assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we;
+assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status;
+assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we;
+assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0];
+assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2);
+assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
+assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
+assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
+assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
+assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
+assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
+assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0];
+assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
+assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
+assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24];
+assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16];
+assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8];
+assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0];
+assign vns_adr = soc_litedramcore_interface_adr;
+assign vns_we = soc_litedramcore_interface_we;
+assign vns_dat_w = soc_litedramcore_interface_dat_w;
+assign soc_litedramcore_interface_dat_r = vns_dat_r;
+assign vns_interface0_bank_bus_adr = vns_adr;
+assign vns_interface1_bank_bus_adr = vns_adr;
+assign vns_interface2_bank_bus_adr = vns_adr;
+assign vns_interface3_bank_bus_adr = vns_adr;
+assign vns_interface4_bank_bus_adr = vns_adr;
+assign vns_interface5_bank_bus_adr = vns_adr;
+assign vns_interface6_bank_bus_adr = vns_adr;
+assign vns_interface0_bank_bus_we = vns_we;
+assign vns_interface1_bank_bus_we = vns_we;
+assign vns_interface2_bank_bus_we = vns_we;
+assign vns_interface3_bank_bus_we = vns_we;
+assign vns_interface4_bank_bus_we = vns_we;
+assign vns_interface5_bank_bus_we = vns_we;
+assign vns_interface6_bank_bus_we = vns_we;
+assign vns_interface0_bank_bus_dat_w = vns_dat_w;
+assign vns_interface1_bank_bus_dat_w = vns_dat_w;
+assign vns_interface2_bank_bus_dat_w = vns_dat_w;
+assign vns_interface3_bank_bus_dat_w = vns_dat_w;
+assign vns_interface4_bank_bus_dat_w = vns_dat_w;
+assign vns_interface5_bank_bus_dat_w = vns_dat_w;
+assign vns_interface6_bank_bus_dat_w = vns_dat_w;
+assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r);
+
+// synthesis translate_off
+reg dummy_d_338;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed0 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6];
+ end
+ default: begin
+ vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_338 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_339;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed1 <= 15'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_339 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_340;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed2 <= 3'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_340 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_341;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed3 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_341 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_342;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed4 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_342 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_343;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed5 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_343 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_344;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed0 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_344 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_345;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed1 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_345 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_346;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed2 <= 1'd0;
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_346 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_347;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed6 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0];
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1];
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2];
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3];
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4];
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5];
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6];
+ end
+ default: begin
+ vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_347 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_348;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed7 <= 15'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_348 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_349;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed8 <= 3'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_349 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_350;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed9 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_350 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_351;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed10 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_351 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_352;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed11 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_352 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_353;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed3 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_353 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_354;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed4 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_354 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_355;
+// synthesis translate_on
+always @(*) begin
+ vns_t_array_muxed5 <= 1'd0;
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_355 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_356;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed12 <= 22'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_356 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_357;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed13 <= 1'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed13 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed13 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_357 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_358;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed14 <= 1'd0;
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_358 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_359;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed15 <= 22'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_359 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_360;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed16 <= 1'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed16 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed16 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_360 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_361;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed17 <= 1'd0;
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_361 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_362;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed18 <= 22'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_362 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_363;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed19 <= 1'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed19 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed19 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_363 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_364;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed20 <= 1'd0;
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_364 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_365;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed21 <= 22'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_365 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_366;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed22 <= 1'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed22 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed22 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_366 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_367;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed23 <= 1'd0;
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_367 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_368;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed24 <= 22'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_368 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_369;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed25 <= 1'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed25 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed25 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_369 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_370;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed26 <= 1'd0;
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_370 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_371;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed27 <= 22'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_371 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_372;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed28 <= 1'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed28 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed28 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_372 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_373;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed29 <= 1'd0;
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_373 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_374;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed30 <= 22'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_374 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_375;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed31 <= 1'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed31 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed31 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_375 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_376;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed32 <= 1'd0;
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_376 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_377;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed33 <= 22'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+ end
+ default: begin
+ vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_377 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_378;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed34 <= 1'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed34 <= soc_port_cmd_payload_we;
+ end
+ default: begin
+ vns_rhs_array_muxed34 <= soc_cmd_payload_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_378 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_379;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed35 <= 1'd0;
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid);
+ end
+ default: begin
+ vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_379 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_380;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed36 <= 30'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr;
+ end
+ default: begin
+ vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_380 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_381;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed37 <= 32'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w;
+ end
+ default: begin
+ vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_381 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_382;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed38 <= 4'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel;
+ end
+ default: begin
+ vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_382 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_383;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed39 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc;
+ end
+ default: begin
+ vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_383 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_384;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed40 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb;
+ end
+ default: begin
+ vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_384 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_385;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed41 <= 1'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we;
+ end
+ default: begin
+ vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_385 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_386;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed42 <= 3'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti;
+ end
+ default: begin
+ vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_386 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_387;
+// synthesis translate_on
+always @(*) begin
+ vns_rhs_array_muxed43 <= 2'd0;
+ case (vns_grant)
+ 1'd0: begin
+ vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte;
+ end
+ default: begin
+ vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_387 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_388;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed0 <= 3'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed0 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_388 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_389;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed1 <= 15'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed1 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed1 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_389 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_390;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed2 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_390 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_391;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed3 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_391 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_392;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed4 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_392 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_393;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed5 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_393 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_394;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed6 <= 1'd0;
+ case (soc_sdram_steerer_sel0)
+ 1'd0: begin
+ vns_array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_394 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_395;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed7 <= 3'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed7 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_395 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_396;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed8 <= 15'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed8 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed8 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_396 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_397;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed9 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_397 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_398;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed10 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_398 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_399;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed11 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_399 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_400;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed12 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_400 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_401;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed13 <= 1'd0;
+ case (soc_sdram_steerer_sel1)
+ 1'd0: begin
+ vns_array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_401 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_402;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed14 <= 3'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed14 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_402 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_403;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed15 <= 15'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed15 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed15 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_403 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_404;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed16 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_404 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_405;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed17 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_405 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_406;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed18 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_406 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_407;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed19 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_407 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_408;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed20 <= 1'd0;
+ case (soc_sdram_steerer_sel2)
+ 1'd0: begin
+ vns_array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_408 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_409;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed21 <= 3'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed21 <= soc_sdram_nop_ba[2:0];
+ end
+ 1'd1: begin
+ vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0];
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_409 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_410;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed22 <= 15'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed22 <= soc_sdram_nop_a;
+ end
+ 1'd1: begin
+ vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a;
+ end
+ default: begin
+ vns_array_muxed22 <= soc_sdram_cmd_payload_a;
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_410 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_411;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed23 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_411 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_412;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed24 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_412 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_413;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed25 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+ end
+ default: begin
+ vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_413 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_414;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed26 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_414 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_415;
+// synthesis translate_on
+always @(*) begin
+ vns_array_muxed27 <= 1'd0;
+ case (soc_sdram_steerer_sel3)
+ 1'd0: begin
+ vns_array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_415 = dummy_s;
+// synthesis translate_on
+end
+assign soc_litedramcore_rx = vns_regs1;
+assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
+assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset);
+
+always @(posedge iodelay_clk) begin
+ if ((soc_reset_counter != 1'd0)) begin
+ soc_reset_counter <= (soc_reset_counter - 1'd1);
+ end else begin
+ soc_ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ soc_reset_counter <= 4'd15;
+ soc_ic_reset <= 1'd1;
+ end
+end
+
+always @(posedge sys_clk) begin
+ if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin
+ if (soc_litedramcore_soccontroller_bus_error) begin
+ soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1);
+ end
+ end
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
+ if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1;
+ end
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
+ if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1;
+ end
+ soc_litedramcore_sink_ready <= 1'd0;
+ if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin
+ soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data;
+ soc_litedramcore_tx_bitcount <= 1'd0;
+ soc_litedramcore_tx_busy <= 1'd1;
+ serial_tx <= 1'd0;
+ end else begin
+ if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin
+ soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1);
+ if ((soc_litedramcore_tx_bitcount == 4'd8)) begin
+ serial_tx <= 1'd1;
+ end else begin
+ if ((soc_litedramcore_tx_bitcount == 4'd9)) begin
+ serial_tx <= 1'd1;
+ soc_litedramcore_tx_busy <= 1'd0;
+ soc_litedramcore_sink_ready <= 1'd1;
+ end else begin
+ serial_tx <= soc_litedramcore_tx_reg[0];
+ soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]};
+ end
+ end
+ end
+ end
+ if (soc_litedramcore_tx_busy) begin
+ {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage);
+ end else begin
+ {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0;
+ end
+ soc_litedramcore_source_valid <= 1'd0;
+ soc_litedramcore_rx_r <= soc_litedramcore_rx;
+ if ((~soc_litedramcore_rx_busy)) begin
+ if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin
+ soc_litedramcore_rx_busy <= 1'd1;
+ soc_litedramcore_rx_bitcount <= 1'd0;
+ end
+ end else begin
+ if (soc_litedramcore_uart_clk_rxen) begin
+ soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1);
+ if ((soc_litedramcore_rx_bitcount == 1'd0)) begin
+ if (soc_litedramcore_rx) begin
+ soc_litedramcore_rx_busy <= 1'd0;
+ end
+ end else begin
+ if ((soc_litedramcore_rx_bitcount == 4'd9)) begin
+ soc_litedramcore_rx_busy <= 1'd0;
+ if (soc_litedramcore_rx) begin
+ soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg;
+ soc_litedramcore_source_valid <= 1'd1;
+ end
+ end else begin
+ soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]};
+ end
+ end
+ end
+ end
+ if (soc_litedramcore_rx_busy) begin
+ {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage);
+ end else begin
+ {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648;
+ end
+ if (soc_litedramcore_uart_tx_clear) begin
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ end
+ soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger;
+ if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin
+ soc_litedramcore_uart_tx_pending <= 1'd1;
+ end
+ if (soc_litedramcore_uart_rx_clear) begin
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ end
+ soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger;
+ if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin
+ soc_litedramcore_uart_rx_pending <= 1'd1;
+ end
+ if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd1;
+ end else begin
+ if (soc_litedramcore_uart_tx_fifo_re) begin
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ end
+ end
+ if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
+ soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1);
+ end
+ if (soc_litedramcore_uart_tx_fifo_do_read) begin
+ soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1);
+ end
+ if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
+ if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin
+ soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_uart_tx_fifo_do_read) begin
+ soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1);
+ end
+ end
+ if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd1;
+ end else begin
+ if (soc_litedramcore_uart_rx_fifo_re) begin
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ end
+ end
+ if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
+ soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1);
+ end
+ if (soc_litedramcore_uart_rx_fifo_do_read) begin
+ soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1);
+ end
+ if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
+ if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin
+ soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_uart_rx_fifo_do_read) begin
+ soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1);
+ end
+ end
+ if (soc_litedramcore_uart_reset) begin
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ soc_litedramcore_uart_tx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ soc_litedramcore_uart_rx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
+ end
+ if (soc_litedramcore_timer_en_storage) begin
+ if ((soc_litedramcore_timer_value == 1'd0)) begin
+ soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage;
+ end else begin
+ soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1);
+ end
+ end else begin
+ soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage;
+ end
+ if (soc_litedramcore_timer_update_value_re) begin
+ soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value;
+ end
+ if (soc_litedramcore_timer_zero_clear) begin
+ soc_litedramcore_timer_zero_pending <= 1'd0;
+ end
+ soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger;
+ if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin
+ soc_litedramcore_timer_zero_pending <= 1'd1;
+ end
+ vns_wb2csr_state <= vns_wb2csr_next_state;
+ soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
+ soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
+ soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
+ soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip0_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip1_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip2_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip3_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip4_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip5_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip6_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip7_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip8_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip9_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip10_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip11_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip12_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip13_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip14_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
+ soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
+ end
+ if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+ soc_a7ddrphy_bitslip15_value <= 1'd0;
+ end
+ soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
+ if (soc_sdram_inti_p0_rddata_valid) begin
+ soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata;
+ end
+ if (soc_sdram_inti_p1_rddata_valid) begin
+ soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata;
+ end
+ if (soc_sdram_inti_p2_rddata_valid) begin
+ soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata;
+ end
+ if (soc_sdram_inti_p3_rddata_valid) begin
+ soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata;
+ end
+ if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin
+ soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1);
+ end else begin
+ soc_sdram_timer_count1 <= 10'd781;
+ end
+ soc_sdram_postponer_req_o <= 1'd0;
+ if (soc_sdram_postponer_req_i) begin
+ soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1);
+ if ((soc_sdram_postponer_count == 1'd0)) begin
+ soc_sdram_postponer_count <= 1'd0;
+ soc_sdram_postponer_req_o <= 1'd1;
+ end
+ end
+ if (soc_sdram_sequencer_start0) begin
+ soc_sdram_sequencer_count <= 1'd0;
+ end else begin
+ if (soc_sdram_sequencer_done1) begin
+ if ((soc_sdram_sequencer_count != 1'd0)) begin
+ soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1);
+ end
+ end
+ end
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd0;
+ if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin
+ soc_sdram_cmd_payload_a <= 11'd1024;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_sequencer_counter == 2'd3)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd1;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ end
+ if ((soc_sdram_sequencer_counter == 6'd55)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd1;
+ end
+ if ((soc_sdram_sequencer_counter == 6'd55)) begin
+ soc_sdram_sequencer_counter <= 1'd0;
+ end else begin
+ if ((soc_sdram_sequencer_counter != 1'd0)) begin
+ soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1);
+ end else begin
+ if (soc_sdram_sequencer_start1) begin
+ soc_sdram_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin
+ soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1);
+ end else begin
+ soc_sdram_zqcs_timer_count1 <= 27'd99999999;
+ end
+ soc_sdram_zqcs_executer_done <= 1'd0;
+ if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin
+ soc_sdram_cmd_payload_a <= 11'd1024;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd1;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
+ soc_sdram_cmd_payload_a <= 1'd0;
+ soc_sdram_cmd_payload_ba <= 1'd0;
+ soc_sdram_cmd_payload_cas <= 1'd0;
+ soc_sdram_cmd_payload_ras <= 1'd0;
+ soc_sdram_cmd_payload_we <= 1'd0;
+ soc_sdram_zqcs_executer_done <= 1'd1;
+ end
+ if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
+ soc_sdram_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin
+ soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (soc_sdram_zqcs_executer_start) begin
+ soc_sdram_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ vns_refresher_state <= vns_refresher_next_state;
+ if (soc_sdram_bankmachine0_row_close) begin
+ soc_sdram_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine0_row_open) begin
+ soc_sdram_bankmachine0_row_opened <= 1'd1;
+ soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first;
+ soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last;
+ soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine0_twtpcon_valid) begin
+ soc_sdram_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin
+ soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine0_trccon_valid) begin
+ soc_sdram_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_trccon_ready)) begin
+ soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine0_trascon_valid) begin
+ soc_sdram_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine0_trascon_ready)) begin
+ soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine0_state <= vns_bankmachine0_next_state;
+ if (soc_sdram_bankmachine1_row_close) begin
+ soc_sdram_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine1_row_open) begin
+ soc_sdram_bankmachine1_row_opened <= 1'd1;
+ soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first;
+ soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last;
+ soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine1_twtpcon_valid) begin
+ soc_sdram_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin
+ soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine1_trccon_valid) begin
+ soc_sdram_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_trccon_ready)) begin
+ soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine1_trascon_valid) begin
+ soc_sdram_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine1_trascon_ready)) begin
+ soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine1_state <= vns_bankmachine1_next_state;
+ if (soc_sdram_bankmachine2_row_close) begin
+ soc_sdram_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine2_row_open) begin
+ soc_sdram_bankmachine2_row_opened <= 1'd1;
+ soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first;
+ soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last;
+ soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine2_twtpcon_valid) begin
+ soc_sdram_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin
+ soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine2_trccon_valid) begin
+ soc_sdram_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_trccon_ready)) begin
+ soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine2_trascon_valid) begin
+ soc_sdram_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine2_trascon_ready)) begin
+ soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine2_state <= vns_bankmachine2_next_state;
+ if (soc_sdram_bankmachine3_row_close) begin
+ soc_sdram_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine3_row_open) begin
+ soc_sdram_bankmachine3_row_opened <= 1'd1;
+ soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first;
+ soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last;
+ soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine3_twtpcon_valid) begin
+ soc_sdram_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin
+ soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine3_trccon_valid) begin
+ soc_sdram_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_trccon_ready)) begin
+ soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine3_trascon_valid) begin
+ soc_sdram_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine3_trascon_ready)) begin
+ soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine3_state <= vns_bankmachine3_next_state;
+ if (soc_sdram_bankmachine4_row_close) begin
+ soc_sdram_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine4_row_open) begin
+ soc_sdram_bankmachine4_row_opened <= 1'd1;
+ soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first;
+ soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last;
+ soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine4_twtpcon_valid) begin
+ soc_sdram_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin
+ soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine4_trccon_valid) begin
+ soc_sdram_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_trccon_ready)) begin
+ soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine4_trascon_valid) begin
+ soc_sdram_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine4_trascon_ready)) begin
+ soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine4_state <= vns_bankmachine4_next_state;
+ if (soc_sdram_bankmachine5_row_close) begin
+ soc_sdram_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine5_row_open) begin
+ soc_sdram_bankmachine5_row_opened <= 1'd1;
+ soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first;
+ soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last;
+ soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine5_twtpcon_valid) begin
+ soc_sdram_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin
+ soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine5_trccon_valid) begin
+ soc_sdram_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_trccon_ready)) begin
+ soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine5_trascon_valid) begin
+ soc_sdram_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine5_trascon_ready)) begin
+ soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine5_state <= vns_bankmachine5_next_state;
+ if (soc_sdram_bankmachine6_row_close) begin
+ soc_sdram_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine6_row_open) begin
+ soc_sdram_bankmachine6_row_opened <= 1'd1;
+ soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first;
+ soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last;
+ soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine6_twtpcon_valid) begin
+ soc_sdram_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin
+ soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine6_trccon_valid) begin
+ soc_sdram_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_trccon_ready)) begin
+ soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine6_trascon_valid) begin
+ soc_sdram_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine6_trascon_ready)) begin
+ soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine6_state <= vns_bankmachine6_next_state;
+ if (soc_sdram_bankmachine7_row_close) begin
+ soc_sdram_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (soc_sdram_bankmachine7_row_open) begin
+ soc_sdram_bankmachine7_row_opened <= 1'd1;
+ soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+ end
+ end
+ if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+ end
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+ end
+ if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
+ if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+ end
+ end else begin
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+ end
+ end
+ if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin
+ soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid;
+ soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first;
+ soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last;
+ soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
+ soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+ end
+ if (soc_sdram_bankmachine7_twtpcon_valid) begin
+ soc_sdram_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin
+ soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine7_trccon_valid) begin
+ soc_sdram_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_trccon_ready)) begin
+ soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_bankmachine7_trascon_valid) begin
+ soc_sdram_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_bankmachine7_trascon_ready)) begin
+ soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1);
+ if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_bankmachine7_state <= vns_bankmachine7_next_state;
+ if ((~soc_sdram_en0)) begin
+ soc_sdram_time0 <= 5'd31;
+ end else begin
+ if ((~soc_sdram_max_time0)) begin
+ soc_sdram_time0 <= (soc_sdram_time0 - 1'd1);
+ end
+ end
+ if ((~soc_sdram_en1)) begin
+ soc_sdram_time1 <= 4'd15;
+ end else begin
+ if ((~soc_sdram_max_time1)) begin
+ soc_sdram_time1 <= (soc_sdram_time1 - 1'd1);
+ end
+ end
+ if (soc_sdram_choose_cmd_ce) begin
+ case (soc_sdram_choose_cmd_grant)
+ 1'd0: begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_sdram_choose_cmd_request[7]) begin
+ soc_sdram_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_sdram_choose_cmd_request[0]) begin
+ soc_sdram_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_cmd_request[1]) begin
+ soc_sdram_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_cmd_request[2]) begin
+ soc_sdram_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_cmd_request[3]) begin
+ soc_sdram_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_cmd_request[4]) begin
+ soc_sdram_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_cmd_request[5]) begin
+ soc_sdram_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_cmd_request[6]) begin
+ soc_sdram_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (soc_sdram_choose_req_ce) begin
+ case (soc_sdram_choose_req_grant)
+ 1'd0: begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_sdram_choose_req_request[7]) begin
+ soc_sdram_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_sdram_choose_req_request[0]) begin
+ soc_sdram_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_sdram_choose_req_request[1]) begin
+ soc_sdram_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_sdram_choose_req_request[2]) begin
+ soc_sdram_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_sdram_choose_req_request[3]) begin
+ soc_sdram_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_sdram_choose_req_request[4]) begin
+ soc_sdram_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_sdram_choose_req_request[5]) begin
+ soc_sdram_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_sdram_choose_req_request[6]) begin
+ soc_sdram_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ soc_sdram_dfi_p0_cs_n <= 1'd0;
+ soc_sdram_dfi_p0_bank <= vns_array_muxed0;
+ soc_sdram_dfi_p0_address <= vns_array_muxed1;
+ soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
+ soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
+ soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
+ soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
+ soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
+ soc_sdram_dfi_p1_cs_n <= 1'd0;
+ soc_sdram_dfi_p1_bank <= vns_array_muxed7;
+ soc_sdram_dfi_p1_address <= vns_array_muxed8;
+ soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
+ soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
+ soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
+ soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
+ soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
+ soc_sdram_dfi_p2_cs_n <= 1'd0;
+ soc_sdram_dfi_p2_bank <= vns_array_muxed14;
+ soc_sdram_dfi_p2_address <= vns_array_muxed15;
+ soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
+ soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
+ soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
+ soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
+ soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
+ soc_sdram_dfi_p3_cs_n <= 1'd0;
+ soc_sdram_dfi_p3_bank <= vns_array_muxed21;
+ soc_sdram_dfi_p3_address <= vns_array_muxed22;
+ soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
+ soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
+ soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
+ soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
+ soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
+ if (soc_sdram_trrdcon_valid) begin
+ soc_sdram_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ soc_sdram_trrdcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_trrdcon_ready)) begin
+ soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1);
+ if ((soc_sdram_trrdcon_count == 1'd1)) begin
+ soc_sdram_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid};
+ if ((soc_sdram_tfawcon_count < 3'd4)) begin
+ if ((soc_sdram_tfawcon_count == 2'd3)) begin
+ soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid);
+ end else begin
+ soc_sdram_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (soc_sdram_tccdcon_valid) begin
+ soc_sdram_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ soc_sdram_tccdcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_tccdcon_ready)) begin
+ soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1);
+ if ((soc_sdram_tccdcon_count == 1'd1)) begin
+ soc_sdram_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_sdram_twtrcon_valid) begin
+ soc_sdram_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ soc_sdram_twtrcon_ready <= 1'd1;
+ end else begin
+ soc_sdram_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_sdram_twtrcon_ready)) begin
+ soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1);
+ if ((soc_sdram_twtrcon_count == 1'd1)) begin
+ soc_sdram_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ vns_multiplexer_state <= vns_multiplexer_next_state;
+ vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
+ vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
+ vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready));
+ vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3;
+ vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4;
+ vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
+ vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
+ vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
+ vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
+ vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
+ vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
+ vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
+ vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
+ vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid));
+ vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9;
+ vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10;
+ vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11;
+ vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12;
+ vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13;
+ vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14;
+ vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15;
+ vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16;
+ if (vns_roundrobin0_ce) begin
+ case (vns_roundrobin0_grant)
+ 1'd0: begin
+ if (vns_roundrobin0_request[1]) begin
+ vns_roundrobin0_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin0_request[0]) begin
+ vns_roundrobin0_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin1_ce) begin
+ case (vns_roundrobin1_grant)
+ 1'd0: begin
+ if (vns_roundrobin1_request[1]) begin
+ vns_roundrobin1_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin1_request[0]) begin
+ vns_roundrobin1_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin2_ce) begin
+ case (vns_roundrobin2_grant)
+ 1'd0: begin
+ if (vns_roundrobin2_request[1]) begin
+ vns_roundrobin2_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin2_request[0]) begin
+ vns_roundrobin2_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin3_ce) begin
+ case (vns_roundrobin3_grant)
+ 1'd0: begin
+ if (vns_roundrobin3_request[1]) begin
+ vns_roundrobin3_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin3_request[0]) begin
+ vns_roundrobin3_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin4_ce) begin
+ case (vns_roundrobin4_grant)
+ 1'd0: begin
+ if (vns_roundrobin4_request[1]) begin
+ vns_roundrobin4_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin4_request[0]) begin
+ vns_roundrobin4_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin5_ce) begin
+ case (vns_roundrobin5_grant)
+ 1'd0: begin
+ if (vns_roundrobin5_request[1]) begin
+ vns_roundrobin5_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin5_request[0]) begin
+ vns_roundrobin5_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin6_ce) begin
+ case (vns_roundrobin6_grant)
+ 1'd0: begin
+ if (vns_roundrobin6_request[1]) begin
+ vns_roundrobin6_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin6_request[0]) begin
+ vns_roundrobin6_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (vns_roundrobin7_ce) begin
+ case (vns_roundrobin7_grant)
+ 1'd0: begin
+ if (vns_roundrobin7_request[1]) begin
+ vns_roundrobin7_grant <= 1'd1;
+ end
+ end
+ 1'd1: begin
+ if (vns_roundrobin7_request[0]) begin
+ vns_roundrobin7_grant <= 1'd0;
+ end
+ end
+ endcase
+ end
+ if (soc_counter_reset) begin
+ soc_counter <= 1'd0;
+ end else begin
+ if (soc_counter_ce) begin
+ soc_counter <= (soc_counter + 1'd1);
+ end
+ end
+ if (soc_address_ce) begin
+ soc_address_q <= soc_address_d;
+ end
+ if (soc_address_reset) begin
+ soc_address_q <= 30'd0;
+ end
+ if (soc_need_refill_ce) begin
+ soc_need_refill_q <= soc_need_refill_d;
+ end
+ if (soc_need_refill_reset) begin
+ soc_need_refill_q <= 1'd1;
+ end
+ vns_converter_state <= vns_converter_next_state;
+ if (soc_cached_datas_ce0) begin
+ soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d;
+ end
+ if (soc_cached_datas_reset0) begin
+ soc_cached_datas_flipflop0_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce1) begin
+ soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d;
+ end
+ if (soc_cached_datas_reset1) begin
+ soc_cached_datas_flipflop1_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce2) begin
+ soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d;
+ end
+ if (soc_cached_datas_reset2) begin
+ soc_cached_datas_flipflop2_q <= 32'd0;
+ end
+ if (soc_cached_datas_ce3) begin
+ soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d;
+ end
+ if (soc_cached_datas_reset3) begin
+ soc_cached_datas_flipflop3_q <= 32'd0;
+ end
+ if (soc_cached_sels_ce0) begin
+ soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d;
+ end
+ if (soc_cached_sels_reset0) begin
+ soc_cached_sels_flipflop0_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce1) begin
+ soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d;
+ end
+ if (soc_cached_sels_reset1) begin
+ soc_cached_sels_flipflop1_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce2) begin
+ soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d;
+ end
+ if (soc_cached_sels_reset2) begin
+ soc_cached_sels_flipflop2_q <= 4'd0;
+ end
+ if (soc_cached_sels_ce3) begin
+ soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d;
+ end
+ if (soc_cached_sels_reset3) begin
+ soc_cached_sels_flipflop3_q <= 4'd0;
+ end
+ vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
+ if (soc_count_next_value_ce) begin
+ soc_count <= soc_count_next_value;
+ end
+ case (vns_grant)
+ 1'd0: begin
+ if ((~vns_request[0])) begin
+ if (vns_request[1]) begin
+ vns_grant <= 1'd1;
+ end
+ end
+ end
+ 1'd1: begin
+ if ((~vns_request[1])) begin
+ if (vns_request[0]) begin
+ vns_grant <= 1'd0;
+ end
+ end
+ end
+ endcase
+ vns_slave_sel_r <= vns_slave_sel;
+ if (vns_wait) begin
+ if ((~vns_done)) begin
+ vns_count <= (vns_count - 1'd1);
+ end
+ end else begin
+ vns_count <= 20'd1000000;
+ end
+ vns_interface0_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank0_sel) begin
+ case (vns_interface0_bank_bus_adr[3:0])
+ 1'd0: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w;
+ end
+ 1'd1: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w;
+ end
+ 2'd2: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w;
+ end
+ 2'd3: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w;
+ end
+ 3'd4: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w;
+ end
+ 3'd5: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w;
+ end
+ 3'd6: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w;
+ end
+ 3'd7: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w;
+ end
+ 4'd8: begin
+ vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank0_reset0_re) begin
+ soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r;
+ end
+ soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re;
+ if (vns_csrbank0_scratch3_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r;
+ end
+ if (vns_csrbank0_scratch2_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r;
+ end
+ if (vns_csrbank0_scratch1_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r;
+ end
+ if (vns_csrbank0_scratch0_re) begin
+ soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r;
+ end
+ soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re;
+ vns_interface1_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank1_sel) begin
+ case (vns_interface1_bank_bus_adr[0])
+ 1'd0: begin
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w;
+ end
+ 1'd1: begin
+ vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank1_init_done0_re) begin
+ soc_init_done_storage <= vns_csrbank1_init_done0_r;
+ end
+ soc_init_done_re <= vns_csrbank1_init_done0_re;
+ if (vns_csrbank1_init_error0_re) begin
+ soc_init_error_storage <= vns_csrbank1_init_error0_r;
+ end
+ soc_init_error_re <= vns_csrbank1_init_error0_re;
+ vns_interface2_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank2_sel) begin
+ case (vns_interface2_bank_bus_adr[3:0])
+ 1'd0: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w;
+ end
+ 1'd1: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w;
+ end
+ 2'd2: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
+ end
+ 2'd3: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
+ end
+ 3'd4: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
+ end
+ 3'd5: begin
+ vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w;
+ end
+ 3'd6: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd7: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
+ end
+ 4'd8: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd9: begin
+ vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
+ end
+ endcase
+ end
+ if (vns_csrbank2_half_sys8x_taps0_re) begin
+ soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r;
+ end
+ soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re;
+ if (vns_csrbank2_wlevel_en0_re) begin
+ soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r;
+ end
+ soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re;
+ if (vns_csrbank2_dly_sel0_re) begin
+ soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r;
+ end
+ soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re;
+ vns_interface3_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank3_sel) begin
+ case (vns_interface3_bank_bus_adr[5:0])
+ 1'd0: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w;
+ end
+ 1'd1: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w;
+ end
+ 3'd4: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w;
+ end
+ 3'd5: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w;
+ end
+ 3'd6: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w;
+ end
+ 3'd7: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w;
+ end
+ 4'd8: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w;
+ end
+ 4'd9: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w;
+ end
+ 4'd10: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w;
+ end
+ 4'd11: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w;
+ end
+ 4'd12: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w;
+ end
+ 4'd13: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w;
+ end
+ 4'd14: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w;
+ end
+ 4'd15: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w;
+ end
+ 5'd16: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w;
+ end
+ 5'd17: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w;
+ end
+ 5'd18: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w;
+ end
+ 5'd19: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w;
+ end
+ 5'd20: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w;
+ end
+ 5'd21: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w;
+ end
+ 5'd22: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w;
+ end
+ 5'd23: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w;
+ end
+ 5'd24: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w;
+ end
+ 5'd25: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w;
+ end
+ 5'd26: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w;
+ end
+ 5'd27: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w;
+ end
+ 5'd28: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w;
+ end
+ 5'd29: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w;
+ end
+ 5'd30: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w;
+ end
+ 5'd31: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w;
+ end
+ 6'd32: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w;
+ end
+ 6'd33: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w;
+ end
+ 6'd34: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w;
+ end
+ 6'd35: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w;
+ end
+ 6'd36: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w;
+ end
+ 6'd37: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w;
+ end
+ 6'd38: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w;
+ end
+ 6'd39: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w;
+ end
+ 6'd40: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w;
+ end
+ 6'd41: begin
+ vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w;
+ end
+ 6'd42: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w;
+ end
+ 6'd43: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w;
+ end
+ 6'd44: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w;
+ end
+ 6'd45: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w;
+ end
+ 6'd46: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w;
+ end
+ 6'd47: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w;
+ end
+ 6'd48: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w;
+ end
+ 6'd49: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w;
+ end
+ 6'd50: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w;
+ end
+ 6'd51: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w;
+ end
+ 6'd52: begin
+ vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank3_dfii_control0_re) begin
+ soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r;
+ end
+ soc_sdram_re <= vns_csrbank3_dfii_control0_re;
+ if (vns_csrbank3_dfii_pi0_command0_re) begin
+ soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r;
+ end
+ soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re;
+ if (vns_csrbank3_dfii_pi0_address1_re) begin
+ soc_sdram_phaseinjector0_address_storage[14:8] <= vns_csrbank3_dfii_pi0_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi0_address0_re) begin
+ soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r;
+ end
+ soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re;
+ if (vns_csrbank3_dfii_pi0_baddress0_re) begin
+ soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r;
+ end
+ soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re;
+ if (vns_csrbank3_dfii_pi0_wrdata3_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata2_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata1_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi0_wrdata0_re) begin
+ soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r;
+ end
+ soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re;
+ if (vns_csrbank3_dfii_pi1_command0_re) begin
+ soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r;
+ end
+ soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re;
+ if (vns_csrbank3_dfii_pi1_address1_re) begin
+ soc_sdram_phaseinjector1_address_storage[14:8] <= vns_csrbank3_dfii_pi1_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi1_address0_re) begin
+ soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r;
+ end
+ soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re;
+ if (vns_csrbank3_dfii_pi1_baddress0_re) begin
+ soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r;
+ end
+ soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re;
+ if (vns_csrbank3_dfii_pi1_wrdata3_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata2_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata1_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi1_wrdata0_re) begin
+ soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r;
+ end
+ soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re;
+ if (vns_csrbank3_dfii_pi2_command0_re) begin
+ soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r;
+ end
+ soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re;
+ if (vns_csrbank3_dfii_pi2_address1_re) begin
+ soc_sdram_phaseinjector2_address_storage[14:8] <= vns_csrbank3_dfii_pi2_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi2_address0_re) begin
+ soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r;
+ end
+ soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re;
+ if (vns_csrbank3_dfii_pi2_baddress0_re) begin
+ soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r;
+ end
+ soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re;
+ if (vns_csrbank3_dfii_pi2_wrdata3_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata2_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata1_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi2_wrdata0_re) begin
+ soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r;
+ end
+ soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re;
+ if (vns_csrbank3_dfii_pi3_command0_re) begin
+ soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r;
+ end
+ soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re;
+ if (vns_csrbank3_dfii_pi3_address1_re) begin
+ soc_sdram_phaseinjector3_address_storage[14:8] <= vns_csrbank3_dfii_pi3_address1_r;
+ end
+ if (vns_csrbank3_dfii_pi3_address0_re) begin
+ soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r;
+ end
+ soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re;
+ if (vns_csrbank3_dfii_pi3_baddress0_re) begin
+ soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r;
+ end
+ soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re;
+ if (vns_csrbank3_dfii_pi3_wrdata3_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata2_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata1_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r;
+ end
+ if (vns_csrbank3_dfii_pi3_wrdata0_re) begin
+ soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r;
+ end
+ soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re;
+ vns_interface4_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank4_sel) begin
+ case (vns_interface4_bank_bus_adr[4:0])
+ 1'd0: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w;
+ end
+ 1'd1: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w;
+ end
+ 2'd2: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w;
+ end
+ 2'd3: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w;
+ end
+ 3'd4: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w;
+ end
+ 3'd5: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w;
+ end
+ 3'd6: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w;
+ end
+ 3'd7: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w;
+ end
+ 4'd8: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w;
+ end
+ 4'd9: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w;
+ end
+ 4'd10: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w;
+ end
+ 4'd11: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w;
+ end
+ 4'd12: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w;
+ end
+ 4'd13: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w;
+ end
+ 4'd14: begin
+ vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w;
+ end
+ 4'd15: begin
+ vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w;
+ end
+ 5'd16: begin
+ vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank4_load3_re) begin
+ soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r;
+ end
+ if (vns_csrbank4_load2_re) begin
+ soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r;
+ end
+ if (vns_csrbank4_load1_re) begin
+ soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r;
+ end
+ if (vns_csrbank4_load0_re) begin
+ soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r;
+ end
+ soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re;
+ if (vns_csrbank4_reload3_re) begin
+ soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r;
+ end
+ if (vns_csrbank4_reload2_re) begin
+ soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r;
+ end
+ if (vns_csrbank4_reload1_re) begin
+ soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r;
+ end
+ if (vns_csrbank4_reload0_re) begin
+ soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r;
+ end
+ soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re;
+ if (vns_csrbank4_en0_re) begin
+ soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r;
+ end
+ soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re;
+ if (vns_csrbank4_update_value0_re) begin
+ soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r;
+ end
+ soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re;
+ if (vns_csrbank4_ev_enable0_re) begin
+ soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r;
+ end
+ soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re;
+ vns_interface5_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank5_sel) begin
+ case (vns_interface5_bank_bus_adr[2:0])
+ 1'd0: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w;
+ end
+ 1'd1: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w;
+ end
+ 2'd2: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w;
+ end
+ 2'd3: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w;
+ end
+ 3'd4: begin
+ vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w;
+ end
+ 3'd5: begin
+ vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank5_ev_enable0_re) begin
+ soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r;
+ end
+ soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re;
+ vns_interface6_bank_bus_dat_r <= 1'd0;
+ if (vns_csrbank6_sel) begin
+ case (vns_interface6_bank_bus_adr[1:0])
+ 1'd0: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w;
+ end
+ 1'd1: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w;
+ end
+ 2'd2: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w;
+ end
+ 2'd3: begin
+ vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w;
+ end
+ endcase
+ end
+ if (vns_csrbank6_tuning_word3_re) begin
+ soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r;
+ end
+ if (vns_csrbank6_tuning_word2_re) begin
+ soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r;
+ end
+ if (vns_csrbank6_tuning_word1_re) begin
+ soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r;
+ end
+ if (vns_csrbank6_tuning_word0_re) begin
+ soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r;
+ end
+ soc_litedramcore_re <= vns_csrbank6_tuning_word0_re;
+ if (sys_rst) begin
+ soc_litedramcore_soccontroller_reset_storage <= 1'd0;
+ soc_litedramcore_soccontroller_reset_re <= 1'd0;
+ soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896;
+ soc_litedramcore_soccontroller_scratch_re <= 1'd0;
+ soc_litedramcore_soccontroller_bus_errors <= 32'd0;
+ soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
+ soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
+ serial_tx <= 1'd1;
+ soc_litedramcore_storage <= 32'd4947802;
+ soc_litedramcore_re <= 1'd0;
+ soc_litedramcore_sink_ready <= 1'd0;
+ soc_litedramcore_uart_clk_txen <= 1'd0;
+ soc_litedramcore_tx_busy <= 1'd0;
+ soc_litedramcore_source_valid <= 1'd0;
+ soc_litedramcore_uart_clk_rxen <= 1'd0;
+ soc_litedramcore_rx_r <= 1'd0;
+ soc_litedramcore_rx_busy <= 1'd0;
+ soc_litedramcore_uart_tx_pending <= 1'd0;
+ soc_litedramcore_uart_tx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_rx_pending <= 1'd0;
+ soc_litedramcore_uart_rx_old_trigger <= 1'd0;
+ soc_litedramcore_uart_eventmanager_storage <= 2'd0;
+ soc_litedramcore_uart_eventmanager_re <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
+ soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
+ soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
+ soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
+ soc_litedramcore_timer_load_storage <= 32'd0;
+ soc_litedramcore_timer_load_re <= 1'd0;
+ soc_litedramcore_timer_reload_storage <= 32'd0;
+ soc_litedramcore_timer_reload_re <= 1'd0;
+ soc_litedramcore_timer_en_storage <= 1'd0;
+ soc_litedramcore_timer_en_re <= 1'd0;
+ soc_litedramcore_timer_update_value_storage <= 1'd0;
+ soc_litedramcore_timer_update_value_re <= 1'd0;
+ soc_litedramcore_timer_value_status <= 32'd0;
+ soc_litedramcore_timer_zero_pending <= 1'd0;
+ soc_litedramcore_timer_zero_old_trigger <= 1'd0;
+ soc_litedramcore_timer_eventmanager_storage <= 1'd0;
+ soc_litedramcore_timer_eventmanager_re <= 1'd0;
+ soc_litedramcore_timer_value <= 32'd0;
+ soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ soc_a7ddrphy_wlevel_en_storage <= 1'd0;
+ soc_a7ddrphy_wlevel_en_re <= 1'd0;
+ soc_a7ddrphy_dly_sel_storage <= 2'd0;
+ soc_a7ddrphy_dly_sel_re <= 1'd0;
+ soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+ soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
+ soc_a7ddrphy_dqspattern_o1 <= 8'd0;
+ soc_a7ddrphy_dq_oe_delayed <= 1'd0;
+ soc_a7ddrphy_bitslip0_value <= 3'd0;
+ soc_a7ddrphy_bitslip1_value <= 3'd0;
+ soc_a7ddrphy_bitslip2_value <= 3'd0;
+ soc_a7ddrphy_bitslip3_value <= 3'd0;
+ soc_a7ddrphy_bitslip4_value <= 3'd0;
+ soc_a7ddrphy_bitslip5_value <= 3'd0;
+ soc_a7ddrphy_bitslip6_value <= 3'd0;
+ soc_a7ddrphy_bitslip7_value <= 3'd0;
+ soc_a7ddrphy_bitslip8_value <= 3'd0;
+ soc_a7ddrphy_bitslip9_value <= 3'd0;
+ soc_a7ddrphy_bitslip10_value <= 3'd0;
+ soc_a7ddrphy_bitslip11_value <= 3'd0;
+ soc_a7ddrphy_bitslip12_value <= 3'd0;
+ soc_a7ddrphy_bitslip13_value <= 3'd0;
+ soc_a7ddrphy_bitslip14_value <= 3'd0;
+ soc_a7ddrphy_bitslip15_value <= 3'd0;
+ soc_a7ddrphy_rddata_en_last <= 8'd0;
+ soc_a7ddrphy_wrdata_en_last <= 4'd0;
+ soc_sdram_storage <= 4'd0;
+ soc_sdram_re <= 1'd0;
+ soc_sdram_phaseinjector0_command_storage <= 6'd0;
+ soc_sdram_phaseinjector0_command_re <= 1'd0;
+ soc_sdram_phaseinjector0_address_re <= 1'd0;
+ soc_sdram_phaseinjector0_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector0_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector0_status <= 32'd0;
+ soc_sdram_phaseinjector1_command_storage <= 6'd0;
+ soc_sdram_phaseinjector1_command_re <= 1'd0;
+ soc_sdram_phaseinjector1_address_re <= 1'd0;
+ soc_sdram_phaseinjector1_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector1_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector1_status <= 32'd0;
+ soc_sdram_phaseinjector2_command_storage <= 6'd0;
+ soc_sdram_phaseinjector2_command_re <= 1'd0;
+ soc_sdram_phaseinjector2_address_re <= 1'd0;
+ soc_sdram_phaseinjector2_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector2_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector2_status <= 32'd0;
+ soc_sdram_phaseinjector3_command_storage <= 6'd0;
+ soc_sdram_phaseinjector3_command_re <= 1'd0;
+ soc_sdram_phaseinjector3_address_re <= 1'd0;
+ soc_sdram_phaseinjector3_baddress_re <= 1'd0;
+ soc_sdram_phaseinjector3_wrdata_re <= 1'd0;
+ soc_sdram_phaseinjector3_status <= 32'd0;
+ soc_sdram_dfi_p0_address <= 15'd0;
+ soc_sdram_dfi_p0_bank <= 3'd0;
+ soc_sdram_dfi_p0_cas_n <= 1'd1;
+ soc_sdram_dfi_p0_cs_n <= 1'd1;
+ soc_sdram_dfi_p0_ras_n <= 1'd1;
+ soc_sdram_dfi_p0_we_n <= 1'd1;
+ soc_sdram_dfi_p0_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p0_rddata_en <= 1'd0;
+ soc_sdram_dfi_p1_address <= 15'd0;
+ soc_sdram_dfi_p1_bank <= 3'd0;
+ soc_sdram_dfi_p1_cas_n <= 1'd1;
+ soc_sdram_dfi_p1_cs_n <= 1'd1;
+ soc_sdram_dfi_p1_ras_n <= 1'd1;
+ soc_sdram_dfi_p1_we_n <= 1'd1;
+ soc_sdram_dfi_p1_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p1_rddata_en <= 1'd0;
+ soc_sdram_dfi_p2_address <= 15'd0;
+ soc_sdram_dfi_p2_bank <= 3'd0;
+ soc_sdram_dfi_p2_cas_n <= 1'd1;
+ soc_sdram_dfi_p2_cs_n <= 1'd1;
+ soc_sdram_dfi_p2_ras_n <= 1'd1;
+ soc_sdram_dfi_p2_we_n <= 1'd1;
+ soc_sdram_dfi_p2_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p2_rddata_en <= 1'd0;
+ soc_sdram_dfi_p3_address <= 15'd0;
+ soc_sdram_dfi_p3_bank <= 3'd0;
+ soc_sdram_dfi_p3_cas_n <= 1'd1;
+ soc_sdram_dfi_p3_cs_n <= 1'd1;
+ soc_sdram_dfi_p3_ras_n <= 1'd1;
+ soc_sdram_dfi_p3_we_n <= 1'd1;
+ soc_sdram_dfi_p3_wrdata_en <= 1'd0;
+ soc_sdram_dfi_p3_rddata_en <= 1'd0;
+ soc_sdram_timer_count1 <= 10'd781;
+ soc_sdram_postponer_req_o <= 1'd0;
+ soc_sdram_postponer_count <= 1'd0;
+ soc_sdram_sequencer_done1 <= 1'd0;
+ soc_sdram_sequencer_counter <= 6'd0;
+ soc_sdram_sequencer_count <= 1'd0;
+ soc_sdram_zqcs_timer_count1 <= 27'd99999999;
+ soc_sdram_zqcs_executer_done <= 1'd0;
+ soc_sdram_zqcs_executer_counter <= 5'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine0_row <= 15'd0;
+ soc_sdram_bankmachine0_row_opened <= 1'd0;
+ soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine0_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine0_trccon_count <= 3'd0;
+ soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine0_trascon_count <= 3'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine1_row <= 15'd0;
+ soc_sdram_bankmachine1_row_opened <= 1'd0;
+ soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine1_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine1_trccon_count <= 3'd0;
+ soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine1_trascon_count <= 3'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine2_row <= 15'd0;
+ soc_sdram_bankmachine2_row_opened <= 1'd0;
+ soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine2_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine2_trccon_count <= 3'd0;
+ soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine2_trascon_count <= 3'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine3_row <= 15'd0;
+ soc_sdram_bankmachine3_row_opened <= 1'd0;
+ soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine3_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine3_trccon_count <= 3'd0;
+ soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine3_trascon_count <= 3'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine4_row <= 15'd0;
+ soc_sdram_bankmachine4_row_opened <= 1'd0;
+ soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine4_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine4_trccon_count <= 3'd0;
+ soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine4_trascon_count <= 3'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine5_row <= 15'd0;
+ soc_sdram_bankmachine5_row_opened <= 1'd0;
+ soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine5_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine5_trccon_count <= 3'd0;
+ soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine5_trascon_count <= 3'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine6_row <= 15'd0;
+ soc_sdram_bankmachine6_row_opened <= 1'd0;
+ soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine6_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine6_trccon_count <= 3'd0;
+ soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine6_trascon_count <= 3'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+ soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+ soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+ soc_sdram_bankmachine7_row <= 15'd0;
+ soc_sdram_bankmachine7_row_opened <= 1'd0;
+ soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+ soc_sdram_bankmachine7_twtpcon_count <= 3'd0;
+ soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+ soc_sdram_bankmachine7_trccon_count <= 3'd0;
+ soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+ soc_sdram_bankmachine7_trascon_count <= 3'd0;
+ soc_sdram_choose_cmd_grant <= 3'd0;
+ soc_sdram_choose_req_grant <= 3'd0;
+ soc_sdram_trrdcon_ready <= 1'd1;
+ soc_sdram_trrdcon_count <= 1'd0;
+ soc_sdram_tfawcon_ready <= 1'd1;
+ soc_sdram_tfawcon_window <= 5'd0;
+ soc_sdram_tccdcon_ready <= 1'd1;
+ soc_sdram_tccdcon_count <= 1'd0;
+ soc_sdram_twtrcon_ready <= 1'd1;
+ soc_sdram_twtrcon_count <= 3'd0;
+ soc_sdram_time0 <= 5'd0;
+ soc_sdram_time1 <= 4'd0;
+ soc_address_q <= 30'd0;
+ soc_counter <= 2'd0;
+ soc_need_refill_q <= 1'd1;
+ soc_cached_datas_flipflop0_q <= 32'd0;
+ soc_cached_datas_flipflop1_q <= 32'd0;
+ soc_cached_datas_flipflop2_q <= 32'd0;
+ soc_cached_datas_flipflop3_q <= 32'd0;
+ soc_cached_sels_flipflop0_q <= 4'd0;
+ soc_cached_sels_flipflop1_q <= 4'd0;
+ soc_cached_sels_flipflop2_q <= 4'd0;
+ soc_cached_sels_flipflop3_q <= 4'd0;
+ soc_count <= 1'd0;
+ soc_init_done_storage <= 1'd0;
+ soc_init_done_re <= 1'd0;
+ soc_init_error_storage <= 1'd0;
+ soc_init_error_re <= 1'd0;
+ vns_wb2csr_state <= 1'd0;
+ vns_refresher_state <= 2'd0;
+ vns_bankmachine0_state <= 4'd0;
+ vns_bankmachine1_state <= 4'd0;
+ vns_bankmachine2_state <= 4'd0;
+ vns_bankmachine3_state <= 4'd0;
+ vns_bankmachine4_state <= 4'd0;
+ vns_bankmachine5_state <= 4'd0;
+ vns_bankmachine6_state <= 4'd0;
+ vns_bankmachine7_state <= 4'd0;
+ vns_multiplexer_state <= 4'd0;
+ vns_roundrobin0_grant <= 1'd0;
+ vns_roundrobin1_grant <= 1'd0;
+ vns_roundrobin2_grant <= 1'd0;
+ vns_roundrobin3_grant <= 1'd0;
+ vns_roundrobin4_grant <= 1'd0;
+ vns_roundrobin5_grant <= 1'd0;
+ vns_roundrobin6_grant <= 1'd0;
+ vns_roundrobin7_grant <= 1'd0;
+ vns_new_master_wdata_ready0 <= 1'd0;
+ vns_new_master_wdata_ready1 <= 1'd0;
+ vns_new_master_wdata_ready2 <= 1'd0;
+ vns_new_master_wdata_ready3 <= 1'd0;
+ vns_new_master_wdata_ready4 <= 1'd0;
+ vns_new_master_wdata_ready5 <= 1'd0;
+ vns_new_master_rdata_valid0 <= 1'd0;
+ vns_new_master_rdata_valid1 <= 1'd0;
+ vns_new_master_rdata_valid2 <= 1'd0;
+ vns_new_master_rdata_valid3 <= 1'd0;
+ vns_new_master_rdata_valid4 <= 1'd0;
+ vns_new_master_rdata_valid5 <= 1'd0;
+ vns_new_master_rdata_valid6 <= 1'd0;
+ vns_new_master_rdata_valid7 <= 1'd0;
+ vns_new_master_rdata_valid8 <= 1'd0;
+ vns_new_master_rdata_valid9 <= 1'd0;
+ vns_new_master_rdata_valid10 <= 1'd0;
+ vns_new_master_rdata_valid11 <= 1'd0;
+ vns_new_master_rdata_valid12 <= 1'd0;
+ vns_new_master_rdata_valid13 <= 1'd0;
+ vns_new_master_rdata_valid14 <= 1'd0;
+ vns_new_master_rdata_valid15 <= 1'd0;
+ vns_new_master_rdata_valid16 <= 1'd0;
+ vns_new_master_rdata_valid17 <= 1'd0;
+ vns_converter_state <= 3'd0;
+ vns_litedramwishbone2native_state <= 2'd0;
+ vns_grant <= 1'd0;
+ vns_slave_sel_r <= 4'd0;
+ vns_count <= 20'd1000000;
+ end
+ vns_regs0 <= serial_rx;
+ vns_regs1 <= vns_regs0;
+end
+
+reg [31:0] mem[0:6143];
+reg [31:0] memdat;
+always @(posedge sys_clk) begin
+ memdat <= mem[soc_litedramcore_litedramcore_adr];
+end
+
+assign soc_litedramcore_litedramcore_dat_r = memdat;
+
+initial begin
+ $readmemh("litedram_core.init", mem);
+end
+
+reg [31:0] mem_1[0:1023];
+reg [9:0] memadr;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_ram_we[0])
+ mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0];
+ if (soc_litedramcore_ram_we[1])
+ mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8];
+ if (soc_litedramcore_ram_we[2])
+ mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16];
+ if (soc_litedramcore_ram_we[3])
+ mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24];
+ memadr <= soc_litedramcore_ram_adr;
+end
+
+assign soc_litedramcore_ram_dat_r = mem_1[memadr];
+
+initial begin
+ $readmemh("mem_1.init", mem_1);
+end
+
+reg [9:0] storage[0:15];
+reg [9:0] memdat_1;
+reg [9:0] memdat_2;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_tx_fifo_wrport_we)
+ storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w;
+ memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_tx_fifo_rdport_re)
+ memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr];
+end
+
+assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1;
+assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2;
+
+reg [9:0] storage_1[0:15];
+reg [9:0] memdat_3;
+reg [9:0] memdat_4;
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_rx_fifo_wrport_we)
+ storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w;
+ memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+ if (soc_litedramcore_uart_rx_fifo_rdport_re)
+ memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr];
+end
+
+assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3;
+assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4;
+
+BUFG BUFG(
+ .I(soc_s7pll0_clkout0),
+ .O(soc_s7pll0_clkout_buf0)
+);
+
+BUFG BUFG_1(
+ .I(soc_s7pll0_clkout1),
+ .O(soc_s7pll0_clkout_buf1)
+);
+
+BUFG BUFG_2(
+ .I(soc_s7pll0_clkout2),
+ .O(soc_s7pll0_clkout_buf2)
+);
+
+BUFG BUFG_3(
+ .I(soc_s7pll1_clkout),
+ .O(soc_s7pll1_clkout_buf)
+);
+
+IDELAYCTRL IDELAYCTRL(
+ .REFCLK(iodelay_clk),
+ .RST(soc_ic_reset)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(1'd0),
+ .D2(1'd1),
+ .D3(1'd0),
+ .D4(1'd1),
+ .D5(1'd0),
+ .D6(1'd1),
+ .D7(1'd0),
+ .D8(1'd1),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
+);
+
+OBUFDS OBUFDS(
+ .I(soc_a7ddrphy_sd_clk_se_nodelay),
+ .O(ddram_clk_p),
+ .OB(ddram_clk_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_1 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[0]),
+ .D2(soc_a7ddrphy_dfi_p0_address[0]),
+ .D3(soc_a7ddrphy_dfi_p1_address[0]),
+ .D4(soc_a7ddrphy_dfi_p1_address[0]),
+ .D5(soc_a7ddrphy_dfi_p2_address[0]),
+ .D6(soc_a7ddrphy_dfi_p2_address[0]),
+ .D7(soc_a7ddrphy_dfi_p3_address[0]),
+ .D8(soc_a7ddrphy_dfi_p3_address[0]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_2 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[1]),
+ .D2(soc_a7ddrphy_dfi_p0_address[1]),
+ .D3(soc_a7ddrphy_dfi_p1_address[1]),
+ .D4(soc_a7ddrphy_dfi_p1_address[1]),
+ .D5(soc_a7ddrphy_dfi_p2_address[1]),
+ .D6(soc_a7ddrphy_dfi_p2_address[1]),
+ .D7(soc_a7ddrphy_dfi_p3_address[1]),
+ .D8(soc_a7ddrphy_dfi_p3_address[1]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_3 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[2]),
+ .D2(soc_a7ddrphy_dfi_p0_address[2]),
+ .D3(soc_a7ddrphy_dfi_p1_address[2]),
+ .D4(soc_a7ddrphy_dfi_p1_address[2]),
+ .D5(soc_a7ddrphy_dfi_p2_address[2]),
+ .D6(soc_a7ddrphy_dfi_p2_address[2]),
+ .D7(soc_a7ddrphy_dfi_p3_address[2]),
+ .D8(soc_a7ddrphy_dfi_p3_address[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[2])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_4 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[3]),
+ .D2(soc_a7ddrphy_dfi_p0_address[3]),
+ .D3(soc_a7ddrphy_dfi_p1_address[3]),
+ .D4(soc_a7ddrphy_dfi_p1_address[3]),
+ .D5(soc_a7ddrphy_dfi_p2_address[3]),
+ .D6(soc_a7ddrphy_dfi_p2_address[3]),
+ .D7(soc_a7ddrphy_dfi_p3_address[3]),
+ .D8(soc_a7ddrphy_dfi_p3_address[3]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[3])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_5 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[4]),
+ .D2(soc_a7ddrphy_dfi_p0_address[4]),
+ .D3(soc_a7ddrphy_dfi_p1_address[4]),
+ .D4(soc_a7ddrphy_dfi_p1_address[4]),
+ .D5(soc_a7ddrphy_dfi_p2_address[4]),
+ .D6(soc_a7ddrphy_dfi_p2_address[4]),
+ .D7(soc_a7ddrphy_dfi_p3_address[4]),
+ .D8(soc_a7ddrphy_dfi_p3_address[4]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[4])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_6 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[5]),
+ .D2(soc_a7ddrphy_dfi_p0_address[5]),
+ .D3(soc_a7ddrphy_dfi_p1_address[5]),
+ .D4(soc_a7ddrphy_dfi_p1_address[5]),
+ .D5(soc_a7ddrphy_dfi_p2_address[5]),
+ .D6(soc_a7ddrphy_dfi_p2_address[5]),
+ .D7(soc_a7ddrphy_dfi_p3_address[5]),
+ .D8(soc_a7ddrphy_dfi_p3_address[5]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[5])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_7 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[6]),
+ .D2(soc_a7ddrphy_dfi_p0_address[6]),
+ .D3(soc_a7ddrphy_dfi_p1_address[6]),
+ .D4(soc_a7ddrphy_dfi_p1_address[6]),
+ .D5(soc_a7ddrphy_dfi_p2_address[6]),
+ .D6(soc_a7ddrphy_dfi_p2_address[6]),
+ .D7(soc_a7ddrphy_dfi_p3_address[6]),
+ .D8(soc_a7ddrphy_dfi_p3_address[6]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[6])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_8 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[7]),
+ .D2(soc_a7ddrphy_dfi_p0_address[7]),
+ .D3(soc_a7ddrphy_dfi_p1_address[7]),
+ .D4(soc_a7ddrphy_dfi_p1_address[7]),
+ .D5(soc_a7ddrphy_dfi_p2_address[7]),
+ .D6(soc_a7ddrphy_dfi_p2_address[7]),
+ .D7(soc_a7ddrphy_dfi_p3_address[7]),
+ .D8(soc_a7ddrphy_dfi_p3_address[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[7])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_9 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[8]),
+ .D2(soc_a7ddrphy_dfi_p0_address[8]),
+ .D3(soc_a7ddrphy_dfi_p1_address[8]),
+ .D4(soc_a7ddrphy_dfi_p1_address[8]),
+ .D5(soc_a7ddrphy_dfi_p2_address[8]),
+ .D6(soc_a7ddrphy_dfi_p2_address[8]),
+ .D7(soc_a7ddrphy_dfi_p3_address[8]),
+ .D8(soc_a7ddrphy_dfi_p3_address[8]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[8])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_10 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[9]),
+ .D2(soc_a7ddrphy_dfi_p0_address[9]),
+ .D3(soc_a7ddrphy_dfi_p1_address[9]),
+ .D4(soc_a7ddrphy_dfi_p1_address[9]),
+ .D5(soc_a7ddrphy_dfi_p2_address[9]),
+ .D6(soc_a7ddrphy_dfi_p2_address[9]),
+ .D7(soc_a7ddrphy_dfi_p3_address[9]),
+ .D8(soc_a7ddrphy_dfi_p3_address[9]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[9])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_11 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[10]),
+ .D2(soc_a7ddrphy_dfi_p0_address[10]),
+ .D3(soc_a7ddrphy_dfi_p1_address[10]),
+ .D4(soc_a7ddrphy_dfi_p1_address[10]),
+ .D5(soc_a7ddrphy_dfi_p2_address[10]),
+ .D6(soc_a7ddrphy_dfi_p2_address[10]),
+ .D7(soc_a7ddrphy_dfi_p3_address[10]),
+ .D8(soc_a7ddrphy_dfi_p3_address[10]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[10])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_12 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[11]),
+ .D2(soc_a7ddrphy_dfi_p0_address[11]),
+ .D3(soc_a7ddrphy_dfi_p1_address[11]),
+ .D4(soc_a7ddrphy_dfi_p1_address[11]),
+ .D5(soc_a7ddrphy_dfi_p2_address[11]),
+ .D6(soc_a7ddrphy_dfi_p2_address[11]),
+ .D7(soc_a7ddrphy_dfi_p3_address[11]),
+ .D8(soc_a7ddrphy_dfi_p3_address[11]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[11])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_13 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[12]),
+ .D2(soc_a7ddrphy_dfi_p0_address[12]),
+ .D3(soc_a7ddrphy_dfi_p1_address[12]),
+ .D4(soc_a7ddrphy_dfi_p1_address[12]),
+ .D5(soc_a7ddrphy_dfi_p2_address[12]),
+ .D6(soc_a7ddrphy_dfi_p2_address[12]),
+ .D7(soc_a7ddrphy_dfi_p3_address[12]),
+ .D8(soc_a7ddrphy_dfi_p3_address[12]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[12])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_14 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[13]),
+ .D2(soc_a7ddrphy_dfi_p0_address[13]),
+ .D3(soc_a7ddrphy_dfi_p1_address[13]),
+ .D4(soc_a7ddrphy_dfi_p1_address[13]),
+ .D5(soc_a7ddrphy_dfi_p2_address[13]),
+ .D6(soc_a7ddrphy_dfi_p2_address[13]),
+ .D7(soc_a7ddrphy_dfi_p3_address[13]),
+ .D8(soc_a7ddrphy_dfi_p3_address[13]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[13])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_15 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_address[14]),
+ .D2(soc_a7ddrphy_dfi_p0_address[14]),
+ .D3(soc_a7ddrphy_dfi_p1_address[14]),
+ .D4(soc_a7ddrphy_dfi_p1_address[14]),
+ .D5(soc_a7ddrphy_dfi_p2_address[14]),
+ .D6(soc_a7ddrphy_dfi_p2_address[14]),
+ .D7(soc_a7ddrphy_dfi_p3_address[14]),
+ .D8(soc_a7ddrphy_dfi_p3_address[14]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_a[14])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_16 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[0]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[0]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[0]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[0]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[0]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_17 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[1]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[1]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[1]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[1]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[1]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_18 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D2(soc_a7ddrphy_dfi_p0_bank[2]),
+ .D3(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D4(soc_a7ddrphy_dfi_p1_bank[2]),
+ .D5(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D6(soc_a7ddrphy_dfi_p2_bank[2]),
+ .D7(soc_a7ddrphy_dfi_p3_bank[2]),
+ .D8(soc_a7ddrphy_dfi_p3_bank[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ba[2])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_19 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_ras_n),
+ .D2(soc_a7ddrphy_dfi_p0_ras_n),
+ .D3(soc_a7ddrphy_dfi_p1_ras_n),
+ .D4(soc_a7ddrphy_dfi_p1_ras_n),
+ .D5(soc_a7ddrphy_dfi_p2_ras_n),
+ .D6(soc_a7ddrphy_dfi_p2_ras_n),
+ .D7(soc_a7ddrphy_dfi_p3_ras_n),
+ .D8(soc_a7ddrphy_dfi_p3_ras_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_ras_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_20 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cas_n),
+ .D2(soc_a7ddrphy_dfi_p0_cas_n),
+ .D3(soc_a7ddrphy_dfi_p1_cas_n),
+ .D4(soc_a7ddrphy_dfi_p1_cas_n),
+ .D5(soc_a7ddrphy_dfi_p2_cas_n),
+ .D6(soc_a7ddrphy_dfi_p2_cas_n),
+ .D7(soc_a7ddrphy_dfi_p3_cas_n),
+ .D8(soc_a7ddrphy_dfi_p3_cas_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cas_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_21 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_we_n),
+ .D2(soc_a7ddrphy_dfi_p0_we_n),
+ .D3(soc_a7ddrphy_dfi_p1_we_n),
+ .D4(soc_a7ddrphy_dfi_p1_we_n),
+ .D5(soc_a7ddrphy_dfi_p2_we_n),
+ .D6(soc_a7ddrphy_dfi_p2_we_n),
+ .D7(soc_a7ddrphy_dfi_p3_we_n),
+ .D8(soc_a7ddrphy_dfi_p3_we_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_we_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_22 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cke),
+ .D2(soc_a7ddrphy_dfi_p0_cke),
+ .D3(soc_a7ddrphy_dfi_p1_cke),
+ .D4(soc_a7ddrphy_dfi_p1_cke),
+ .D5(soc_a7ddrphy_dfi_p2_cke),
+ .D6(soc_a7ddrphy_dfi_p2_cke),
+ .D7(soc_a7ddrphy_dfi_p3_cke),
+ .D8(soc_a7ddrphy_dfi_p3_cke),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cke)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_23 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_odt),
+ .D2(soc_a7ddrphy_dfi_p0_odt),
+ .D3(soc_a7ddrphy_dfi_p1_odt),
+ .D4(soc_a7ddrphy_dfi_p1_odt),
+ .D5(soc_a7ddrphy_dfi_p2_odt),
+ .D6(soc_a7ddrphy_dfi_p2_odt),
+ .D7(soc_a7ddrphy_dfi_p3_odt),
+ .D8(soc_a7ddrphy_dfi_p3_odt),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_odt)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_24 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_reset_n),
+ .D2(soc_a7ddrphy_dfi_p0_reset_n),
+ .D3(soc_a7ddrphy_dfi_p1_reset_n),
+ .D4(soc_a7ddrphy_dfi_p1_reset_n),
+ .D5(soc_a7ddrphy_dfi_p2_reset_n),
+ .D6(soc_a7ddrphy_dfi_p2_reset_n),
+ .D7(soc_a7ddrphy_dfi_p3_reset_n),
+ .D8(soc_a7ddrphy_dfi_p3_reset_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_reset_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_25 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_cs_n),
+ .D2(soc_a7ddrphy_dfi_p0_cs_n),
+ .D3(soc_a7ddrphy_dfi_p1_cs_n),
+ .D4(soc_a7ddrphy_dfi_p1_cs_n),
+ .D5(soc_a7ddrphy_dfi_p2_cs_n),
+ .D6(soc_a7ddrphy_dfi_p2_cs_n),
+ .D7(soc_a7ddrphy_dfi_p3_cs_n),
+ .D8(soc_a7ddrphy_dfi_p3_cs_n),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_cs_n)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_26 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_dm[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_27 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .OQ(ddram_dm[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_28 (
+ .CLK(sys4x_dqs_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+ .TCE(1'd1),
+ .OFB(soc_a7ddrphy0),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay0),
+ .TQ(soc_a7ddrphy_dqs_t0)
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("FIXED"),
+ .IDELAY_VALUE(4'd8),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2 (
+ .IDATAIN(soc_a7ddrphy_dqs_i[0]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
+);
+
+IOBUFDS IOBUFDS(
+ .I(soc_a7ddrphy_dqs_o_no_delay0),
+ .T(soc_a7ddrphy_dqs_t0),
+ .IO(ddram_dqs_p[0]),
+ .IOB(ddram_dqs_n[0]),
+ .O(soc_a7ddrphy_dqs_i[0])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_29 (
+ .CLK(sys4x_dqs_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dqspattern_o1[0]),
+ .D2(soc_a7ddrphy_dqspattern_o1[1]),
+ .D3(soc_a7ddrphy_dqspattern_o1[2]),
+ .D4(soc_a7ddrphy_dqspattern_o1[3]),
+ .D5(soc_a7ddrphy_dqspattern_o1[4]),
+ .D6(soc_a7ddrphy_dqspattern_o1[5]),
+ .D7(soc_a7ddrphy_dqspattern_o1[6]),
+ .D8(soc_a7ddrphy_dqspattern_o1[7]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+ .TCE(1'd1),
+ .OFB(soc_a7ddrphy1),
+ .OQ(soc_a7ddrphy_dqs_o_no_delay1),
+ .TQ(soc_a7ddrphy_dqs_t1)
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("FIXED"),
+ .IDELAY_VALUE(4'd8),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_1 (
+ .IDATAIN(soc_a7ddrphy_dqs_i[1]),
+ .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
+);
+
+IOBUFDS IOBUFDS_1(
+ .I(soc_a7ddrphy_dqs_o_no_delay1),
+ .T(soc_a7ddrphy_dqs_t1),
+ .IO(ddram_dqs_p[1]),
+ .IOB(ddram_dqs_n[1]),
+ .O(soc_a7ddrphy_dqs_i[1])
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_30 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay0),
+ .TQ(soc_a7ddrphy_dq_t0)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed0),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data0[7]),
+ .Q2(soc_a7ddrphy_dq_i_data0[6]),
+ .Q3(soc_a7ddrphy_dq_i_data0[5]),
+ .Q4(soc_a7ddrphy_dq_i_data0[4]),
+ .Q5(soc_a7ddrphy_dq_i_data0[3]),
+ .Q6(soc_a7ddrphy_dq_i_data0[2]),
+ .Q7(soc_a7ddrphy_dq_i_data0[1]),
+ .Q8(soc_a7ddrphy_dq_i_data0[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_2 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
+);
+
+IOBUF IOBUF(
+ .I(soc_a7ddrphy_dq_o_nodelay0),
+ .T(soc_a7ddrphy_dq_t0),
+ .IO(ddram_dq[0]),
+ .O(soc_a7ddrphy_dq_i_nodelay0)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_31 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay1),
+ .TQ(soc_a7ddrphy_dq_t1)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_1 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed1),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data1[7]),
+ .Q2(soc_a7ddrphy_dq_i_data1[6]),
+ .Q3(soc_a7ddrphy_dq_i_data1[5]),
+ .Q4(soc_a7ddrphy_dq_i_data1[4]),
+ .Q5(soc_a7ddrphy_dq_i_data1[3]),
+ .Q6(soc_a7ddrphy_dq_i_data1[2]),
+ .Q7(soc_a7ddrphy_dq_i_data1[1]),
+ .Q8(soc_a7ddrphy_dq_i_data1[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_3 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
+);
+
+IOBUF IOBUF_1(
+ .I(soc_a7ddrphy_dq_o_nodelay1),
+ .T(soc_a7ddrphy_dq_t1),
+ .IO(ddram_dq[1]),
+ .O(soc_a7ddrphy_dq_i_nodelay1)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_32 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay2),
+ .TQ(soc_a7ddrphy_dq_t2)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_2 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed2),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data2[7]),
+ .Q2(soc_a7ddrphy_dq_i_data2[6]),
+ .Q3(soc_a7ddrphy_dq_i_data2[5]),
+ .Q4(soc_a7ddrphy_dq_i_data2[4]),
+ .Q5(soc_a7ddrphy_dq_i_data2[3]),
+ .Q6(soc_a7ddrphy_dq_i_data2[2]),
+ .Q7(soc_a7ddrphy_dq_i_data2[1]),
+ .Q8(soc_a7ddrphy_dq_i_data2[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_4 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
+);
+
+IOBUF IOBUF_2(
+ .I(soc_a7ddrphy_dq_o_nodelay2),
+ .T(soc_a7ddrphy_dq_t2),
+ .IO(ddram_dq[2]),
+ .O(soc_a7ddrphy_dq_i_nodelay2)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_33 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay3),
+ .TQ(soc_a7ddrphy_dq_t3)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_3 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed3),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data3[7]),
+ .Q2(soc_a7ddrphy_dq_i_data3[6]),
+ .Q3(soc_a7ddrphy_dq_i_data3[5]),
+ .Q4(soc_a7ddrphy_dq_i_data3[4]),
+ .Q5(soc_a7ddrphy_dq_i_data3[3]),
+ .Q6(soc_a7ddrphy_dq_i_data3[2]),
+ .Q7(soc_a7ddrphy_dq_i_data3[1]),
+ .Q8(soc_a7ddrphy_dq_i_data3[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_5 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
+);
+
+IOBUF IOBUF_3(
+ .I(soc_a7ddrphy_dq_o_nodelay3),
+ .T(soc_a7ddrphy_dq_t3),
+ .IO(ddram_dq[3]),
+ .O(soc_a7ddrphy_dq_i_nodelay3)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_34 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay4),
+ .TQ(soc_a7ddrphy_dq_t4)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_4 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed4),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data4[7]),
+ .Q2(soc_a7ddrphy_dq_i_data4[6]),
+ .Q3(soc_a7ddrphy_dq_i_data4[5]),
+ .Q4(soc_a7ddrphy_dq_i_data4[4]),
+ .Q5(soc_a7ddrphy_dq_i_data4[3]),
+ .Q6(soc_a7ddrphy_dq_i_data4[2]),
+ .Q7(soc_a7ddrphy_dq_i_data4[1]),
+ .Q8(soc_a7ddrphy_dq_i_data4[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_6 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
+);
+
+IOBUF IOBUF_4(
+ .I(soc_a7ddrphy_dq_o_nodelay4),
+ .T(soc_a7ddrphy_dq_t4),
+ .IO(ddram_dq[4]),
+ .O(soc_a7ddrphy_dq_i_nodelay4)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_35 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay5),
+ .TQ(soc_a7ddrphy_dq_t5)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_5 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed5),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data5[7]),
+ .Q2(soc_a7ddrphy_dq_i_data5[6]),
+ .Q3(soc_a7ddrphy_dq_i_data5[5]),
+ .Q4(soc_a7ddrphy_dq_i_data5[4]),
+ .Q5(soc_a7ddrphy_dq_i_data5[3]),
+ .Q6(soc_a7ddrphy_dq_i_data5[2]),
+ .Q7(soc_a7ddrphy_dq_i_data5[1]),
+ .Q8(soc_a7ddrphy_dq_i_data5[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_7 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
+);
+
+IOBUF IOBUF_5(
+ .I(soc_a7ddrphy_dq_o_nodelay5),
+ .T(soc_a7ddrphy_dq_t5),
+ .IO(ddram_dq[5]),
+ .O(soc_a7ddrphy_dq_i_nodelay5)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_36 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay6),
+ .TQ(soc_a7ddrphy_dq_t6)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_6 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed6),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data6[7]),
+ .Q2(soc_a7ddrphy_dq_i_data6[6]),
+ .Q3(soc_a7ddrphy_dq_i_data6[5]),
+ .Q4(soc_a7ddrphy_dq_i_data6[4]),
+ .Q5(soc_a7ddrphy_dq_i_data6[3]),
+ .Q6(soc_a7ddrphy_dq_i_data6[2]),
+ .Q7(soc_a7ddrphy_dq_i_data6[1]),
+ .Q8(soc_a7ddrphy_dq_i_data6[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_8 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
+);
+
+IOBUF IOBUF_6(
+ .I(soc_a7ddrphy_dq_o_nodelay6),
+ .T(soc_a7ddrphy_dq_t6),
+ .IO(ddram_dq[6]),
+ .O(soc_a7ddrphy_dq_i_nodelay6)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_37 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay7),
+ .TQ(soc_a7ddrphy_dq_t7)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_7 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed7),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data7[7]),
+ .Q2(soc_a7ddrphy_dq_i_data7[6]),
+ .Q3(soc_a7ddrphy_dq_i_data7[5]),
+ .Q4(soc_a7ddrphy_dq_i_data7[4]),
+ .Q5(soc_a7ddrphy_dq_i_data7[3]),
+ .Q6(soc_a7ddrphy_dq_i_data7[2]),
+ .Q7(soc_a7ddrphy_dq_i_data7[1]),
+ .Q8(soc_a7ddrphy_dq_i_data7[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_9 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
+);
+
+IOBUF IOBUF_7(
+ .I(soc_a7ddrphy_dq_o_nodelay7),
+ .T(soc_a7ddrphy_dq_t7),
+ .IO(ddram_dq[7]),
+ .O(soc_a7ddrphy_dq_i_nodelay7)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_38 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay8),
+ .TQ(soc_a7ddrphy_dq_t8)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_8 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed8),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data8[7]),
+ .Q2(soc_a7ddrphy_dq_i_data8[6]),
+ .Q3(soc_a7ddrphy_dq_i_data8[5]),
+ .Q4(soc_a7ddrphy_dq_i_data8[4]),
+ .Q5(soc_a7ddrphy_dq_i_data8[3]),
+ .Q6(soc_a7ddrphy_dq_i_data8[2]),
+ .Q7(soc_a7ddrphy_dq_i_data8[1]),
+ .Q8(soc_a7ddrphy_dq_i_data8[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_10 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
+);
+
+IOBUF IOBUF_8(
+ .I(soc_a7ddrphy_dq_o_nodelay8),
+ .T(soc_a7ddrphy_dq_t8),
+ .IO(ddram_dq[8]),
+ .O(soc_a7ddrphy_dq_i_nodelay8)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_39 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay9),
+ .TQ(soc_a7ddrphy_dq_t9)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_9 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed9),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data9[7]),
+ .Q2(soc_a7ddrphy_dq_i_data9[6]),
+ .Q3(soc_a7ddrphy_dq_i_data9[5]),
+ .Q4(soc_a7ddrphy_dq_i_data9[4]),
+ .Q5(soc_a7ddrphy_dq_i_data9[3]),
+ .Q6(soc_a7ddrphy_dq_i_data9[2]),
+ .Q7(soc_a7ddrphy_dq_i_data9[1]),
+ .Q8(soc_a7ddrphy_dq_i_data9[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_11 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
+);
+
+IOBUF IOBUF_9(
+ .I(soc_a7ddrphy_dq_o_nodelay9),
+ .T(soc_a7ddrphy_dq_t9),
+ .IO(ddram_dq[9]),
+ .O(soc_a7ddrphy_dq_i_nodelay9)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_40 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay10),
+ .TQ(soc_a7ddrphy_dq_t10)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_10 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed10),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data10[7]),
+ .Q2(soc_a7ddrphy_dq_i_data10[6]),
+ .Q3(soc_a7ddrphy_dq_i_data10[5]),
+ .Q4(soc_a7ddrphy_dq_i_data10[4]),
+ .Q5(soc_a7ddrphy_dq_i_data10[3]),
+ .Q6(soc_a7ddrphy_dq_i_data10[2]),
+ .Q7(soc_a7ddrphy_dq_i_data10[1]),
+ .Q8(soc_a7ddrphy_dq_i_data10[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_12 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
+);
+
+IOBUF IOBUF_10(
+ .I(soc_a7ddrphy_dq_o_nodelay10),
+ .T(soc_a7ddrphy_dq_t10),
+ .IO(ddram_dq[10]),
+ .O(soc_a7ddrphy_dq_i_nodelay10)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_41 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay11),
+ .TQ(soc_a7ddrphy_dq_t11)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_11 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed11),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data11[7]),
+ .Q2(soc_a7ddrphy_dq_i_data11[6]),
+ .Q3(soc_a7ddrphy_dq_i_data11[5]),
+ .Q4(soc_a7ddrphy_dq_i_data11[4]),
+ .Q5(soc_a7ddrphy_dq_i_data11[3]),
+ .Q6(soc_a7ddrphy_dq_i_data11[2]),
+ .Q7(soc_a7ddrphy_dq_i_data11[1]),
+ .Q8(soc_a7ddrphy_dq_i_data11[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_13 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
+);
+
+IOBUF IOBUF_11(
+ .I(soc_a7ddrphy_dq_o_nodelay11),
+ .T(soc_a7ddrphy_dq_t11),
+ .IO(ddram_dq[11]),
+ .O(soc_a7ddrphy_dq_i_nodelay11)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_42 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay12),
+ .TQ(soc_a7ddrphy_dq_t12)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_12 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed12),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data12[7]),
+ .Q2(soc_a7ddrphy_dq_i_data12[6]),
+ .Q3(soc_a7ddrphy_dq_i_data12[5]),
+ .Q4(soc_a7ddrphy_dq_i_data12[4]),
+ .Q5(soc_a7ddrphy_dq_i_data12[3]),
+ .Q6(soc_a7ddrphy_dq_i_data12[2]),
+ .Q7(soc_a7ddrphy_dq_i_data12[1]),
+ .Q8(soc_a7ddrphy_dq_i_data12[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_14 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
+);
+
+IOBUF IOBUF_12(
+ .I(soc_a7ddrphy_dq_o_nodelay12),
+ .T(soc_a7ddrphy_dq_t12),
+ .IO(ddram_dq[12]),
+ .O(soc_a7ddrphy_dq_i_nodelay12)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_43 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay13),
+ .TQ(soc_a7ddrphy_dq_t13)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_13 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed13),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data13[7]),
+ .Q2(soc_a7ddrphy_dq_i_data13[6]),
+ .Q3(soc_a7ddrphy_dq_i_data13[5]),
+ .Q4(soc_a7ddrphy_dq_i_data13[4]),
+ .Q5(soc_a7ddrphy_dq_i_data13[3]),
+ .Q6(soc_a7ddrphy_dq_i_data13[2]),
+ .Q7(soc_a7ddrphy_dq_i_data13[1]),
+ .Q8(soc_a7ddrphy_dq_i_data13[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_15 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
+);
+
+IOBUF IOBUF_13(
+ .I(soc_a7ddrphy_dq_o_nodelay13),
+ .T(soc_a7ddrphy_dq_t13),
+ .IO(ddram_dq[13]),
+ .O(soc_a7ddrphy_dq_i_nodelay13)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_44 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay14),
+ .TQ(soc_a7ddrphy_dq_t14)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_14 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed14),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data14[7]),
+ .Q2(soc_a7ddrphy_dq_i_data14[6]),
+ .Q3(soc_a7ddrphy_dq_i_data14[5]),
+ .Q4(soc_a7ddrphy_dq_i_data14[4]),
+ .Q5(soc_a7ddrphy_dq_i_data14[3]),
+ .Q6(soc_a7ddrphy_dq_i_data14[2]),
+ .Q7(soc_a7ddrphy_dq_i_data14[1]),
+ .Q8(soc_a7ddrphy_dq_i_data14[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_16 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
+);
+
+IOBUF IOBUF_14(
+ .I(soc_a7ddrphy_dq_o_nodelay14),
+ .T(soc_a7ddrphy_dq_t14),
+ .IO(ddram_dq[14]),
+ .O(soc_a7ddrphy_dq_i_nodelay14)
+);
+
+OSERDESE2 #(
+ .DATA_RATE_OQ("DDR"),
+ .DATA_RATE_TQ("BUF"),
+ .DATA_WIDTH(4'd8),
+ .SERDES_MODE("MASTER"),
+ .TRISTATE_WIDTH(1'd1)
+) OSERDESE2_45 (
+ .CLK(sys4x_clk),
+ .CLKDIV(sys_clk),
+ .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
+ .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
+ .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
+ .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
+ .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
+ .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
+ .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
+ .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
+ .OCE(1'd1),
+ .RST(sys_rst),
+ .T1((~soc_a7ddrphy_dq_oe_delayed)),
+ .TCE(1'd1),
+ .OQ(soc_a7ddrphy_dq_o_nodelay15),
+ .TQ(soc_a7ddrphy_dq_t15)
+);
+
+ISERDESE2 #(
+ .DATA_RATE("DDR"),
+ .DATA_WIDTH(4'd8),
+ .INTERFACE_TYPE("NETWORKING"),
+ .IOBDELAY("IFD"),
+ .NUM_CE(1'd1),
+ .SERDES_MODE("MASTER")
+) ISERDESE2_15 (
+ .BITSLIP(1'd0),
+ .CE1(1'd1),
+ .CLK(sys4x_clk),
+ .CLKB((~sys4x_clk)),
+ .CLKDIV(sys_clk),
+ .DDLY(soc_a7ddrphy_dq_i_delayed15),
+ .RST(sys_rst),
+ .Q1(soc_a7ddrphy_dq_i_data15[7]),
+ .Q2(soc_a7ddrphy_dq_i_data15[6]),
+ .Q3(soc_a7ddrphy_dq_i_data15[5]),
+ .Q4(soc_a7ddrphy_dq_i_data15[4]),
+ .Q5(soc_a7ddrphy_dq_i_data15[3]),
+ .Q6(soc_a7ddrphy_dq_i_data15[2]),
+ .Q7(soc_a7ddrphy_dq_i_data15[1]),
+ .Q8(soc_a7ddrphy_dq_i_data15[0])
+);
+
+IDELAYE2 #(
+ .CINVCTRL_SEL("FALSE"),
+ .DELAY_SRC("IDATAIN"),
+ .HIGH_PERFORMANCE_MODE("TRUE"),
+ .IDELAY_TYPE("VARIABLE"),
+ .IDELAY_VALUE(1'd0),
+ .PIPE_SEL("FALSE"),
+ .REFCLK_FREQUENCY(200.0),
+ .SIGNAL_PATTERN("DATA")
+) IDELAYE2_17 (
+ .C(sys_clk),
+ .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
+ .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
+ .INC(1'd1),
+ .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+ .LDPIPEEN(1'd0),
+ .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
+);
+
+IOBUF IOBUF_15(
+ .I(soc_a7ddrphy_dq_o_nodelay15),
+ .T(soc_a7ddrphy_dq_t15),
+ .IO(ddram_dq[15]),
+ .O(soc_a7ddrphy_dq_i_nodelay15)
+);
+
+reg [24:0] storage_2[0:15];
+reg [24:0] memdat_5;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
+ storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_3[0:15];
+reg [24:0] memdat_6;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
+ storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_4[0:15];
+reg [24:0] memdat_7;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
+ storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_5[0:15];
+reg [24:0] memdat_8;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
+ storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
+assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_6[0:15];
+reg [24:0] memdat_9;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
+ storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
+assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_7[0:15];
+reg [24:0] memdat_10;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
+ storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
+assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_8[0:15];
+reg [24:0] memdat_11;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
+ storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
+assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+
+reg [24:0] storage_9[0:15];
+reg [24:0] memdat_12;
+always @(posedge sys_clk) begin
+ if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
+ storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+ memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
+assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+
+VexRiscv VexRiscv(
+ .clk(sys_clk),
+ .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack),
+ .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r),
+ .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err),
+ .externalInterruptArray(soc_litedramcore_cpu_interrupt),
+ .externalResetVector(soc_litedramcore_vexriscv),
+ .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack),
+ .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r),
+ .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err),
+ .reset((sys_rst | soc_litedramcore_cpu_reset)),
+ .softwareInterrupt(1'd0),
+ .timerInterrupt(1'd0),
+ .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr),
+ .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte),
+ .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti),
+ .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc),
+ .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w),
+ .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel),
+ .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb),
+ .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we),
+ .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr),
+ .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte),
+ .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti),
+ .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc),
+ .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w),
+ .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel),
+ .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb),
+ .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we)
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(5'd16),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(5'd16),
+ .CLKOUT0_PHASE(1'd0),
+ .CLKOUT1_DIVIDE(3'd4),
+ .CLKOUT1_PHASE(1'd0),
+ .CLKOUT2_DIVIDE(3'd4),
+ .CLKOUT2_PHASE(7'd90),
+ .DIVCLK_DIVIDE(1'd1),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV (
+ .CLKFBIN(vns_pll_fb0),
+ .CLKIN1(soc_s7pll0_clkin),
+ .RST(soc_sys_pll_reset),
+ .CLKFBOUT(vns_pll_fb0),
+ .CLKOUT0(soc_s7pll0_clkout0),
+ .CLKOUT1(soc_s7pll0_clkout1),
+ .CLKOUT2(soc_s7pll0_clkout2),
+ .LOCKED(soc_sys_pll_locked)
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(5'd16),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(4'd8),
+ .CLKOUT0_PHASE(1'd0),
+ .DIVCLK_DIVIDE(1'd1),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV_1 (
+ .CLKFBIN(vns_pll_fb1),
+ .CLKIN1(soc_s7pll1_clkin),
+ .RST(soc_iodelay_pll_reset),
+ .CLKFBOUT(vns_pll_fb1),
+ .CLKOUT0(soc_s7pll1_clkout),
+ .LOCKED(soc_iodelay_pll_locked)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE (
+ .C(sys_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_1 (
+ .C(sys_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+ .Q(sys_rst)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_2 (
+ .C(sys4x_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_3 (
+ .C(sys4x_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl1),
+ .Q(vns_xilinxasyncresetsynchronizerimpl1_expr)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_4 (
+ .C(sys4x_dqs_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_5 (
+ .C(sys4x_dqs_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl2),
+ .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_6 (
+ .C(iodelay_clk),
+ .CE(1'd1),
+ .D(1'd0),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+ .INIT(1'd1)
+) FDPE_7 (
+ .C(iodelay_clk),
+ .CE(1'd1),
+ .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
+ .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+ .Q(iodelay_rst)
+);
+
+endmodule
--- /dev/null
+CAPI=2:
+
+name : :microwatt:litedram:0
+
+generators:
+ litedram_gen:
+ interpreter: python3
+ command: extras/fusesoc-add-files.py
+ description: Generate a litedram memory controller
+ usage: |
+ litedram_gen adds the pre-generated LiteX LiteDRAM memory controller
+ based on the board type.
+
+ Parameters:
+ board: The board type (arty, nexys_video)
- fpga/cmod_a7-35.xdc : {file_type : xdc}
- fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
+ litedram:
+ depend : [":microwatt:litedram"]
+
targets:
nexys_a7:
default_tool: vivado
description : Prevent Vivado from flattening the main core components
paramtype : generic
default : false
+
+ use_litedram:
+ datatype : bool
+ description : Use liteDRAM
+ paramtype : generic
+ default : false
mw_debug: mw_debug.c
$(CC) -o $@ $^ -lurjtag
+clean:
+ rm -f mw_debug
+distclean:
+ rm -f *~
+
projects / microwatt.git / commitdiff