Consistency

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index a20d3cdce85c3469ff5ee66d7166c2b8700612d5..38a5a8d24c0375e889462610284d0127e3c79e10 100644 (file)
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -45,7 +45,7 @@ match dsp
        select nusers(port(dsp, \C, SigSpec())) > 1
 endmatch
 
-code sigC sigP
+code sigC sigP clock
        unextend = [](const SigSpec &sig) {
                int i;
                for (i = GetSize(sig)-1; i > 0; i--)
@@ -71,6 +71,8 @@ code sigC sigP
        }
        else
                sigP = P;
+
+       clock = port(dsp, \CLK, SigBit());
 endcode
 
 // (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
@@ -82,8 +84,6 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
        if (sigC == sigP)
                reject;
 
-       clock = port(dsp, \CLK, SigBit());
-
        argQ = sigC;
        subpattern(in_dffe);
        if (dff) {