i965: Drop BLT TexSubImage Y-tiling restriction on Gen6+.

Currently, we don't use this path on Sandybridge because we suspect
other paths will be faster.  But we potentially could.  If we do, we
should allow it to support Y-tiled BLTs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 6942039fdc9ebf5d717f3630f6402f39554758d8..b65a7720af5f545013b1b4d385a18b881b7496b8 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -98,8 +98,8 @@ intel_blit_texsubimage(struct gl_context * ctx,
    if (!intelImage->mt)
       return false;
 
-   /* The blitter can't handle Y tiling */
-   if (intelImage->mt->region->tiling == I915_TILING_Y)
+   /* Prior to Sandybridge, the blitter can't handle Y tiling */
+   if (brw->gen < 6 && intelImage->mt->region->tiling == I915_TILING_Y)
       return false;
 
    if (texImage->TexObject->Target != GL_TEXTURE_2D)