X86: Implement CLTS.

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 0e13d3104115a7326efc84d164063c96700ef905..4c0460e28485b6979431e39bbcaa8e3c2debcc75 100644 (file)
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -190,6 +190,7 @@ if env['TARGET_ISA'] == 'x86':
         'general_purpose/system_calls.py',
         'romutil.py',
         'system/__init__.py',
+        'system/control_registers.py',
         'system/halt.py',
         'system/invlpg.py',
         'system/undefined_operation.py',

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index f4a007282aaaf2e64ff047557bf4e8ac810acccf..c127ff458093023fec2af148b4226ce30e4f9d24 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -264,7 +264,7 @@
 #else
                 0x05: SyscallInst::syscall('xc->syscall(Rax)', IsSyscall);
 #endif
-                0x06: clts();
+                0x06: Inst::CLTS();
                 0x07: decode MODE_SUBMODE {
                     0x0: decode OPSIZE {
                         // Return to 64 bit mode.

diff --git a/src/arch/x86/isa/insts/system/__init__.py b/src/arch/x86/isa/insts/system/__init__.py
index 409a929f532f7fabf3eb5e83f84a2a43834b3f75..0dec9ebda84de2c92712e2937f403ae6c52dc764 100644 (file)
--- a/src/arch/x86/isa/insts/system/__init__.py
+++ b/src/arch/x86/isa/insts/system/__init__.py
@@ -81,7 +81,8 @@
 #
 # Authors: Gabe Black
 
-categories = ["halt",
+categories = ["control_registers",
+              "halt",
               "invlpg",
               "undefined_operation",
               "msrs",

diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
new file mode 100644 (file)
index 0000000..902c01a
--- /dev/null
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2009 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+microcode = '''
+def macroop CLTS {
+    rdcr t1, 0, dataSize=8
+    andi t1, t1, 0xF7, dataSize=1
+    wrcr 0, t1, dataSize=8
+};
+'''