configs, arch-arm: Check if gic has cpu_addr attribute
authorChun-Chen TK Hsu <chunchenhsu@google.com>
Mon, 29 Jul 2019 15:09:35 +0000 (23:09 +0800)
committerChun-Chen TK Hsu <chunchenhsu@google.com>
Tue, 30 Jul 2019 11:39:20 +0000 (11:39 +0000)
Add this check because Gicv3 does not have the cpu_addr attribute.

Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the
following command to boot Debian.

M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \
--dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \
--kernel $PWD/fs_files/binaries/vmlinux \
--disk $PWD/fs_files/disks/disk.img \
--cpu-type atomic --big-cpus 1 --little-cpus 0

Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
configs/example/arm/devices.py

index c7d5a7c4d32428f7334215f7284ad56e29e91e8b..1cacef8b443afd981e3f2006e1dd5bbbb6efe2ff 100644 (file)
@@ -196,7 +196,8 @@ class SimpleSystem(LinuxArmSystem):
 
         self.realview = VExpress_GEM5_V1()
 
-        self.gic_cpu_addr = self.realview.gic.cpu_addr
+        if hasattr(self.realview.gic, 'cpu_addr'):
+            self.gic_cpu_addr = self.realview.gic.cpu_addr
         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 
         self.membus = MemBus()
@@ -239,7 +240,8 @@ class SimpleSystem(LinuxArmSystem):
             self.dmabridge.master = self.membus.slave
             self.dmabridge.slave = self.iobus.master
 
-        self.gic_cpu_addr = self.realview.gic.cpu_addr
+        if hasattr(self.realview.gic, 'cpu_addr'):
+            self.gic_cpu_addr = self.realview.gic.cpu_addr
         self.realview.attachOnChipIO(self.membus, self.iobridge)
         self.realview.attachIO(self.iobus)
         self.system_port = self.membus.slave