* config/elf.h: Fix comment formatting.
* config/elf64.h: Likewise.
* config/iris5.h: Likewise.
* config/iris5gas.h: Likewise.
* config/iris6.h: Likewise.
* config/isa3264.h: Likewise.
* config/linux.h: Likewise.
* config/mips.c: Likewise.
* config/mips.h: Likewise.
* config/mips.md: Likewise.
* config/mips16.S: Likewise.
* config/netbsd.h: Likewise.
* config/osfrose.h: Likewise.
* config/r3900.h: Likewise.
* config/sni-svr4.h: Likewise.
* config/svr4-t.h: Likewise.
* config/ultrix.h: Likewise.
From-SVN: r46670
+2001-10-30 Kazu Hirata <kazu@hxi.com>
+
+ * config/elf.h: Fix comment formatting.
+ * config/elf64.h: Likewise.
+ * config/iris5.h: Likewise.
+ * config/iris5gas.h: Likewise.
+ * config/iris6.h: Likewise.
+ * config/isa3264.h: Likewise.
+ * config/linux.h: Likewise.
+ * config/mips.c: Likewise.
+ * config/mips.h: Likewise.
+ * config/mips.md: Likewise.
+ * config/mips16.S: Likewise.
+ * config/netbsd.h: Likewise.
+ * config/osfrose.h: Likewise.
+ * config/r3900.h: Likewise.
+ * config/sni-svr4.h: Likewise.
+ * config/svr4-t.h: Likewise.
+ * config/ultrix.h: Likewise.
+
2001-10-30 Daniel Berlin <dan@cgsoftware.com>
* bitmap.c (bitmap_element_free): Don't forget to update head->indx
specified as the number of bits.
Try to use function `asm_output_aligned_bss' defined in file
- `varasm.c' when defining this macro. */
+ `varasm.c' when defining this macro. */
#ifndef ASM_OUTPUT_ALIGNED_BSS
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
mips-elf gas supports .weak, but not .weakext.
mips-elf gas has been changed to support both .weak and .weakext,
but until that support is generally available, the 'if' below
- should serve. */
+ should serve. */
#undef ASM_WEAKEN_LABEL
#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
mips-elf gas supports .weak, but not .weakext.
mips-elf gas has been changed to support both .weak and .weakext,
but until that support is generally available, the 'if' below
- should serve. */
+ should serve. */
#undef ASM_WEAKEN_LABEL
#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
/* We do not want to run mips-tfile! */
#undef ASM_FINAL_SPEC
-/* The system header files are C++ aware. */
+/* The system header files are C++ aware. */
/* ??? Unfortunately, most but not all of the headers are C++ aware.
Specifically, curses.h is not, and as a consequence, defining this
used to prevent libg++ building. This is no longer the case so
fixing. */
#define NO_IMPLICIT_EXTERN_C 1
-/* We don't support debugging info for now. */
+/* We don't support debugging info for now. */
#undef DBX_DEBUGGING_INFO
#undef SDB_DEBUGGING_INFO
#undef MIPS_DEBUGGING_INFO
-/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */
+/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */
/* Enable debugging. */
#define DBX_DEBUGGING_INFO
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* Force the generation of dwarf .debug_frame sections even if not
- compiling -g. This guarantees that we can unwind the stack. */
+ compiling -g. This guarantees that we can unwind the stack. */
#define DWARF2_FRAME_INFO 1
/* The size in bytes of a DWARF field indicating an offset or length
#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32} %{!mips*: %{!mabi*:-mips3} %{mabi=n32:-mips3} %{mabi=64:-mips4}}"
/* Must pass -g0 to the assembler, otherwise it may overwrite our
- debug info with its own debug info. */
+ debug info with its own debug info. */
/* Must pass -show instead of -v. */
/* Must pass -G 0 to the assembler, otherwise we may get warnings about
GOT overflow. */
#include "mips/elf.h"
/* This must be done after including mips.h so that the
- ABI_{EABI,O64,O32,...} are #defined. */
+ ABI_{EABI,O64,O32,...} are #defined. */
#if MIPS_ABI_DEFAULT == ABI_EABI
#undef SUBTARGET_CPP_SIZE_SPEC
For MEABI the size of longs is always 32bits. If long64 is specified then
we honor that. The errors for long64 & long32 is because while CC1 can
- handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */
+ handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */
#if MIPS_ISA_DEFAULT == 3 || MIPS_ISA_DEFAULT == 4 || MIPS_ISA_DEFAULT == 5 || MIPS_ISA_DEFAULT == 64
#undef SUBTARGET_CPP_SIZE_SPEC
specified as the number of bits.
Try to use function `asm_output_aligned_bss' defined in file
- `varasm.c' when defining this macro. */
+ `varasm.c' when defining this macro. */
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
ASM_GLOBALIZE_LABEL (FILE, NAME); \
/* Required to keep collect2.c happy */
#undef OBJECT_FORMAT_COFF
-/* If we don't set MASK_ABICALLS, we can't default to PIC. */
+/* If we don't set MASK_ABICALLS, we can't default to PIC. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
/* Enumeration for all of the relational tests, so that we can build
arrays indexed by the test type, and not worry about the order
- of EQ, NE, etc. */
+ of EQ, NE, etc. */
enum internal_test {
ITEST_EQ,
start and end boundaries). */
int sdb_label_count = 0;
-/* Next label # for each statement for Silicon Graphics IRIS systems. */
+/* Next label # for each statement for Silicon Graphics IRIS systems. */
int sym_lineno = 0;
/* Non-zero if inside of a function, because the stupid MIPS asm can't
/* This is only used to determine if an type size setting option was
explicitly specified (-mlong64, -mint64, -mlong32). The specs
- set this option if such an option is used. */
+ set this option if such an option is used. */
const char *mips_explicit_type_size_string;
/* Whether we are generating mips16 hard float code. In mips16 mode
}
/* Return truth value of whether OP is a register or the constant 0,
- even in mips16 mode. */
+ even in mips16 mode. */
int
true_reg_or_0_operand (op, mode)
if (GET_CODE (op) != SYMBOL_REF)
return 0;
- /* let's be paranoid.... */
+ /* let's be paranoid.... */
if (! SMALL_INT (offset))
return 0;
}
return 1;
/* Similarly, we accept a case where the memory address is
- itself on the stack, and will be reloaded. */
+ itself on the stack, and will be reloaded. */
if (GET_CODE (addr) == MEM)
{
rtx maddr;
}
/* Check for constant before stripping off SUBREG, so that we don't
- accept (subreg (const_int)) which will fail to reload. */
+ accept (subreg (const_int)) which will fail to reload. */
if (CONSTANT_ADDRESS_P (xinsn)
&& ! (mips_split_addresses && mips_check_split (xinsn, mode))
&& (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
return 2;
}
- /* ... fall through ... */
+ /* ... fall through ... */
case SYMBOL_REF:
return SYMBOL_REF_FLAG (addr) ? 1 : 2;
The block move type can be one of the following:
BLOCK_MOVE_NORMAL Do all of the block move.
BLOCK_MOVE_NOT_LAST Do all but the last store.
- BLOCK_MOVE_LAST Do just the last store. */
+ BLOCK_MOVE_LAST Do just the last store. */
const char *
output_block_move (insn, operands, num_regs, move_type)
/* Determine if this function has variable arguments. This is
indicated by the last argument being 'void_type_mode' if there
are no variable arguments. The standard MIPS calling sequence
- passes all arguments in the general purpose registers in this case. */
+ passes all arguments in the general purpose registers in this case. */
for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
param != 0; param = next_param)
Note that the GPR save area is not constant size, due to optimization
in the prologue. Hence, we can't use a design with two pointers
and two offsets, although we could have designed this with two pointers
- and three offsets. */
+ and three offsets. */
tree
if (mips_abi == ABI_EABI)
{
int gpr_save_area_size;
- /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
+ /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
if (int_arg_words < 8 )
/* Adjust for the prologue's economy measure */
gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
/* Emit code setting a pointer into the overflow (shared-stack) area.
If there were more than 8 non-float formals, or more than 8
float formals, then this pointer isn't to the base of the area.
- In that case, it must point to where the first vararg is. */
+ In that case, it must point to where the first vararg is. */
size_excess = 0;
if (float_formals > floats_passed_in_regs)
size_excess += (float_formals-floats_passed_in_regs) * 8;
take into account the exact sequence of floats and non-floats
which make up the excess. That calculation should be rolled
into the code which sets the current_function_args_info struct.
- The above then reduces to a fetch from that struct. */
+ The above then reduces to a fetch from that struct. */
t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- /* Emit code setting a ptr to the base of the overflow area. */
+ /* Emit code setting a ptr to the base of the overflow area. */
t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
If mips4, this is gpr_save_area_size below the overflow area.
If mips2, also round down to an 8-byte boundary, since the FPR
save area is 8-byte aligned, and GPR is 4-byte-aligned.
- Therefore there can be a 4-byte gap between the save areas. */
+ Therefore there can be a 4-byte gap between the save areas. */
gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
fpr_save_offset = gpr_save_area_size;
if (!TARGET_64BIT)
/* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
/* Everything is in the GPR save area, or in the overflow
- area which is contiguous with it. */
+ area which is contiguous with it. */
int offset = -gpr_save_area_size;
if (gpr_save_area_size == 0)
if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
{
/* Case of all args in a merged stack. No need to check bounds,
- just advance valist along the stack. */
+ just advance valist along the stack. */
tree gpr = valist;
if (! indirect
return addr_rtx;
}
- /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
+ /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
f_ovfl = TYPE_FIELDS (va_list_type_node);
f_gtop = TREE_CHAIN (f_ovfl);
if (TREE_CODE (type) == REAL_TYPE)
{
- /* Emit code to branch if foff == 0. */
+ /* Emit code to branch if foff == 0. */
r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
EXPAND_NORMAL);
emit_cmp_and_jump_insns (r, const0_rtx, EQ,
/* For mips2, the overflow area contains mixed size items.
If a 4-byte int is followed by an 8-byte float, then
natural alignment causes a 4 byte gap.
- So, dynamically adjust ovfl up to a multiple of 8. */
+ So, dynamically adjust ovfl up to a multiple of 8. */
t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
build_int_2 (7, 0));
t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
}
/* Emit code for addr_rtx = the ovfl pointer into overflow area.
- Regardless of mips2, postincrement the ovfl pointer by 8. */
+ Regardless of mips2, postincrement the ovfl pointer by 8. */
t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
size_int (8));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
/* In mips2, int takes 32 bits of the GPR save area, but
longlong takes an aligned 64 bits. So, emit code
to zero the low order bits of goff, thus aligning
- the later calculation of (gtop-goff) upwards. */
+ the later calculation of (gtop-goff) upwards. */
t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
build_int_2 (-8, -1));
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
- /* Emit code to branch if goff == 0. */
+ /* Emit code to branch if goff == 0. */
r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
EXPAND_NORMAL);
emit_cmp_and_jump_insns (r, const0_rtx, EQ,
const1_rtx, GET_MODE (r), 1, 1, lab_false);
- /* Emit code for addr_rtx = gtop - goff. */
+ /* Emit code for addr_rtx = gtop - goff. */
t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
emit_move_insn (addr_rtx, r);
- /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
+ /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
step_size = 8;
else
step_size = UNITS_PER_WORD;
/* Emit code for goff = goff - step_size.
- Advances the offset up GPR save area over the item. */
+ Advances the offset up GPR save area over the item. */
t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
build_int_2 (step_size, 0));
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
}
else
{
- /* Not EABI. */
+ /* Not EABI. */
int align;
/* ??? The original va-mips.h did always align, despite the fact
/* If both single-float and soft-float are set, then clear the one that
was set by TARGET_DEFAULT, leaving the one that was set by the
user. We assume here that the specs prevent both being set by the
- user. */
+ user. */
#ifdef TARGET_DEFAULT
if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
}
#ifdef MIPS_ABI_DEFAULT
- /* Get the ABI to use. */
+ /* Get the ABI to use. */
if (mips_abi_string == (char *) 0)
mips_abi = MIPS_ABI_DEFAULT;
else if (! strcmp (mips_abi_string, "32"))
/* Require:
OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
- HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
+ HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
}
if (mips_entry && ! mips_can_use_return_insn ())
the varargs special argument, and treat it as part of the
variable arguments.
- This is only needed if store_args_on_stack is true. */
+ This is only needed if store_args_on_stack is true. */
INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
regno = GP_ARG_FIRST;
int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
rtx ptr = stack_pointer_rtx;
- /* If we are doing svr4-abi, sp has already been decremented by tsize. */
+ /* If we are doing svr4-abi, sp has already been decremented by tsize. */
if (TARGET_ABICALLS)
offset += tsize;
}
\f
/* Do any necessary cleanup after a function to restore stack, frame,
- and regs. */
+ and regs. */
#define RA_MASK BITMASK_HIGH /* 1 << 31 */
#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
{
/* Don't pass the actual CUM to FUNCTION_ARG, because we would
get double copies of any offsets generated for small structs
- passed in registers. */
+ passed in registers. */
CUMULATIVE_ARGS temp;
temp = *cum;
if (FUNCTION_ARG (temp, mode, type, named) != 0)
/* We build the stub code by hand. That's the only way we can
do it, since we can't generate 32 bit code during a 16 bit
- compilation. */
+ compilation. */
/* We don't want the assembler to insert any nops here. */
fprintf (asm_out_file, "\t.set\tnoreorder\n");
{
/* If we haven't had a barrier within 0x8000 bytes of a
constant reference or we are at the end of the function,
- emit a barrier now. */
+ emit a barrier now. */
rtx label, jump, barrier;
break;
case LTU:
- /* A condition which will always be false. */
+ /* A condition which will always be false. */
code = NE;
op1 = "%.";
break;
value at preprocessing time.
ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
- defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
+ defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
#define ABI_32 0
#define ABI_N32 1
Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
EABI the legacy EABI. In the end we may end up calling both ABI's
EABI but give them different version numbers, but for now I'm going
- with different names. */
+ with different names. */
#define ABI_MEABI 5
BLOCK_MOVE_LAST /* generate just the last store */
};
-extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
+extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
extern const char *current_function_file; /* filename current function is in */
extern int num_source_filenames; /* current .file # */
#define MASK_DEBUG 0 /* unused */
#define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
#define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
-#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
+#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
#define MASK_DEBUG_D 0 /* don't do define_split's */
#define MASK_DEBUG_E 0 /* function_arg debug */
#define MASK_DEBUG_F 0 /* ??? */
/* always store uninitialized const
variables in rodata, requires
- TARGET_EMBEDDED_DATA. */
+ TARGET_EMBEDDED_DATA. */
#define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
/* generate big endian code. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
#define HAVE_SQRT_P() (mips_isa != 1)
-/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
+/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
#define ISA_HAS_64BIT_REGS (mips_isa == 3 \
|| mips_isa == 4 \
|| mips_isa == 64)
-/* ISA has branch likely instructions (eg. mips2). */
+/* ISA has branch likely instructions (eg. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
/* || TARGET_MIPS3900 */)
-/* ISA has the conditional move instructions introduced in mips4. */
+/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
|| mips_isa == 32 \
|| mips_isa == 64)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
- branch on CC, and move (both FP and non-FP) on CC. */
+ branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (mips_isa == 4 \
|| mips_isa == 32 \
|| mips_isa == 64)
/* Redefinition of libraries used. Mips doesn't support normal
UNIX style profiling via calling _mcount. It does offer
- profiling that samples the PC, so do what we can... */
+ profiling that samples the PC, so do what we can... */
#ifndef LIB_SPEC
#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
/* Local compiler-generated symbols must have a prefix that the assembler
understands. By default, this is $, although some targets (e.g.,
- NetBSD-ELF) need to override this. */
+ NetBSD-ELF) need to override this. */
#ifndef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "$"
#endif
/* By default on the mips, external symbols do not have an underscore
- prepended, but some targets (e.g., NetBSD) require this. */
+ prepended, but some targets (e.g., NetBSD) require this. */
#ifndef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX ""
#undef DBX_CONTIN_LENGTH
#define DBX_CONTIN_LENGTH 1500
-/* How to renumber registers for dbx and gdb. */
+/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
/* The mapping from gcc register number to DWARF 2 CFA column number.
*/
#define BITS_BIG_ENDIAN 0
-/* Define this if most significant byte of a word is the lowest numbered. */
+/* Define this if most significant byte of a word is the lowest numbered. */
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-/* Define this if most significant word of a multiword number is the lowest. */
+/* Define this if most significant word of a multiword number is the lowest. */
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
/* Define this to set the endianness to use in libgcc2.c, which can
/* Define this macro if an argument declared as `char' or `short' in a
prototype should actually be passed as an `int'. In addition to
avoiding errors in certain cases of mismatch, it also makes for
- better code on certain machines. */
+ better code on certain machines. */
#define PROMOTE_PROTOTYPES 1
/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
registers explicitly used in the rtl to be used as spill registers
but prevents the compiler from extending the lifetime of these
- registers. */
+ registers. */
#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero. */
+ For args passed entirely in registers or entirely in memory, zero. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
- Do not define this if the table should contain absolute addresses. */
+ Do not define this if the table should contain absolute addresses. */
#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
/* Specify the tree operation to be used to convert reals to integers. */
#define SLOW_ZERO_EXTEND
/* Define this to be nonzero if shift instructions ignore all but the low-order
- few bits. */
+ few bits. */
#define SHIFT_COUNT_TRUNCATED 1
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode.
- For MIPS we make pointers are the smaller of longs and gp-registers. */
+ For MIPS we make pointers are the smaller of longs and gp-registers. */
#ifndef Pmode
#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
if (GET_CODE (symref) != SYMBOL_REF) \
return COSTS_N_INSNS (4); \
\
- /* let's be paranoid.... */ \
+ /* let's be paranoid.... */ \
if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
return COSTS_N_INSNS (2); \
\
different numbers of registers on machines with lots of registers.
This macro will normally either not be defined or be defined as
- a constant. */
+ a constant. */
#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
all values except -1. We could handle that case by using a signed
divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
compare/branch to test the input value to see which instruction we
- need to use. This gets pretty messy, but it is feasible. */
+ need to use. This gets pretty messy, but it is feasible. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
$Lb[0-9]+ Begin blocks for MIPS debug support
$Lc[0-9]+ Label for use in s<xx> operation.
$Le[0-9]+ End blocks for MIPS debug support
- $Lp\..+ Half-pic labels. */
+ $Lp\..+ Half-pic labels. */
/* This is how to output the definition of a user-level label named NAME,
such as the label on a static function or variable NAME.
address with faster (gp) register relative addressing, which can
only get at sdata and sbss items (there is no stext !!) However,
if the constant is too large for sdata, and it's readonly, it
- will go into the .rdata section. */
+ will go into the .rdata section. */
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
and mips-tdump.c to print them out.
These must match the corresponding definitions in gdb/mipsread.c.
- Unfortunately, gcc and gdb do not currently share any directories. */
+ Unfortunately, gcc and gdb do not currently share any directories. */
#define CODE_MASK 0x8F300
#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
have_dep_anti = 1;
if (! have_dep_anti)
{
- /* No branch delay slots on mips16. */
+ /* No branch delay slots on mips16. */
if (which_alternative == 1)
return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
else
/* This file contains 32 bit assembly code. */
.set nomips16
-/* Start a function. */
+/* Start a function. */
#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
#define TARGET_MEM_FUNCTIONS
-/* Define mips-specific netbsd predefines... */
+/* Define mips-specific netbsd predefines... */
#ifndef CPP_PREDEFINES
#define CPP_PREDEFINES "-D__ANSI_COMPAT \
-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -D__NetBSD__ -Dmips \
/* Define this macro meaning that `gcc' should find the library
`libgcc.a' by hand, rather than passing the argument `-lgcc' to
- tell the linker to do the search. */
+ tell the linker to do the search. */
#define LINK_LIBGCC_SPECIAL 1
%e-msingle-float and -msoft-float can not both be specified.}}"
/* The following is needed because -mips3 and -mips4 set gp64 which in
- combination with abi=eabi, causes long64 to be set. */
+ combination with abi=eabi, causes long64 to be set. */
#define SUBTARGET_CPP_SIZE_SPEC "\
%{mips3:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
%{mips4:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the
- gnu assembler not to generate debugging information. */
+ gnu assembler not to generate debugging information. */
#define SUBTARGET_ASM_DEBUGGING_SPEC "\
%{!mmips-as: \
#undef OBJECT_FORMAT_COFF
-/* We don't support debugging info for now. */
+/* We don't support debugging info for now. */
#undef DBX_DEBUGGING_INFO
#undef SDB_DEBUGGING_INFO
#undef MIPS_DEBUGGING_INFO
-/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */
+/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */
/* Use the default value for this. */
#undef STANDARD_INCLUDE_DIR
#define TARGET_MEM_FUNCTIONS
/* Work around assembler forward label references generated in exception
- handling code. */
+ handling code. */
#define DWARF2_UNWIND_INFO 0
/* INITIALIZE_TRAMPOLINE calls this library function to flush
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