\begin{frame}[fragile]{\subsubsecname{} -- Example}
\begin{columns}
\column[t]{4cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select_01.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v}
\column[t]{7cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select_01.ys}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys}
\end{columns}
-\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select_01.pdf}
+\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsectionpagesuffix
\end{frame}
-\subsubsection{TBD}
+\subsubsection{Intro to coarse-grain synthesis}
+
+\begin{frame}[fragile]{\subsubsecname}
+In coarse-grain synthesis the target architecure has cells of the same
+complexity or larger complexity than the internal RTL representation.
+
+For example:
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]
+ wire [15:0] a, b;
+ wire [31:0] c, y;
+ assign y = a * b + c;
+\end{lstlisting}
+
+This circuit contains two cells in the RTL representation: one multiplier and
+one adder.
+
+\medskip
+Coarse grain synthesis is mapping this circuit to a single multiply-add cell
+of the target architecture, for example using an FPGA DSP core.
+
+\bigskip
+Fine-grain synthesis would be matching the circuit to smaller elements, such
+as LUTs, gates, or half- and full-adders.
+\end{frame}
+
+\subsubsection{The extract pass}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item Like the {\tt techmap} pass, the {\tt extract} pass is called with
+a map file. It compares the circuits inside the modules of the map file
+with the design and looks for sub-circuits in the design that match any
+of the modules in the map file.
+\bigskip
+\item If a match is found, the {\tt extract} pass will replace the matching
+subcircuit with an instance of the module from the map file.
+\bigskip
+\item In a way the {\tt extract} pass is the inverse of the techmap pass.
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2}
+\vbox to 0cm{
+\vskip2cm
+\begin{tikzpicture}
+ \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}};
+ \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}};
+ \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2);
+\end{tikzpicture}
+\vss}
+\vskip-1.2cm
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys]
+read_verilog macc_simple_test.v
+hierarchy -check -top test
+
+extract -map macc_simple_xmap.v;;
+\end{lstlisting}
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2}
+\hfil\begin{tabular}{cc}
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} &
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\
+\end{tabular}
+\end{frame}
+
+\subsubsection{The wrap-extract-unwrap method}
\begin{frame}{\subsubsecname}
TBD
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
+all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
+ macc_simple_xmap.pdf
-select_01.pdf: select_01.v select_01.ys
- ../../yosys select_01.ys
+select.pdf: select.v select.ys
+ ../../yosys select.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys
addshift.pdf: addshift_*
../../yosys addshift_test.ys
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+ ../../yosys macc_simple_test.ys
+
--- /dev/null
+module test(a, b, c, d, y);
+input [15:0] a, b;
+input [31:0] c, d;
+output [31:0] y;
+assign y = a * b + c + d;
+endmodule
--- /dev/null
+read_verilog macc_simple_test.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -constports -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+read_verilog macc_simple_test_01.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_02.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_xmap.v
+hierarchy -check -top macc_16_16_32;;
+
+show -prefix macc_simple_xmap -format pdf -notitle
--- /dev/null
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + c*d + x;
+endmodule
--- /dev/null
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + (c*d + x);
+endmodule
--- /dev/null
+module macc_16_16_32(a, b, c, y);
+input [15:0] a, b;
+input [31:0] c;
+output [31:0] y;
+assign y = a*b + c;
+endmodule
--- /dev/null
+module test(clk, s, a, y);
+ input clk, s;
+ input [15:0] a;
+ output [15:0] y;
+ reg [15:0] b, c;
+
+ always @(posedge clk) begin
+ b <= a;
+ c <= b;
+ end
+
+ wire [15:0] state_a = (a ^ b) + c;
+ wire [15:0] state_b = (a ^ b) - c;
+ assign y = !s ? state_a : state_b;
+endmodule
--- /dev/null
+read_verilog select.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select -format pdf -notitle \
+ -color red @cone_ab -color magenta @cone_a \
+ -color blue @cone_b
+++ /dev/null
-module test(clk, s, a, y);
- input clk, s;
- input [15:0] a;
- output [15:0] y;
- reg [15:0] b, c;
-
- always @(posedge clk) begin
- b <= a;
- c <= b;
- end
-
- wire [15:0] state_a = (a ^ b) + c;
- wire [15:0] state_b = (a ^ b) - c;
- assign y = !s ? state_a : state_b;
-endmodule
+++ /dev/null
-read_verilog select_01.v
-hierarchy -check -top test
-proc; opt
-cd test
-select -set cone_a state_a %ci*:-$dff
-select -set cone_b state_b %ci*:-$dff
-select -set cone_ab @cone_a @cone_b %i
-show -prefix select_01 -format pdf -notitle \
- -color red @cone_ab -color magenta @cone_a \
- -color blue @cone_b
Because of the framework characterisitcs of Yosys, an increasing number of features
become available in one tool. Yosys not only can be used for circuit synthesis but
also for formal equivialence checking, SAT solving, and for circuit analysis, to
-name just a few other application domains. With propritaery software one needs to
+name just a few other application domains. With proprietary software one needs to
learn a new tool for each of this applications.
\end{itemize}
\end{frame}
projects / yosys.git / commitdiff