EXTRA3 = 2
EXTRA32 = 3 # mixed EXTRA3 and EXTRA2 using RM bits 6&7 for MASK_SRC
- def __repr__(self):
+ def __str__(self):
return self.name
NO = 0
EN = 1
- def __repr__(self):
+ def __str__(self):
return self.name
CIA = 8 # for addpcis
RT = 9
+ def __str__(self):
+ if self is In1Sel.RA_OR_ZERO:
+ return "RA0"
+ return self.name
+
@property
def type(self):
if self is In1Sel.NONE:
CONST_DXHI4 = 18 # for addpcis
CONST_DQ = 19 # for ld/st-quad
+ def __str__(self):
+ return self.name
+
@property
def type(self):
if self is In2Sel.NONE:
RTp = RT
FRA = 7
+ def __str__(self):
+ return self.name
+
@property
def type(self):
if self is In3Sel.NONE:
RSp = RS
FRA = 8
+ def __str__(self):
+ if self is OutSel.RT_OR_ZERO:
+ return "RT0"
+ return self.name
+
@property
def type(self):
if self is OutSel.NONE:
CR1 = 7
BA = 8
+ def __str__(self):
+ return self.name
+
@property
def type(self):
if self is CRInSel.NONE:
NONE = 0
BB = 1
+ def __str__(self):
+ return self.name
+
@property
def type(self):
if self is CRIn2Sel.NONE:
WHOLE_REG = 4
CR1 = 5
+ def __str__(self):
+ return self.name
+
@property
def type(self):
if self is CROutSel.NONE: