| `fcvttgud. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 3` |
| `fcvttgudo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 3` |
| `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
-
-----------
-
-\newpage{}
-
-## Floating Convert Single To Integer In GPR
-
-```
- fcvtstg RT, FRB, CVM, IT
- fcvtstg. RT, FRB, CVM, IT
- fcvtstgo RT, FRB, CVM, IT
- fcvtstgo. RT, FRB, CVM, IT
-```
-
-| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21 | 22-30 | 31 | Form |
-|-----|------|-------|-------|-------|----|-------|----|---------|
-| PO | RT | IT | CVM | FRB | OE | XO | Rc | XO-Form |
-
-```
- # based on xscvdpuxws
- reset_xflags()
- src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
-
- switch(IT)
- case(0): # Signed 32-bit
- range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
- range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
- js_mask <- 0x0000_0000_FFFF_FFFF
- case(1): # Unsigned 32-bit
- range_min <- bfp_CONVERT_FROM_UI32(0)
- range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
- js_mask <- 0x0000_0000_FFFF_FFFF
- case(2): # Signed 64-bit
- range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
- range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
- default: # Unsigned 64-bit
- range_min <- bfp_CONVERT_FROM_UI64(0)
- range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
-
- if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
- rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
- else if FPSCR.RN = 0b00 then
- rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
- else if FPSCR.RN = 0b10 then
- rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
- else if FPSCR.RN = 0b11 then
- rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
-
- switch(CVM)
- case(0, 1): # OpenPower semantics
- if IsNaN(rnd) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(rnd)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(rnd)
- case(2, 3): # Java/Saturating semantics
- if IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(rnd)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(rnd)
- default: # JavaScript semantics
- # CVM = 6, 7 are illegal instructions
- # using a 128-bit intermediate works here because the largest type
- # this instruction can convert from has 53 significand bits, and
- # the largest type this instruction can convert to has 64 bits,
- # and the sum of those is strictly less than the 128 bits of the
- # intermediate result.
- limit <- bfp_CONVERT_FROM_UI128([1] * 128)
- if IsInf(rnd) | IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
- result <- [0] * 64
- else
- result128 <- si128_CONVERT_FROM_BFP(rnd)
- result <- result128[64:127] & js_mask
-
- switch(IT)
- case(0): # Signed 32-bit
- result <- EXTS64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
- case(1): # Unsigned 32-bit
- result <- EXTZ64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
- case(2): # Signed 64-bit
- result_bfp <- bfp_CONVERT_FROM_SI64(result)
- default: # Unsigned 64-bit
- result_bfp <- bfp_CONVERT_FROM_UI64(result)
-
- overflow <- 0 # signals SO only when OE = 1
- if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
- overflow <- 1 # signals SO only when OE = 1
- vxcvi_flag <- 1
- xx_flag <- 0
- inc_flag <- 0
- else
- xx_flag <- ¬bfp_COMPARE_EQ(src, result_bfp)
- inc_flag <- bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
-
- if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
- if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
- if xx_flag = 1 then SetFX(FPSCR.XX)
-
- vx_flag <- vxsnan_flag | vxcvi_flag
- vex_flag <- FPSCR.VE & vx_flag
- if vex_flag = 0 then
- RT <- result
- FPSCR.FPRF <- undefined
- FPSCR.FR <- inc_flag
- FPSCR.FI <- xx_flag
- else
- FPSCR.FR <- 0
- FPSCR.FI <- 0
-```
-
-Convert from 32-bit float in FRB to a unsigned/signed 32/64-bit integer
-in RT, with the conversion overflow/rounding semantics following the
-chosen `CVM` value, following the usual 32-bit float in 64-bit float
-format. `FPSCR` is modified and exceptions are raised as usual.
-
-These instructions have an Rc=1 mode which sets CR0 in the normal
-way for any instructions producing a GPR result. Additionally, when OE=1,
-if the numerical value of the FP number is not 100% accurately preserved
-(due to truncation or saturation and including when the FP number was
-NaN) then this is considered to be an Integer Overflow condition, and
-CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
-that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits
-except SO are undefined.
-
-Special Registers altered:
-
-```
- CR0 (if Rc=1)
- XER SO, OV, OV32 (if OE=1)
- FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
-```
-
-### Assembly Aliases
-
-| Assembly Alias | Full Instruction |
-|----------------------------|-----------------------------|
-| `fcvtstgw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 0` |
-| `fcvtstgw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 0` |
-| `fcvtstgwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 0` |
-| `fcvtstgwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 0` |
-| `fcvtstguw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 1` |
-| `fcvtstguw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 1` |
-| `fcvtstguwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 1` |
-| `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` |
-| `fcvtstgd RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 2` |
-| `fcvtstgd. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 2` |
-| `fcvtstgdo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 2` |
-| `fcvtstgdo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 2` |
-| `fcvtstgud RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 3` |
-| `fcvtstgud. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 3` |
-| `fcvtstgudo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 3` |
-| `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` |
fmvtg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
fmvfg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
fcvtfg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
-fcvttg(s), ls006.fpintmv, high, 9, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
+fcvttg(o), ls006.fpintmv, high, 9, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO
# Big-Integer Chained 3-in 2-out (64-bit Carry)
dsld, ls003.bignum, high, 5, yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes
dsrd, ls003.bignum, high, 5, yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes
projects / libreriscv.git / commitdiff