control: Reduce pipeline depth to 1

To match our one stage execute.

This might change back if we end up adding 2 stages to match the
LSU, but in that case we'll want forwards as well.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/control.vhdl b/control.vhdl
index 44c6374f7e552df02458a4f2a2d4f5be5eea877f..0555b060c4cccea920e5bfca37861bed89c6bdf9 100644 (file)
--- a/control.vhdl
+++ b/control.vhdl
@@ -57,7 +57,7 @@ architecture rtl of control is
 begin
     gpr_hazard0: entity work.gpr_hazard
         generic map (
-            PIPELINE_DEPTH => 2
+            PIPELINE_DEPTH => PIPELINE_DEPTH
             )
         port map (
             clk                => clk,
@@ -72,7 +72,7 @@ begin
 
     gpr_hazard1: entity work.gpr_hazard
         generic map (
-            PIPELINE_DEPTH => 2
+            PIPELINE_DEPTH => PIPELINE_DEPTH
             )
         port map (
             clk                => clk,
@@ -87,7 +87,7 @@ begin
 
     gpr_hazard2: entity work.gpr_hazard
         generic map (
-            PIPELINE_DEPTH => 2
+            PIPELINE_DEPTH => PIPELINE_DEPTH
             )
         port map (
             clk                => clk,
@@ -102,7 +102,7 @@ begin
 
     cr_hazard0: entity work.cr_hazard
         generic map (
-            PIPELINE_DEPTH => 2
+            PIPELINE_DEPTH => PIPELINE_DEPTH
             )
         port map (
             clk                => clk,

diff --git a/decode2.vhdl b/decode2.vhdl
index c8dee489c62b96327e772132276f0fca5a754630..1307e7d7f5a3f6954e2ee873369fa7298cfae818 100644 (file)
--- a/decode2.vhdl
+++ b/decode2.vhdl
@@ -152,7 +152,7 @@ architecture behaviour of decode2 is
 begin
        control_0: entity work.control
        generic map (
-               PIPELINE_DEPTH => 2
+               PIPELINE_DEPTH => 1
        )
        port map (
                clk         => clk,