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raw | patch | inline | side by side (parent: 30adb1e)
add major.csv LD operations with SVP64BREV condition
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 24 Jun 2021 18:23:54 +0000 (19:23 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 24 Jun 2021 18:23:54 +0000 (19:23 +0100)
openpower/isatables/major.csv patch | blob | history

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index d06d5a39ca26b5bf46d93c1cd0110eb479102391..8fd9235fbcdab83e144f48d86f71089f7e334326 100644 (file)
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -1,4 +1,16 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,SVD,SVP64BREV
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,SVD,SVP64BREV
+50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,SVD,SVP64BREV
+51,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,SVD,SVP64BREV
+48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,SVD,SVP64BREV
+49,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,SVD,SVP64BREV
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,SVD,SVP64BREV
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,SVD,SVP64BREV
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,SVD,SVP64BREV
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,SVD,SVP64BREV
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,SVD,SVP64BREV
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,SVD,SVP64BREV
 12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic,D,
 13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D,
 14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D,
@@ -10,18 +22,18 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 16,BRANCH,OP_BC,SPR,CONST_BD,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc,B,
 11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi,D,
 10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli,D,
-34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D,
-35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D,
-50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D,
-51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D,
-48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D,
-49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D,
-42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D,
-43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D,
-40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D,
-41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,
-32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,
-33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D,~SVP64BREV
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D,~SVP64BREV
+50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D,~SVP64BREV
+51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D,~SVP64BREV
+48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D,~SVP64BREV
+49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D,~SVP64BREV
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D,~SVP64BREV
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D,~SVP64BREV
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D,~SVP64BREV
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,~SVP64BREV
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,~SVP64BREV
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,~SVP64BREV
 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,
 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,
 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,