techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4cbb56ea16cf224772f129703e768782938f06b1..b099c25d36cf45ddbc35e6a24f5f4fcb524923ae 100644 (file)
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -312,6 +312,11 @@ struct SynthEcp5Pass : public ScriptPass
                        run("techmap " + techmap_args);
 
                        if (abc9) {
+                               run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+                               run("wbflip @abc9_boxes");
+                               run("techmap -autoproc @abc9_boxes");
+                               run("aigmap @abc9_boxes");
+                               run("wbflip @abc9_boxes");
                                run("read_verilog -icells -lib +/ecp5/abc9_model.v");
                                if (nowidelut)
                                        run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 901194b06385bd9ff7bfe0931e055b6d45598000..2f0bdb130f536414958ec9442d05f7142ef0d985 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass
                        }
                        if (!noabc) {
                                if (abc == "abc9") {
+                                       run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+                                       run("wbflip @abc9_boxes");
+                                       run("techmap -autoproc @abc9_boxes");
+                                       run("aigmap @abc9_boxes");
+                                       run("wbflip @abc9_boxes");
                                        run("read_verilog -icells -lib +/ice40/abc9_model.v");
                                        int wire_delay;
                                        if (device_opt == "lp")

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2c5686a3564a28448abe285a1e7ebbdce92547a6..8c30148c053ee73898f53f61bf0ad3d8a6db0542 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -533,6 +533,11 @@ struct SynthXilinxPass : public ScriptPass
                                        log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
                                                        "will use timing for 'xc7' instead.\n", family.c_str());
                                run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+                               run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+                               run("wbflip @abc9_boxes");
+                               run("techmap -autoproc @abc9_boxes");
+                               run("aigmap @abc9_boxes");
+                               run("wbflip @abc9_boxes");
                                run("read_verilog -icells -lib +/xilinx/abc9_model.v");
                                std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
                                abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);