arch-riscv: Fix the srlw and srliw instructions.

Change-Id: I14ccb0655819887db2306fee1188e1c83a991743
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/11669
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d8f3395e398e80b9bd232dd1a6880b6bb74cde6c..b4bf3854b165bf6e9d74492ef7eaaac025ebcb98 100644 (file)
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -447,7 +447,7 @@ decode QUADRANT default Unknown::unknown() {
                 }});
                 0x5: decode SRTYPE {
                     0x0: srliw({{
-                        Rd = Rs1_uw >> SHAMT5;
+                        Rd_sd = (int32_t)(Rs1_uw >> SHAMT5);
                     }});
                     0x1: sraiw({{
                         Rd_sd = Rs1_sw >> SHAMT5;
@@ -759,7 +759,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, IntDivOp);
                 0x5: decode FUNCT7 {
                     0x0: srlw({{
-                        Rd_uw = Rs1_uw >> Rs2<4:0>;
+                        Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>);
                     }});
                     0x1: divuw({{
                         if (Rs2_uw == 0) {