def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
- self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
- self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6)
+ self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
- self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
- self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6)
+ self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+ self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
litex/boards/targets/simple.py litex.boards.platforms.{p} \
--cpu-type=vexriscv \
--no-compile-software \
- --no-compile-gateware \
--uart-name=stub \
""".format(p=p)
subprocess.check_call(cmd, shell=True)
--cpu-type={c} \
--cpu-variant={v} \
--no-compile-software \
- --no-compile-gateware \
--uart-name=stub \
""".format(c=cpu, v=variant)
subprocess.check_output(cmd, shell=True)