ARM: Set the value of the MVFR0 and MVFR1 registers.

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 41382e5102e1431fe95834a0c122d912addf1abf..9195cdfcd9a6a8dc918e31383e98ae1d7ca079cd 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -134,6 +134,27 @@ namespace ArmISA
             // Separate Instruction and Data TLBs.
             miscRegs[MISCREG_TLBTR] = 1;
 
+            MVFR0 mvfr0 = 0;
+            mvfr0.advSimdRegisters = 2;
+            mvfr0.singlePrecision = 2;
+            mvfr0.doublePrecision = 2;
+            mvfr0.vfpExceptionTrapping = 0;
+            mvfr0.divide = 1;
+            mvfr0.squareRoot = 1;
+            mvfr0.shortVectors = 1;
+            mvfr0.roundingModes = 1;
+            miscRegs[MISCREG_MVFR0] = mvfr0;
+
+            MVFR1 mvfr1 = 0;
+            mvfr1.flushToZero = 1;
+            mvfr1.defaultNaN = 1;
+            mvfr1.advSimdLoadStore = 1;
+            mvfr1.advSimdInteger = 1;
+            mvfr1.advSimdSinglePrecision = 1;
+            mvfr1.advSimdHalfPrecision = 1;
+            mvfr1.vfpHalfPrecision = 1;
+            miscRegs[MISCREG_MVFR1] = mvfr1;
+
             //XXX We need to initialize the rest of the state.
         }
 
@@ -273,6 +294,8 @@ namespace ArmISA
                 warn("The csselr register isn't implemented.\n");
                 break;
               case MISCREG_TLBTR:
+              case MISCREG_MVFR0:
+              case MISCREG_MVFR1:
                 return;
             }
             return setMiscRegNoEffect(misc_reg, newVal);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b7521cbd0f736a1406392d9dc5cd43d6c861e050..851044a35295e7353bfa8a8c25cb633f99acc5b8 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -320,6 +320,28 @@ namespace ArmISA
         Bitfield<30> z;
         Bitfield<31> n;
     EndBitUnion(FPSCR)
+
+    BitUnion32(MVFR0)
+        Bitfield<3, 0> advSimdRegisters;
+        Bitfield<7, 4> singlePrecision;
+        Bitfield<11, 8> doublePrecision;
+        Bitfield<15, 12> vfpExceptionTrapping;
+        Bitfield<19, 16> divide;
+        Bitfield<23, 20> squareRoot;
+        Bitfield<27, 24> shortVectors;
+        Bitfield<31, 28> roundingModes;
+    EndBitUnion(MVFR0)
+
+    BitUnion32(MVFR1)
+        Bitfield<3, 0> flushToZero;
+        Bitfield<7, 4> defaultNaN;
+        Bitfield<11, 8> advSimdLoadStore;
+        Bitfield<15, 12> advSimdInteger;
+        Bitfield<19, 16> advSimdSinglePrecision;
+        Bitfield<23, 20> advSimdHalfPrecision;
+        Bitfield<27, 24> vfpHalfPrecision;
+        Bitfield<31, 28> raz;
+    EndBitUnion(MVFR1)
 };
 
 #endif // __ARCH_ARM_MISCREGS_HH__