opcodes/

	* ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
	(extract_fxm): Don't test dialect.
	(XFXFXM_MASK): Include the power4 bit.
	(XFXM): Add p4 param.
	(powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.

gas/testsuite/
	* gas/ppc/power4.d: Update.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0b853b22337a33aab74de4621d379259051fde73..442d5b88d517aa10e816b91948c7ad0c25ed4e55 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2004-06-28  Alan Modra  <amodra@bigpond.net.au>
+
+       * gas/ppc/power4.d: Update.
+
 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 
        * gas/i386/prescott.s: Remove fisttpd and fisttpq.

diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d
index 4a56a271382b55edf93491a5cf218b93a3e1975a..6aabc270087df2acc54910f53fca33ac89ab7c56 100644 (file)
--- a/gas/testsuite/gas/ppc/power4.d
+++ b/gas/testsuite/gas/ppc/power4.d
@@ -82,23 +82,23 @@ Disassembly of section \.text:
  +68:  7c 6f f1 20     mtcr    r3
  +6c:  7c 6f f1 20     mtcr    r3
  +70:  7c 68 11 20     mtcrf   129,r3
- +74:  7c 70 11 20     mtcrf   1,r3
- +78:  7c 70 21 20     mtcrf   2,r3
- +7c:  7c 70 41 20     mtcrf   4,r3
- +80:  7c 70 81 20     mtcrf   8,r3
- +84:  7c 71 01 20     mtcrf   16,r3
- +88:  7c 72 01 20     mtcrf   32,r3
- +8c:  7c 74 01 20     mtcrf   64,r3
- +90:  7c 78 01 20     mtcrf   128,r3
+ +74:  7c 70 11 20     mtocrf  1,r3
+ +78:  7c 70 21 20     mtocrf  2,r3
+ +7c:  7c 70 41 20     mtocrf  4,r3
+ +80:  7c 70 81 20     mtocrf  8,r3
+ +84:  7c 71 01 20     mtocrf  16,r3
+ +88:  7c 72 01 20     mtocrf  32,r3
+ +8c:  7c 74 01 20     mtocrf  64,r3
+ +90:  7c 78 01 20     mtocrf  128,r3
  +94:  7c 60 00 26     mfcr    r3
- +98:  7c 70 10 26     mfcr    r3,1
- +9c:  7c 70 20 26     mfcr    r3,2
- +a0:  7c 70 40 26     mfcr    r3,4
- +a4:  7c 70 80 26     mfcr    r3,8
- +a8:  7c 71 00 26     mfcr    r3,16
- +ac:  7c 72 00 26     mfcr    r3,32
- +b0:  7c 74 00 26     mfcr    r3,64
- +b4:  7c 78 00 26     mfcr    r3,128
+ +98:  7c 70 10 26     mfocrf  r3,1
+ +9c:  7c 70 20 26     mfocrf  r3,2
+ +a0:  7c 70 40 26     mfocrf  r3,4
+ +a4:  7c 70 80 26     mfocrf  r3,8
+ +a8:  7c 71 00 26     mfocrf  r3,16
+ +ac:  7c 72 00 26     mfocrf  r3,32
+ +b0:  7c 74 00 26     mfocrf  r3,64
+ +b4:  7c 78 00 26     mfocrf  r3,128
  +b8:  7c 01 17 ec     dcbz    r1,r2
  +bc:  7c 23 27 ec     dcbzl   r3,r4
  +c0:  7c 05 37 ec     dcbz    r5,r6

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fd4e6e061d46f159cd1ddc9cd048a7aa61ddb1c9..18510c473c7b6d2c5ea3cfec5cb1488f611dddad 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2004-06-28  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
+       (extract_fxm): Don't test dialect.
+       (XFXFXM_MASK): Include the power4 bit.
+       (XFXM): Add p4 param.
+       (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
+
 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 
        2003-07-21  Richard Sandiford  <rsandifo@redhat.com>

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f5ff9baf0d4aca291bf38fe741bda731ac065bfb..9936f3ead44d57b374589af151cfe08ccd37a7ba 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -998,11 +998,22 @@ insert_fxm (unsigned long insn,
            int dialect,
            const char **errmsg)
 {
+  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
+     one bit of the mask field is set.  */
+  if ((insn & (1 << 20)) != 0)
+    {
+      if (value == 0 || (value & -value) != value)
+       {
+         *errmsg = _("invalid mask field");
+         value = 0;
+       }
+    }
+
   /* If the optional field on mfcr is missing that means we want to use
      the old form of the instruction that moves the whole cr.  In that
      case we'll have VALUE zero.  There doesn't seem to be a way to
      distinguish this from the case where someone writes mfcr %r3,0.  */
-  if (value == 0)
+  else if (value == 0)
     ;
 
   /* If only one bit of the FXM field is set, we can use the new form
@@ -1028,7 +1039,7 @@ insert_fxm (unsigned long insn,
 
 static long
 extract_fxm (unsigned long insn,
-            int dialect,
+            int dialect ATTRIBUTE_UNUSED,
             int *invalid)
 {
   long mask = (insn >> 12) & 0xff;
@@ -1036,14 +1047,9 @@ extract_fxm (unsigned long insn,
   /* Is this a Power4 insn?  */
   if ((insn & (1 << 20)) != 0)
     {
-      if ((dialect & PPC_OPCODE_POWER4) == 0)
+      /* Exactly one bit of MASK should be set.  */
+      if (mask == 0 || (mask & -mask) != mask)
        *invalid = 1;
-      else
-       {
-         /* Exactly one bit of MASK should be set.  */
-         if (mask == 0 || (mask & -mask) != mask)
-           *invalid = 1;
-       }
     }
 
   /* Check that non-power4 form of mfcr has a zero MASK.  */
@@ -1681,11 +1687,12 @@ extract_tbr (unsigned long insn,
 #define XS_MASK XS (0x3f, 0x1ff, 1)
 
 /* A mask for the FXM version of an XFX form instruction.  */
-#define XFXFXM_MASK (X_MASK | (1 << 11))
+#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
 
 /* An XFX form instruction with the FXM field filled in.  */
-#define XFXM(op, xop, fxm) \
-  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
+#define XFXM(op, xop, fxm, p4) \
+  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
+   | ((unsigned long)(p4) << 20))
 
 /* An XFX form instruction with the SPR field filled in.  */
 #define XSPR(op, xop, spr) \
@@ -3227,6 +3234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "iseleq",  X(31,79),      X_MASK,    PPCISEL,        { RT, RA, RB } },
 { "isel",    XISEL(31,15),  XISEL_MASK,        PPCISEL,        { RT, RA, RB, CRB } },
 
+{ "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,                { RT, FXM } },
 { "mfcr",    X(31,19), XRARB_MASK,     NOPOWER4,       { RT } },
 { "mfcr",    X(31,19), XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
 
@@ -3382,7 +3390,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbtstlse",X(31,142),X_MASK,                PPCCHLK64,      { CT, RA, RB }},
 
-{ "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,       { RS }},
+{ "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,       { FXM, RS } },
+{ "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,     { RS }},
 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
 
 { "mtmsr",   X(31,146),        XRARB_MASK,     COM,            { RS } },