boards/targets: add ulx3s

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
new file mode 100755 (executable)
index 0000000..0574aa7
--- /dev/null
+++ b/litex/boards/targets/ulx3s.py
@@ -0,0 +1,80 @@
+#!/usr/bin/env python3
+
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.boards.platforms import ulx3s
+
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import MT48LC16M16
+from litedram.phy import GENSDRPHY
+
+
+class _CRG(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys_ps = ClockDomain()
+
+        # # #
+
+        clk25 = platform.request("clk25")
+        rst = platform.request("rst")
+
+        # sys_clk
+        self.comb += self.cd_sys.clk.eq(clk25)
+        # FIXME: AsyncResetSynchronizer needs FD1S3BX support.
+        #self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
+        self.comb += self.cd_sys.rst.eq(rst)
+
+        # sys_clk phase shifted (for sdram)
+        sdram_ps_clk = self.cd_sys.clk
+        # FIXME: phase shift with luts, needs PLL support.
+        sdram_ps_luts = 5
+        for i in range(sdram_ps_luts):
+            new_sdram_ps_clk = Signal()
+            self.specials += Instance("LUT4",
+                p_INIT=2,
+                i_A=sdram_ps_clk,
+                i_B=0,
+                i_C=0,
+                i_D=0,
+                o_Z=new_sdram_ps_clk)
+            sdram_ps_clk = new_sdram_ps_clk
+        self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
+
+
+class BaseSoC(SoCSDRAM):
+    def __init__(self, **kwargs):
+        platform = ulx3s.Platform(toolchain="prjtrellis")
+        sys_clk_freq = int(25e6)
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+                          integrated_rom_size=0x8000,
+                          **kwargs)
+
+        self.submodules.crg = _CRG(platform)
+
+        if not self.integrated_main_ram_size:
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
+            self.register_sdram(self.sdrphy,
+                                sdram_module.geom_settings,
+                                sdram_module.timing_settings)
+
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()