return modules_.count(name) ? modules_.at(name) : NULL;
}
+RTLIL::Module *RTLIL::Design::top_module()
+{
+ RTLIL::Module *module = nullptr;
+ int module_count = 0;
+
+ for (auto mod : selected_modules()) {
+ if (mod->get_bool_attribute("\\top"))
+ return mod;
+ module_count++;
+ module = mod;
+ }
+
+ return module_count == 1 ? module : nullptr;
+}
+
void RTLIL::Design::add(RTLIL::Module *module)
{
log_assert(modules_.count(module->name) == 0);
RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(RTLIL::IdString name);
+ RTLIL::Module *top_module();
bool has(RTLIL::IdString id) const {
return modules_.count(id) != 0;
log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
log("with public names. This ignores all selected ports.\n");
log("\n");
+ log(" rename -top new_name\n");
+ log("\n");
+ log("Rename top module.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_enumerate = false;
bool flag_hide = false;
+ bool flag_top = false;
bool got_mode = false;
size_t argidx;
got_mode = true;
continue;
}
+ if (arg == "-top" && !got_mode) {
+ flag_top = true;
+ got_mode = true;
+ continue;
+ }
if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
int pos = args[++argidx].find('%');
pattern_prefix = args[argidx].substr(0, pos);
}
}
else
+ if (flag_top)
+ {
+ if (argidx+1 != args.size())
+ log_cmd_error("Invalid number of arguments!\n");
+
+ IdString new_name = RTLIL::escape_id(args[argidx]);
+ RTLIL::Module *module = design->top_module();
+
+ if (module == NULL)
+ log_cmd_error("No top module found!\n");
+
+ log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
+ design->modules_.erase(module->name);
+ module->name = new_name;
+ design->modules_[module->name] = module;
+ }
+ else
{
if (argidx+2 != args.size())
log_cmd_error("Invalid number of arguments!\n");