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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 878915662fbaeef76715501129cf9ed83968ed4b..a7a96e7ba83dbd210497dd79825bbc5d309c659b 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -257,15 +257,21 @@ Memory access remains exactly the same: the effects of `MSR.LE` remain
 exactly the same, affecting as they already do and remain **only**
 on the Load and Store memory-register operation byte-order, and having
 nothing to do with the ordering of the contents of register files or
-register-register operations.
+register-register arithmetic or logical operations.
 
 The only major impact on Arithmetic and Logical operations is that all
 Scalar operations are defined, where practical and workable, to have
-three new widths: elwidth=32, elwidth=16, elwidth=8.  The default of
+three new widths: elwidth=32, elwidth=16, elwidth=8.
+
+*Architectural note: a future revision of SVP64 for VSX may have entirely
+different definitions of possible elwidths.*
+
+The default of
 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
 variant of `addi`, but the sole exclusive difference is the width.
-*In no way* is the actual `addi` instruction fundamentally altered.
+*In no way* is the actual `addi` instruction fundamentally altered
+to become an entirely different operation.
 FP Operations elwidth overrides are also defined, as explained in
 the [[svp64/appendix]].
 
@@ -274,7 +280,7 @@ To be absolutely clear:
 ```
     There are no conceptual arithmetic ordering or other changes over the
     Scalar Power ISA definitions to registers or register files or to
-    arithmetic or Logical Operations beyond element-width subdivision
+    arithmetic or Logical Operations, beyond element-width subdivision
 ```
 
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