Add comment on why we have to match for clock-enable/reset muxes

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 09d94ff4b6caa478bb8483966417233d16dd4edf..604aa222b042ce7580c63194c0d0a6570d5bcc38 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -441,7 +441,10 @@ endcode
 // #######################
 
 // Subpattern for matching against input registers, based on knowledge of the
-//   'Q' input.
+//   'Q' input. Typically, identifying registers with clock-enable and reset
+//   capability would be a task would be handled by other Yosys passes such as
+//   dff2dffe, but since DSP inference happens much before this, these patterns
+//   have to be manually identified.
 // At a high level:
 //   (1) Starting from a $dff cell that (partially or fully) drives the given
 //       'Q' argument

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 3f84864067e76f7d47bf00b2aee7eeb79eec0527..2408d483ab4fe69f8c2d9791dfce35e72468f936 100644 (file)
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -105,7 +105,9 @@ endcode
 // #######################
 
 // Subpattern for matching against input registers, based on knowledge of the
-//   'Q' input.
+//   'Q' input. Typically, this task would be handled by other Yosys passes
+//   such as dff2dffe, but since DSP inference happens much before this, these
+//   patterns have to be manually identified.
 // At a high level:
 //   (1) Starting from a $dff cell that (partially or fully) drives the given
 //       'Q' argument

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 42d1aee6c04e24fd31e45258f0cd3bfe45276d85..7a32df2b7d25231c3819864c085b50f5b65aee34 100644 (file)
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -298,7 +298,10 @@ endcode
 // #######################
 
 // Subpattern for matching against input registers, based on knowledge of the
-//   'Q' input.
+//   'Q' input. Typically, identifying registers with clock-enable and reset
+//   capability would be a task would be handled by other Yosys passes such as
+//   dff2dffe, but since DSP inference happens much before this, these patterns
+//   have to be manually identified.
 // At a high level:
 //   (1) Starting from a $dff cell that (partially or fully) drives the given
 //       'Q' argument