Added in handling of the annul bit for branches, and fixed up computation of ccr...

--HG--
extra : convert_revision : ed38d26e13d25e21819dd32d159f1ee4ffcc780b

diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index 823bf2626c9b500e1564b601d24108859e516f84..792918267569aa1bdb21ede70db2fe32a93e75e8 100644 (file)
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -16,16 +16,22 @@ decode OP default Unknown::unknown()
                 0x0: bpcci({{
                     if(passesCondition(CcrIcc, COND2))
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x2: bpccx({{
                     if(passesCondition(CcrXcc, COND2))
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
             }
         }
         0x2: Branch22::bicc({{
             if(passesCondition(CcrIcc, COND2))
                 NNPC = xc->readPC() + disp;
+            else
+                handle_annul
         }});
         0x3: decode RCOND2
         {
@@ -34,26 +40,38 @@ decode OP default Unknown::unknown()
                 0x1: bpreq({{
                     if(Rs1 == 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x2: bprle({{
                     if(Rs1 <= 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x3: bprl({{
                     if(Rs1 < 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x5: bprne({{
                     if(Rs1 != 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x6: bprg({{
                     if(Rs1 > 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
                 0x7: bprge({{
                     if(Rs1 >= 0)
                         NNPC = xc->readPC() + disp;
+                    else
+                        handle_annul
                 }});
             }
         }
@@ -117,22 +135,22 @@ decode OP default Unknown::unknown()
             0x10: addcc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 Rd = resTemp = Rs1 + val2;}},
-                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{(Rs1<31:0> + val2<31:0>)<32:>}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );
             0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
             0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
             0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
             0x14: subcc({{
-                int64_t resTemp, val2 = Rs2_or_imm13;
-                Rd = resTemp = Rs1 - val2;}},
-                {{((Rs1 & 0xFFFFFFFF - val2 & 0xFFFFFFFF) >> 31)}},
-                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                {{(((Rs1 >> 1) + (~val2) >> 1) +
-                    ((Rs1 | ~val2) & 0x1))<63:>}},
-                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+                int64_t val2 = Rs2_or_imm13;
+                Rd = Rs1 - val2;}},
+                {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
+                {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
+                {{(~(Rs1<63:1> + (~val2)<63:1> +
+                    (Rs1 | ~val2)<0:>))<63:>}},
+                {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
             );
             0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
             0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
@@ -141,11 +159,10 @@ decode OP default Unknown::unknown()
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 int64_t carryin = CcrIccC;
                 Rd = resTemp = Rs1 + val2 + carryin;}},
-                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
-                    + carryin)}},
+                {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                {{((Rs1 >> 1) + (val2 >> 1) +
-                    ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
+                {{(Rs1<63:1> + val2<63:1> +
+                    ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );
             0x1A: umulcc({{
@@ -162,9 +179,9 @@ decode OP default Unknown::unknown()
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 int64_t carryin = CcrIccC;
                 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
-                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
+                {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
                 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                {{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
+                {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
                 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
             );
             0x1D: udivxcc({{

diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index b76f7a9f6a1dafebffa3305d8c74dd71b9e5c1ca..37bdb94029d52f098583880d1aaebde11d03c8df 100644 (file)
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -194,7 +194,7 @@ output decoder {{
             {
                 ccprintf(response, " <%s", symbol);
                 if(symbolAddr != target)
-                    ccprintf(response, "+0x%x>", target - symbolAddr);
+                    ccprintf(response, "+%d>", target - symbolAddr);
                 else
                     ccprintf(response, ">");
             }
@@ -226,8 +226,25 @@ def template BranchExecute {{
         }
 }};
 
+let {{
+    handle_annul = '''
+    {
+        if(A)
+        {
+            NPC = xc->readNextNPC();
+            NNPC = NPC + 4;
+        }
+        else
+        {
+            NPC = xc->readNextPC();
+            NNPC = xc->readNextNPC();
+        }
+    }'''
+}};
+
 // Primary format for branch instructions:
 def format Branch(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         (usesImm, code, immCode,
          rString, iString) = splitOutImm(code)
         iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
@@ -247,6 +264,7 @@ def format Branch(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch19(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -257,6 +275,7 @@ def format Branch19(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch22(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -267,6 +286,7 @@ def format Branch22(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch30(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -277,6 +297,7 @@ def format Branch30(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format BranchSplit(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)