Fixed "test_cell -simlib all"

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 09ffa9a688517285b47acc2cd7407e88bafc9c7c..3c931c813617dcd93ecdf6cf60c2f92eba9c9cdd 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -108,12 +108,13 @@ parameter Y_WIDTH = 0;
 
 input [A_WIDTH-1:0] A;
 output [Y_WIDTH-1:0] Y;
+wire [Y_WIDTH-1:0] tmp;
 
 generate
        if (A_SIGNED) begin:BLOCK1
-               assign Y = -$signed(A);
+               assign tmp = $signed(A), Y = -tmp;
        end else begin:BLOCK2
-               assign Y = -A;
+               assign tmp = A, Y = -tmp;
        end
 endgenerate