* mn10300-opc.c (mn10300_operands): Add "REGS" for a register

        list.
        (mn10300_opcodes): Use REGS for register list in "movm" instructions.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9358b149c9923a9a0fc8817649d170c8563ba0ab..f845111f4e22293ccd1f079ca83a4c7051b1893a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+Tue Nov 19 13:33:01 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_operands): Add "REGS" for a register
+       list.
+       (mn10300_opcodes): Use REGS for register list in "movm" instructions.
+       
 start-sanitize-d10v
 Mon Nov 18 15:20:35 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
 

diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c
index cebceac184b592fb67e837a5135d61248456cd0d..9484d4e347745c6edf75ed2ed3a3ee1f346f9d8a 100644 (file)
--- a/opcodes/mn10300-opc.c
+++ b/opcodes/mn10300-opc.c
@@ -150,6 +150,9 @@ const struct mn10300_operand mn10300_operands[] = {
 #define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
   {8, 8, 0},
 
+#define REGS    (IMM8_SHIFT8+1)
+  {8, 0, MN10300_OPERAND_REG_LIST},
+
 } ; 
 
 #define MEM(ADDR) PAREN, ADDR, PAREN 
@@ -280,8 +283,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "exth",      0x18,           0xfc,           FMT_S0, {DN0}},
 { "exthu",     0x1c,           0xfc,           FMT_S0, {DN0}},
 
-{ "movm",      0xce00,         0xff00,         FMT_S1, {MEM(SP), IMM8}},
-{ "movm",      0xcf00,         0xff00,         FMT_S1, {IMM8, MEM(SP)}},
+{ "movm",      0xce00,         0xff00,         FMT_S1, {MEM(SP), REGS}},
+{ "movm",      0xcf00,         0xff00,         FMT_S1, {REGS, MEM(SP)}},
 
 { "clr",       0x00,           0xf3,           FMT_S0, {DN1}},