invoke.texi (RS/6000 and PowerPC Options): Document -mspe option.

 2003-04-06  Aldy Hernandez  <aldyh@redhat.com>

        * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mspe
        option.

        * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set
        rs6000_spe.

        * config/rs6000/eabi.h (TARGET_E500): Define.

        * config/rs6000/rs6000.h (TARGET_E500): Define.
        (TARGET_OPTIONS): Add spe= option.
        Declare rs6000_spe and rs6000_spe_string extern.

        * config/rs6000/rs6000.c (branch_positive_comparison_operator):
        Change TARGET_SPE to TARGET_E500.
        (ccr_bit): Change TARGET_SPE to TARGET_E500.  Check for
        !TARGET_FPRS.
        (print_operand): Same.
        (rs6000_generate_compare): Same.
        (output_cbranch): Same.
        (rs6000_spe): Declare.
        (rs6000_spe_string): Declare.
        (rs6000_override_options): Call rs6000_parse_spe_option.
        (rs6000_parse_spe_option): New.

From-SVN: r65319

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6cf593c99cce4b0a5c8fa815edeb36edc8c98f23..ca209182bc0b096d22d57f21a99101eec718daa9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+2003-04-06  Aldy Hernandez  <aldyh@redhat.com>
+
+        * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mspe
+        option.
+
+        * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set
+        rs6000_spe.
+
+        * config/rs6000/eabi.h (TARGET_E500): Define.
+
+        * config/rs6000/rs6000.h (TARGET_E500): Define.
+        (TARGET_OPTIONS): Add spe= option.
+        Declare rs6000_spe and rs6000_spe_string extern.
+
+        * config/rs6000/rs6000.c (branch_positive_comparison_operator):
+        Change TARGET_SPE to TARGET_E500.
+        (ccr_bit): Change TARGET_SPE to TARGET_E500.  Check for
+        !TARGET_FPRS.
+        (print_operand): Same.
+        (rs6000_generate_compare): Same.
+        (output_cbranch): Same.
+        (rs6000_spe): Declare.
+        (rs6000_spe_string): Declare.
+        (rs6000_override_options): Call rs6000_parse_spe_option.
+        (rs6000_parse_spe_option): New.
+
 2003-04-06  Steven Bosscher  <steven@gcc.gnu.org>
 
        * hashtable.c (gcc_obstack_init): Delete this function

diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h
index 373dd2b6fc702b575150d06f1026faa9f960ecb8..e61a91fae6b6827b6adde4e66fa1d8cc3517912f 100644 (file)
--- a/gcc/config/rs6000/eabi.h
+++ b/gcc/config/rs6000/eabi.h
@@ -45,10 +45,12 @@ Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_SPE_ABI
 #undef TARGET_SPE
+#undef TARGET_E500
 #undef TARGET_ISEL
 #undef TARGET_FPRS
 
 #define TARGET_SPE_ABI rs6000_spe_abi
-#define TARGET_SPE (rs6000_cpu == PROCESSOR_PPC8540)
+#define TARGET_SPE rs6000_spe
+#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
 #define TARGET_ISEL rs6000_isel
 #define TARGET_FPRS rs6000_fprs

diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h
index bfec030b9de42fdbc431b06244d54e7f916a4ade..5cbe7f7ba5e6ee9efc978128e593e719039fec43 100644 (file)
--- a/gcc/config/rs6000/eabispe.h
+++ b/gcc/config/rs6000/eabispe.h
@@ -36,6 +36,8 @@ Boston, MA 02111-1307, USA.  */
   /* See note below.  */ \
   /*if (rs6000_long_double_size_string == NULL)*/ \
   /*  rs6000_long_double_type_size = 128;*/ \
+  if (rs6000_spe_string == NULL) \
+    rs6000_spe = 1; \
   if (rs6000_isel_string == NULL) \
     rs6000_isel = 1
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d62bbd336fa7e2e36c393c9ce53212bd2208fcfe..921d25da23cdb12f8e430cd29c65564af8d23c39 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -95,12 +95,18 @@ int rs6000_spe_abi;
 /* Whether isel instructions should be generated.  */
 int rs6000_isel;
 
+/* Whether SPE simd instructions should be generated.  */
+int rs6000_spe;
+
 /* Nonzero if we have FPRs.  */
 int rs6000_fprs = 1;
 
 /* String from -misel=.  */
 const char *rs6000_isel_string;
 
+/* String from -mspe=.  */
+const char *rs6000_spe_string;
+
 /* Set to nonzero once AIX common-mode calls have been defined.  */
 static GTY(()) int common_mode_defined;
 
@@ -270,6 +276,7 @@ static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
 static void rs6000_parse_abi_options PARAMS ((void));
 static void rs6000_parse_vrsave_option PARAMS ((void));
 static void rs6000_parse_isel_option PARAMS ((void));
+static void rs6000_parse_spe_option (void);
 static int first_altivec_reg_to_save PARAMS ((void));
 static unsigned int compute_vrsave_mask PARAMS ((void));
 static void is_altivec_return_reg PARAMS ((rtx, void *));
@@ -612,7 +619,7 @@ rs6000_override_options (default_cpu)
        }
     }
 
-  if (rs6000_cpu == PROCESSOR_PPC8540)
+  if (TARGET_E500)
     rs6000_isel = 1;
 
   /* If we are optimizing big endian systems for space, use the load/store
@@ -701,6 +708,9 @@ rs6000_override_options (default_cpu)
   /* Handle -misel= option.  */
   rs6000_parse_isel_option ();
 
+  /* Handle -mspe= option.  */
+  rs6000_parse_spe_option ();
+
 #ifdef SUBTARGET_OVERRIDE_OPTIONS
   SUBTARGET_OVERRIDE_OPTIONS;
 #endif
@@ -788,6 +798,20 @@ rs6000_parse_isel_option ()
          rs6000_isel_string);
 }
 
+/* Handle -mspe= option.  */
+static void
+rs6000_parse_spe_option (void)
+{
+  if (rs6000_spe_string == 0)
+    return;
+  else if (!strcmp (rs6000_spe_string, "yes"))
+    rs6000_spe = 1;
+  else if (!strcmp (rs6000_spe_string, "no"))
+    rs6000_spe = 0;
+  else
+    error ("unknown -mspe= option specified: '%s'", rs6000_spe_string);
+}
+
 /* Handle -mvrsave= options.  */
 static void
 rs6000_parse_vrsave_option ()
@@ -7009,7 +7033,7 @@ branch_positive_comparison_operator (op, mode)
 
   code = GET_CODE (op);
   return (code == EQ || code == LT || code == GT
-         || (TARGET_SPE && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
+         || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
          || code == LTU || code == GTU
          || code == UNORDERED);
 }
@@ -7469,11 +7493,13 @@ ccr_bit (op, scc_p)
   switch (code)
     {
     case NE:
-      if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
+      if (TARGET_E500 && !TARGET_FPRS
+         && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
        return base_bit + 1;
       return scc_p ? base_bit + 3 : base_bit + 2;
     case EQ:
-      if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
+      if (TARGET_E500 && !TARGET_FPRS
+         && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
        return base_bit + 1;
       return base_bit + 2;
     case GT:  case GTU:  case UNLE:
@@ -7685,7 +7711,7 @@ print_operand (file, x, code)
          fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
                   base_bit + 2, base_bit + 2);
        }
-      else if (TARGET_SPE && TARGET_HARD_FLOAT
+      else if (TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT
               && GET_CODE (x) == EQ
               && GET_MODE (XEXP (x, 0)) == CCFPmode)
        {
@@ -8192,7 +8218,7 @@ print_operand (file, x, code)
 
        tmp = XEXP (x, 0);
 
-       if (TARGET_SPE)
+       if (TARGET_E500)
          {
            /* Handle [reg].  */
            if (GET_CODE (tmp) == REG)
@@ -8477,7 +8503,8 @@ rs6000_generate_compare (code)
   compare_result = gen_reg_rtx (comp_mode);
 
   /* SPE FP compare instructions on the GPRs.  Yuck!  */
-  if ((TARGET_SPE && TARGET_HARD_FLOAT) && rs6000_compare_fp_p)
+  if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
+      && rs6000_compare_fp_p)
     {
       rtx cmp, or1, or2, or_result, compare_result2;
 
@@ -8602,7 +8629,7 @@ rs6000_generate_compare (code)
      except for flag_unsafe_math_optimizations we don't bother.  */
   if (rs6000_compare_fp_p
       && ! flag_unsafe_math_optimizations
-      && ! (TARGET_HARD_FLOAT && TARGET_SPE)
+      && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
       && (code == LE || code == GE
          || code == UNEQ || code == LTGT
          || code == UNGT || code == UNLT))
@@ -8730,7 +8757,7 @@ output_cbranch (op, label, reversed, insn)
        code = reverse_condition (code);
     }
 
-  if ((TARGET_SPE && TARGET_HARD_FLOAT) && mode == CCFPmode)
+  if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
     {
       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
         to the GT bit.  */

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 0d8085c4e3f23674650eac7d3310815d78995480..10d6233af56d56f7c5ce50d3e9bc72e082150313 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -388,6 +388,8 @@ extern enum processor_type rs6000_cpu;
     N_("Specify size of long double (64 or 128 bits)") },              \
    {"isel=", &rs6000_isel_string,                                       \
     N_("Specify yes/no if isel instructions should be generated") },    \
+   {"spe=", &rs6000_spe_string,                                         \
+    N_("Specify yes/no if SPE SIMD instructions should be generated") },\
    {"vrsave=", &rs6000_altivec_vrsave_string,                         \
     N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
    {"longcall", &rs6000_longcall_switch,                               \
@@ -425,8 +427,10 @@ extern int rs6000_long_double_type_size;
 extern int rs6000_altivec_abi;
 extern int rs6000_spe_abi;
 extern int rs6000_isel;
+extern int rs6000_spe;
 extern int rs6000_fprs;
 extern const char *rs6000_isel_string;
+extern const char *rs6000_spe_string;
 extern const char *rs6000_altivec_vrsave_string;
 extern int rs6000_altivec_vrsave;
 extern const char *rs6000_longcall_switch;
@@ -438,6 +442,7 @@ extern int rs6000_default_long_calls;
 
 #define TARGET_SPE_ABI 0
 #define TARGET_SPE 0
+#define TARGET_E500 0
 #define TARGET_ISEL 0
 #define TARGET_FPRS 1
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3d8026cc847c672404aa0a0f7d51a934b829ecc1..fac5ae922cfc50f6896b9f14c23bfba0cc68c436 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -447,6 +447,7 @@ in the following sections.
 -mabi=altivec -mabi=no-altivec @gol
 -mabi=spe -mabi=no-spe @gol
 -misel=yes -misel=no @gol
+-mspe=yes -mspe=no @gol
 -mprototype  -mno-prototype @gol
 -msim  -mmvme  -mads  -myellowknife  -memb -msdata @gol
 -msdata=@var{opt}  -mvxworks -mwindiss -G @var{num} -pthread}
@@ -7028,6 +7029,12 @@ Disable Booke SPE ABI extensions for the current ABI.
 @opindex misel
 This switch enables or disables the generation of ISEL instructions.
 
+@item -mspe=@var{yes/no}
+@itemx -mspe
+@opindex mspe
+This switch enables or disables the generation of SPE simd
+instructions.
+
 @item -mfull-toc
 @itemx -mno-fp-in-toc
 @itemx -mno-sum-in-toc