sparc.md (TFmode splits): Handle destination registers being referenced in the addres...

	* config/sparc/sparc.md (TFmode splits): Handle destination
	registers being referenced in the address correctly.

From-SVN: r21901

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0c72f9286305bd58e85ae3d7bfe1f39e96b1927c..319d3145150a44cd27821ae89ab4b6c63d9b8393 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Fri Aug 21 23:07:46 1998  David S. Miller  <davem@pierdol.cobaltmicro.com>
+
+       * config/sparc/sparc.md (TFmode splits): Handle destination
+       registers being referenced in the address correctly.
+
 Fri Aug 21 19:31:31 1998  Alexandre Petit-Bianco <apbianco@cygnus.com>
 
        * tree.def (LABELED_BLOCK_EXPR, EXIT_BLOCK_EXPR): New tree nodes.

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 365d1638f5d1bf549f544ad65a970468593f9891..9796ec794de5a50ddb63e629074cbd65bdd6cfda 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -3333,12 +3333,26 @@
   rtx word1 = change_address (operands[1], DFmode,
                              plus_constant_for_output (XEXP (word0, 0), 8));
   rtx dest1, dest2;
+  int self_reference = reg_mentioned_p (operands[0],
+                                        XEXP (XEXP (word1, 0), 0));
 
   /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
   dest1 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN == 0);
   dest2 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN != 0);
-  emit_insn (gen_movdf (dest1, word0));
-  emit_insn (gen_movdf (dest2, word1));
+
+  /* Now output, ordering such that we don't clobber any registers
+     mentioned in the address.  */
+  if (self_reference != 0
+      && WORDS_BIG_ENDIAN)
+    {
+      emit_insn (gen_movdf (dest2, word1));
+      emit_insn (gen_movdf (dest1, word0));
+    }
+  else
+   {
+      emit_insn (gen_movdf (dest1, word0));
+      emit_insn (gen_movdf (dest2, word1));
+   }
   DONE;
 }")