#define DBX_DEBUGGING_INFO
-/* Generate SDB debugging information by default. */
+/* Generate SDB debugging information by default. */
#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
#define CONDITIONAL_REGISTER_USAGE \
- /* Hitachi saves and restores mac registers on call */ \
+ /* Hitachi saves and restores mac registers on call. */ \
if (TARGET_HITACHI) \
{ \
call_used_regs[MACH_REG] = 0; \
call_used_regs[MACL_REG] = 0; \
- }
-
+ }
\f
-/* Run-time compilation parameters selecting different hardware subsets. */
+/* Run-time compilation parameters selecting different hardware subsets. */
extern int target_flags;
#define ISIZE_BIT (1<<1)
#define PACKSTRUCT_BIT (1<<28)
#define LITTLE_ENDIAN_BIT (1<<29)
-/* Nonzero if we should generate code using type 0 insns */
+/* Nonzero if we should generate code using type 0 insns. */
#define TARGET_SH0 (target_flags & SH0_BIT)
-/* Nonzero if we should generate code using type 1 insns */
+/* Nonzero if we should generate code using type 1 insns. */
#define TARGET_SH1 (target_flags & SH1_BIT)
-/* Nonzero if we should generate code using type 2 insns */
+/* Nonzero if we should generate code using type 2 insns. */
#define TARGET_SH2 (target_flags & SH2_BIT)
-/* Nonzero if we should generate code using type 3 insns */
+/* Nonzero if we should generate code using type 3 insns. */
#define TARGET_SH3 (target_flags & SH3_BIT)
-/* Nonzero if we should generate faster code rather than smaller code */
+/* Nonzero if we should generate faster code rather than smaller code. */
#define TARGET_FASTCODE (target_flags & FAST_BIT)
-/* Nonzero if we should generate smaller code rather than faster code */
+/* Nonzero if we should generate smaller code rather than faster code. */
#define TARGET_SMALLCODE (target_flags & SPACE_BIT)
-/* Nonzero if we should dump out instruction size info */
+/* Nonzero if we should dump out instruction size info. */
#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
-/* Nonzero if we should dump the rtl in the assembly file. */
+/* Nonzero if we should dump the rtl in the assembly file. */
#define TARGET_DUMP_RTL (target_flags & RTL_BIT)
-/* Nonzero if we should dump the rtl somewher else. */
+/* Nonzero if we should dump the rtl somewher else. */
#define TARGET_DUMP_R (target_flags & R_BIT)
-/* Nonzero to align doubles on 64 bit boundaries */
+/* Nonzero to align doubles on 64 bit boundaries. */
#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
-/* Nonzero to use long jump tables */
+/* Nonzero to use long jump tables. */
#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
-/* Nonzero if combine dumping wanted */
+/* Nonzero if combine dumping wanted. */
#define TARGET_CDUMP (target_flags & C_BIT)
-/* Select max size of computed constant code sequences to be 3 insns */
+/* Select max size of computed constant code sequences to be 3 insns. */
#define TARGET_CLEN3 (target_flags & CONSTLEN_3_BIT)
-/* Select max size of computed constant code sequences to be 0 insns - ie don't do it */
+/* Select max size of computed constant code sequences to be 0 insns -
+ i.e. don't do it. */
#define TARGET_CLEN0 (target_flags & CONSTLEN_0_BIT)
-/* Nonzero if using Hitachi's calling convention */
+/* Nonzero if using Hitachi's calling convention. */
#define TARGET_HITACHI (target_flags & HITACHI_BIT)
-/* Nonzero if packing structures as small as they'll go (incompatible with Hitachi's compiler) */
+/* Nonzero if packing structures as small as they'll go (incompatible
+ with Hitachi's compiler). */
#define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT)
sh_cpu = CPU_SH3|CPU_SH2; \
\
/* We *MUST* always define optimize since we *HAVE* to run \
- shorten branches to get correct code. */ \
+ shorten branches to get correct code. */ \
\
optimize = 1; \
flag_delayed_branch = 1; \
/* But never run scheduling before reload, since than can \
break global alloc, and generates slower code anyway due \
- to the pressure on R0. */ \
+ to the pressure on R0. */ \
flag_schedule_insns = 0; \
if (max_si) \
max_count_si = atoi (max_si); \
else \
max_count_hi = 500; \
} while (0)
-
\f
/* Target machine storage Layout. */
/* Define to use software floating point emulator for REAL_ARITHMETIC and
- decimal <-> binary conversion. */
+ decimal <-> binary conversion. */
#define REAL_ARITHMETIC
/* Define this if most significant bit is lowest numbered
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#endif
-/* Number of bits in an addressable storage unit */
+/* Number of bits in an addressable storage unit. */
#define BITS_PER_UNIT 8
/* Width in bits of a "word", which is the contents of a machine register.
/* Number of bits which any structure or union's size must be a
multiple of. Each structure or union's size is rounded up to a
- multiple of this. */
+ multiple of this. */
#define STRUCTURE_SIZE_BOUNDARY (TARGET_PACKSTRUCT ? 8 : 32)
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
-
\f
/* Standard register usage. */
ap arg pointer (doesn't really exist, always eliminated)
pr subroutine return address
t t bit
- mach multiply/accumulate result
- macl
-*/
+ mach multiply/accumulate result, high part
+ macl multiply/accumulate result, low part. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers. */
+ even those that are not normally considered general registers. */
-#define AP_REG 16
+#define AP_REG 16
#define PR_REG 17
#define T_REG 18
#define GBR_REG 19
#define FIRST_PSEUDO_REGISTER 22
/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
+ and are not available for the register allocator.
Mach register is fixed 'cause it's only 10 bits wide for SH1.
It is 32 bits wide for SH2. */
- /* r0 r1 r2 r3
+ /* r0 r1 r2 r3
r4 r5 r6 r7
r8 r9 r10 r11
r12 r13 r14 r15
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
- /* r0 r1 r2 r3
- r4 r5 r6 r7
+ /* r0 r1 r2 r3
+ r4 r5 r6 r7
r8 r9 r10 r11
r12 r13 r14 r15
- ap pr t gbr
+ ap pr t gbr
mh ml */
#define CALL_USED_REGISTERS \
0, 0, 0, 0, \
0, 0, 0, 1, \
1, 0, 1, 1, \
- 1, 1}
+ 1, 1}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the SH regs are UNITS_PER_WORD bits wide; */
+ On the SH regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
(((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- We may keep double values in even registers */
+ We may keep double values in even registers. */
extern int hard_regno_mode_ok[];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
/* Register in which the static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 13
-/* The register in which a struct value address is passed */
+/* The register in which a struct value address is passed. */
#define STRUCT_VALUE_REGNUM 2
exactly how to return structures in the RETURN_IN_MEMORY macro. */
#define DEFAULT_PCC_STRUCT_RETURN 0
-
\f
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
For any two classes, it is very desirable that there be another
class that represents their union. */
-/* The SH has two sorts of general registers, R0 and the rest. R0 can
+/* The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the
- Procedure Return Register and the Multipy Accumulate Registers */
+ Procedure Return Register and the Multipy Accumulate Registers. */
enum reg_class
{
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
/* When defined, the compiler allows registers explicitly used in the
rtl to be used as spill registers but prevents the compiler from
- extending the lifetime of these registers. */
+ extending the lifetime of these registers. */
#define SMALL_REGISTER_CLASSES
#define INDEX_REG_CLASS R0_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Get reg_class from a letter such as appears in the machine
- description. */
+/* Get reg_class from a letter such as appears in the machine
+ description. */
extern enum reg_class reg_class_from_letter[];
#define REG_CLASS_FROM_LETTER(C) \
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
-/* Return the register class of a scratch register needed to copy IN into
- or out of a register in CLASS in MODE. If it can be done directly,
- NO_REGS is returned. */
-
-
/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS.
+ needed to represent mode MODE in a register of class CLASS.
- On SH this is the size of MODE in words */
+ On SH this is the size of MODE in words. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-
\f
/* Stack layout; function entry, exit and calling. */
/* Define this if pushing a word on the stack
makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
+#define STACK_GROWS_DOWNWARD
/* Define this macro if the addresses of local variable slots are at
negative offsets from the frame pointer.
- The SH only has positive indexes, so grow the frame up
-*/
+ The SH only has positive indexes, so grow the frame up. */
/* #define FRAME_GROWS_DOWNWARD */
/* Offset from the frame pointer to the first local variable slot to
- be allocated. */
+ be allocated. */
#define STARTING_FRAME_OFFSET 0
/* If we generate an insn to push BYTES bytes,
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == FIRST_RET_REG)
-/* 1 if N is a possible register number for function argument passing.*/
+/* 1 if N is a possible register number for function argument passing. */
#define FUNCTION_ARG_REGNO_P(REGNO) \
((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
-
-
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
#define ROUND_ADVANCE(SIZE) \
((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Round a register number up to a proper boundary for an arg of mode
- MODE.
-
+/* Round a register number up to a proper boundary for an arg of mode
+ MODE.
+
The SH doesn't care about double alignment, so we only
- round doubles to even regs when asked to explicitly. */
+ round doubles to even regs when asked to explicitly. */
#define ROUND_REG(X, MODE) \
((TARGET_ALIGN_DOUBLE \
NPARM_REGS words is at least partially passed in a register unless
its data type forbids. */
-
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
sh_function_arg (CUM, MODE, TYPE, NAMED)
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
For args passed entirely in registers or entirely in memory, zero.
-
- We sometimes split args */
+
+ We sometimes split args. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
extern int current_function_anonymous_args;
/* Perform any needed actions needed for a function that is receiving a
- variable number of arguments. */
+ variable number of arguments. */
#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
current_function_anonymous_args = 1;
-
-/* Call the function profiler with a given profile label. */
+/* Call the function profiler with a given profile label. */
#define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
}
-
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
#define EXIT_IGNORE_STACK 1
-/* Generate the assembly code for function exit
- Just dump out any accumulated constant table.*/
+/* Generate the assembly code for function exit
+ Just dump out any accumulated constant table. */
#define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
-
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
3 0004 4D2B jmp @r13
4 0006 200B or r0,r0
5 0008 00000000 l1: .long function
- 6 000c 00000000 l2: .long area
-*/
+ 6 000c 00000000 l2: .long area */
#define TRAMPOLINE_TEMPLATE(FILE) \
{ \
fprintf ((FILE), " .word 0xd301\n"); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
(FNADDR)); \
}
-
\f
/* Addressing modes, and classification of registers for them. */
#define HAVE_POST_INCREMENT 1
They give nonzero only if REGNO is a hard reg of the suitable class
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c.
-
-*/
+ has been allocated, which happens in local-alloc.c. */
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
-/* Maximum number of registers that can appear in a valid memory
- address. */
+/* Maximum number of registers that can appear in a valid memory
+ address. */
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF)
-/* Nonzero if the constant value X is a legitimate general operand. */
+/* Nonzero if the constant value X is a legitimate general operand. */
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE(X) != CONST_DOUBLE /*&& GET_CODE(X) != LABEL_REF*/)
-
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
We have two alternate definitions for each of them.
#define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
#define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
-/* ??? These two work only if the target is R0, so we do not support them. */
-#define MODE_DISP_OK_2(X,MODE) (0)
-#define MODE_DISP_OK_1(X,MODE) (0)
#ifndef REG_OK_STRICT
-
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
(REGNO_OK_FOR_BASE_P (REGNO (X)))
#endif
-/* The Q is a pc relative load operand */
+/* The Q is a pc relative load operand. */
#define EXTRA_CONSTRAINT_Q(OP) \
(GET_CODE (OP) == MEM && \
((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
: 0)
-
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
/* Jump to LABEL if X is a valid address RTX. This must also take
REG_OK_STRICT into account when deciding about valid registers, but it uses
- the above macros so we are in luck.
-
+ the above macros so we are in luck.
+
Allow REG
REG+disp
REG+r0
REG++
- --REG
-*/
+ --REG */
-/* The SH allows a displacement in a QI or HI amode, but only when the
+/* The SH allows a displacement in a QI or HI amode, but only when the
other operand is R0. GCC doesn't handle this very well, so we forgo
all of that.
- A legitimate index for a QI or HI is 0, SI and above can be any
- number 0..63 */
+ A legitimate index for a QI or HI is 0, SI and above can be any
+ number 0..63. */
#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
do { \
{ \
if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
- if (MODE_DISP_OK_2 (OP, MODE)) goto LABEL; \
- if (MODE_DISP_OK_1 (OP, MODE)) goto LABEL; \
} \
} while(0)
&& GET_CODE (XEXP (X, 0)) == REG \
&& REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
goto LABEL; \
-}
-
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
+}
+\f
+/* Try machine-dependent ways of modifying an illegitimate address
to be legitimate. If we find one, return the new, valid address.
This macro is used in only one place: `memory_address' in explow.c.
GO_IF_LEGITIMATE_ADDRESS.
It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
-
- */
+ opportunities to optimize the output. */
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
/* Define this if the tablejump instruction expects the table
to contain offsets from the address of the table.
Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE
+#define CASE_VECTOR_PC_RELATIVE
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* This is the kind of divide that is easiest to do in the general case. */
#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-/* 'char' is signed by default */
+/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
/* The type of size_t unsigned int. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Define this if zero-extension is slow (more than one real instruction).
- On the SH, it's only one instruction */
+ On the SH, it's only one instruction. */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
/* Chars and shorts should be passed as ints. */
#define PROMOTE_PROTOTYPES 1
-/* The machine modes of pointers and functions */
+/* The machine modes of pointers and functions. */
#define Pmode SImode
#define FUNCTION_MODE Pmode
return COSTS_N_INSNS (multcosts (X)); \
case ASHIFT: \
case ASHIFTRT: \
+ case LSHIFTRT: \
return COSTS_N_INSNS (shiftcosts (X)) ; \
case DIV: \
case UDIV: \
are actually function calls with some special constraints on arguments
and register usage.
- These macros tell reorg that the references to arguments and
- register clobbers for insns of type sfunc do not appear to happen
+ These macros tell reorg that the references to arguments and
+ register clobbers for insns of type sfunc do not appear to happen
until after the millicode call. This allows reorg to put insns
which set the argument registers into the delay slot of the millicode
call -- thus they act more like traditional CALL_INSNs.
&& GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \
- && get_attr_type (X) == TYPE_SFUNC))
+ && get_attr_type (X) == TYPE_SFUNC))
/* Compute extra cost of moving data between one register class
- and another.
+ and another.
On the SH it is hard to move into the T reg, but simple to load
- from it.
-*/
+ from it. */
#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
(((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
\f
-/* Assembler output control */
+/* Assembler output control. */
-/* The text to go at the start of the assembler file */
-#define ASM_FILE_START(STREAM) \
- output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
- W_options, sizeof W_options / sizeof W_options[0]);
-
-
-#define ASM_FILE_END(STREAM)
+/* The text to go at the start of the assembler file. */
+#define ASM_FILE_START(STREAM) \
+ output_file_start (STREAM, f_options, \
+ sizeof f_options / sizeof f_options[0], \
+ W_options, sizeof W_options / sizeof W_options[0]);
+#define ASM_FILE_END(STREAM)
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
#define FILE_ASM_OP "\t.file\n"
#define IDENT_ASM_OP "\t.ident\n"
-/* How to change between sections. */
+/* How to change between sections. */
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
in_section = in_dtors; \
} \
-}
+}
/* A C statement to output something to the assembler file to switch to section
NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
-#undef DO_GLOBAL_CTORS_BODY
+#undef DO_GLOBAL_CTORS_BODY
#define DO_GLOBAL_CTORS_BODY \
{ \
{ \
(*--p)(); \
} \
-}
+}
-#undef DO_GLOBAL_DTORS_BODY
+#undef DO_GLOBAL_DTORS_BODY
#define DO_GLOBAL_DTORS_BODY \
{ \
typedef (*pfunc)(); \
{ \
(*p)(); \
} \
-}
+}
#define ASM_OUTPUT_REG_PUSH(file, v) \
#define ASM_OUTPUT_REG_POP(file, v) \
fprintf (file, "\tmov.l @r15+,r%s\n", v);
-
+
/* The assembler's names for the registers. RFP need not always be used as
the Real framepointer; it can also be used as a normal general register.
Note that the name `fp' is horribly misleading since `fp' is in fact only
"ap", "pr", "t", "gbr", "mach","macl" \
}
-/* DBX register number for a given compiler register number */
+/* DBX register number for a given compiler register number. */
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
/* Output a label definition. */
((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
-/* Jump tables must be 32 bit aligned, no matter the size of the element */
+/* Jump tables must be 32 bit aligned, no matter the size of the element. */
#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
-/* Output a relative address table. */
+/* Output a relative address table. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
if (TARGET_BIGTABLE) \
else \
fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
-/* Output an absolute table element */
+/* Output an absolute table element. */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (TARGET_BIGTABLE) \
/* Output various types of constants. */
-/* This is how to output an assembler line defining a `double' */
+/* This is how to output an assembler line defining a `double'. */
#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
do { char dstr[30]; \
#define ASM_OUTPUT_INT(STREAM, EXP) \
(fprintf (STREAM, "\t.long\t"), \
output_addr_const (STREAM, (EXP)), \
- fputc ('\n', STREAM))
+ fputc ('\n', STREAM))
#define ASM_OUTPUT_SHORT(STREAM, EXP) \
(fprintf (STREAM, "\t.short\t"), \
output_addr_const (STREAM, (EXP)), \
- fputc ('\n', STREAM))
+ fputc ('\n', STREAM))
#define ASM_OUTPUT_CHAR(STREAM, EXP) \
(fprintf (STREAM, "\t.byte\t"), \
#define TARGET_FF 014
#define TARGET_CR 015
\f
-
/* Only perform branch elimination (by making instructions conditional) if
we're optimising. Otherwise it's of no use anyway. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
-
\f
extern struct rtx_def *sh_compare_op0;
extern struct rtx_def *sh_compare_op1;
extern struct rtx_def *prepare_scc_operands();
-extern struct rtx_def *table_lab;
-/* ??? Wrong, this is an incomplete enum type. Fix this to do it the same
- way that the mips compiler does this. */
-extern enum attr_cpu sh_cpu; /* target cpu */
+/* Which processor to schedule for. The elements of the enumeration must
+ match exactly the cpu attribute in the sh.md file. */
-/* Declare functions defined in sh.c and used in templates. */
+enum processor_type {
+ PROCESSOR_SH0,
+ PROCESSOR_SH1,
+ PROCESSOR_SH2,
+ PROCESSOR_SH3
+};
+
+#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
+extern enum processor_type sh_cpu;
+
+/* Declare functions defined in sh.c and used in templates. */
extern char *output_branch();
extern char *output_shift();
extern char *output_jump_label_table();
extern char *output_far_jump();
-
#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
/* Generate calls to memcpy, memcmp and memset. */
#define HANDLE_PRAGMA(finput) return handle_pragma (finput)
-/* Set when processing a function with pragma interrupt turned on. */
+/* Set when processing a function with pragma interrupt turned on. */
extern int pragma_interrupt;
#define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16)
/* Instructions with unfilled delay slots take up an extra two bytes for
the nop in the delay slot. */
-/* ??? Does this catch conditional branches when -m2? */
-
#define ADJUST_INSN_LENGTH(X, LENGTH) \
if (((GET_CODE (X) == INSN \
&& GET_CODE (PATTERN (X)) != SEQUENCE \
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