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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index f470b2868fe32ff933972d00c8cfe558a998c26d..c01b4b04202834fa43adfbe718cb8b4c696dcb67 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -20,11 +20,12 @@ Register x 3 -> register operations:
 | ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
 | rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
 
-mm values:
-mm = 00 -> use current global saturation or rounding, no mask
-mm = 00 -> force saturation or rounding for this instruction only
-mm = 10 -> use v1 as predicate mask
-mm = 11 -> use ~v1 as predicate mask
+Values for mm field (bits 12:13 above):
+
+* mm = 00 -> use current global saturation or rounding, no mask
+* mm = 00 -> force saturation or rounding for this instruction only
+* mm = 10 -> use v1 as predicate mask
+* mm = 11 -> use ~v1 as predicate mask
 
 ## Register file