Squelch a little more trailing whitespace

diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v
index 744dbe9e39ff36f5cca64b6516ef433cc6c5bab9..92329a6f94c5ba793349ed3b8ccba9f8158d6421 100644 (file)
--- a/backends/simplec/test00_uut.v
+++ b/backends/simplec/test00_uut.v
@@ -3,12 +3,12 @@ module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
   unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
   assign z = a ^ b ^ c, w = z;
 endmodule
-  
+
 module unit_x(input [31:0] a, b, c, output [31:0] x);
   assign x = (a & b) | c;
 endmodule
-  
+
 module unit_y(input [31:0] a, b, c, output [31:0] y);
   assign y = a & (b | c);
 endmodule
-  
+

diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv
index 74ab9343035d8e7dea13ae521a05e9e476021e86..d5ad497dd0a78ce13a642b8f2a27d4f5cb4fc5db 100644 (file)
--- a/tests/sva/basic01.sv
+++ b/tests/sva/basic01.sv
@@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
                write <= ctrl;
                ready <= write;
        end
-       
+
        a_rw: assert property ( @(posedge clock) !(read && write) );
 `ifdef FAIL
        a_wr: assert property ( @(posedge clock) write |-> ready );