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Added brackets for lhaux instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Tue, 26 Sep 2023 10:29:47 +0000 (11:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
openpower/isa/fixedload.mdwn patch | blob | history

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 16575ce598f1fe3e253628302c21098b52ead7ad..1199024d3ed3019e5b04be53474f86781fc6462d 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -307,7 +307,7 @@ Description:
 
     Let the effective address (EA) be the sum (RA)+ (RB).
     The halfword in storage addressed by EA is loaded into
-    RT48:63. RT 0:47 are filled with a copy of bit 0 of the
+    RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
     loaded halfword.
 
     EA is placed into register RA.