radeonsi/gfx9: set optimal OVERWRITE_COMBINER_WATERMARK

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index dc95afb7421079d0c1818aa90c52148bf11b594d..0807c8ddacc2bfd3fee1d1a1fe97f377a3ffa70f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -617,6 +617,7 @@ struct si_framebuffer {
        ubyte                           color_is_int8;
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
+       ubyte                           dcc_overwrite_combiner_watermark;
        bool                            dirty_zsbuf;
        bool                            any_dst_linear;
        bool                            CB_has_shader_readable_metadata;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 36dce3815398e2097e093bea061f24fa529489d2..43d76d199161ff051c6770c5063546f3f9b1cf58 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -113,12 +113,13 @@ static void si_emit_cb_render_state(struct si_context *sctx)
                                  blend &&
                                  blend->blend_enable_4bit & cb_target_mask &&
                                  sctx->framebuffer.nr_samples >= 2;
+               unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
 
                radeon_opt_set_context_reg(
                                sctx, R_028424_CB_DCC_CONTROL,
                                SI_TRACKED_CB_DCC_CONTROL,
                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
-                               S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
+                               S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
                                S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
        }
 
@@ -2855,6 +2856,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        sctx->framebuffer.any_dst_linear = false;
        sctx->framebuffer.CB_has_shader_readable_metadata = false;
        sctx->framebuffer.DB_has_shader_readable_metadata = false;
+       unsigned num_bpp64_colorbufs = 0;
 
        for (i = 0; i < state->nr_cbufs; i++) {
                if (!state->cbufs[i])
@@ -2901,6 +2903,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 
                if (tex->surface.is_linear)
                        sctx->framebuffer.any_dst_linear = true;
+               if (tex->surface.bpe >= 8)
+                       num_bpp64_colorbufs++;
 
                if (vi_dcc_enabled(tex, surf->base.u.tex.level))
                        sctx->framebuffer.CB_has_shader_readable_metadata = true;
@@ -2916,6 +2920,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                }
        }
 
+       /* For optimal DCC performance. */
+       if (sctx->chip_class == VI)
+               sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
+       else if (num_bpp64_colorbufs >= 5)
+               sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
+       else
+               sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
+
        struct si_texture *zstex = NULL;
 
        if (state->zsbuf) {