(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 2a47bd46311644d3fbc2a35295c0b3eb480eeb07..788616057f7f7bb824e4ac2bab229fa4cb06bee7 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -116,14 +116,9 @@ Pages being developed and examples
 * [[sv/implementation]] implementation planning and coordination
 * [[sv/svp64]] contains the packet-format *only*, the [[sv/svp64/appendix]]
   contains explanations and further details
-* [[sv/setvl]] the Cray-style "Vector Length" instruction
 * [[sv/svp64_quirks]] things in SVP64  that slightly break the rules
-* [[sv/cr_int_predication]] instructions needed for effective predication
-* [[opcode_regs_deduped]]
-* [[sv/vector_swizzle]]
-* [[sv/vector_ops]]
-* [[sv/mv.swizzle]]
-* [[sv/mv.x]]
+* [[opcode_regs_deduped]] autogenerated table of SVP64 instructions
+* [[sv/sprs]] SPRs
 * SVP64 "Modes":
   - For condition register operations see [[sv/cr_ops]] - SVP64 Condition
     Register ops: Guidelines
@@ -133,16 +128,28 @@ Pages being developed and examples
   - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch
     behaviour: All/Some Vector CRs
   - For arithmetic and logical, see [[sv/normal]]
-* [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
-* [[sv/fclass]] detect class of FP numbers
-* [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
+
+Core SVP64 instructions:
+
+* [[sv/setvl]] the Cray-style "Vector Length" instruction
+* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
+* [[sv/svstep]] Key stepping instruction for Vertical-First Mode
+
+Vector-related:
+
+* [[sv/vector_swizzle]]
+* [[sv/vector_ops]]
 * [[sv/mv.vec]] move to and from vec2/3/4
-* [[sv/sprs]] SPRs
+* [[sv/mv.swizzle]]
+
+Scalar Instructions:
+
+* [[sv/cr_int_predication]] instructions needed for effective predication
 * [[sv/bitmanip]]
 * [[sv/biginteger]] Operations that help with big arithmetic
-* [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing"
-* [[sv/svstep]] Key stepping instruction for Vertical-First Mode
-* [[sv/propagation]] Context propagation including svp64, swizzle and remap
+* [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
+* [[sv/fclass]] detect class of FP numbers
+* [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * Twin targetted instructions (two registers out, one implicit)
@@ -150,10 +157,11 @@ Pages being developed and examples
   (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
   - [[isa/svfixedarith]]
   - [[isa/svfparith]]
-* TODO: OpenPOWER [[openpower/transcendentals]]
+* TODO: OpenPOWER adaptation [[openpower/transcendentals]]
 
-Examples experiments ideas discussion:
+Examples experiments future ideas discussion:
 
+* [[sv/propagation]] Context propagation including svp64, swizzle and remap
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]
 * [[sv/example_dep_matrices]]
@@ -163,6 +171,7 @@ Examples experiments ideas discussion:
 * [[sv/toc_data_pointer]] experimental
 * [[sv/predication]] discussion on predication concepts
 * [[sv/register_type_tags]]
+* [[sv/mv.x]] deprecated in favour of Indexed REMAP
 
 Additional links: