+2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+
+ * or1korbis.cpu (h-atomic-reserve): New hardware.
+ (h-atomic-address): Likewise.
+ (insn-opcode): Add opcodes for LWA and SWA.
+ (atomic-reserve): New operand.
+ (atomic-address): Likewise.
+ (l-lwa, l-swa): New instructions.
+ (l-lbs): Fix typo in comment.
+ (store-insn): Clear atomic reserve on store to atomic-address.
+ Fix register names in fmt field.
+
2014-04-22 Christian Svensson <blue@cmd.nu>
* openrisc.cpu: Delete.
(dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ())
(dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ())
+; Hardware for the (internal) atomic registers
+(dsh h-atomic-reserve "atomic reserve flag" () (register BI))
+(dsh h-atomic-address "atomic reserve address" () (register SI))
+
; Instruction classes.
(dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6)
("JR" #x11)
("JALR" #x12)
("MACI" #x13)
+ ("LWA" #x1b)
("CUST1" #x1c)
("CUST2" #x1d)
("CUST3" #x1e)
("MTSPR" #x30)
("MAC" #x31)
("FLOAT" #x32)
+ ("SWA" #x33)
("SD" #x34)
("SW" #x35)
("SB" #x36)
(dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil)
(dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil)
+(dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil)
+(dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil)
+
(dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6)
(dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1)
()
)
+(dni l-lwa "l.lwa reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lwa $rD,${simm16}($rA)"
+ (+ OPC_LWA rD rA simm16)
+ (sequence ()
+ (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
+ (set atomic-reserve (const 1))
+ (set atomic-address (load-store-addr rA simm16 4))
+ )
+ ()
+)
+
(dni l-lbz "l.lbz reg/simm16(reg)"
((MACH ORBIS-MACHS))
"l.lbz $rD,${simm16}($rA)"
()
)
-(dni l-lbs "l.lbz reg/simm16(reg)"
+(dni l-lbs "l.lbs reg/simm16(reg)"
((MACH ORBIS-MACHS))
"l.lbs $rD,${simm16}($rA)"
(+ OPC_LBS rD rA simm16)
(.str "l." mnemonic " simm16(reg)/reg")
((MACH ORBIS-MACHS))
(.str "l." mnemonic " ${simm16-split}($rA),$rB")
- (+ opc-op rB rD simm16-split)
- (set mode (mem mode (load-store-addr rA simm16-split size)) (trunc mode rB))
+ (+ opc-op rA rB simm16-split)
+ (sequence ((SI addr))
+ (set addr (load-store-addr rA simm16-split size))
+ (set mode (mem mode addr) (trunc mode rB))
+ (if (eq (and addr #xffffffc) atomic-address)
+ (set atomic-reserve (const 0))
+ )
+ )
()
)
)
(store-insn sb OPC_SB UQI 1)
(store-insn sh OPC_SH UHI 2)
+(dni l-swa "l.swa simm16(reg)/reg"
+ ((MACH ORBIS-MACHS))
+ "l.swa ${simm16-split}($rA),$rB"
+ (+ OPC_SWA rA rB simm16)
+ (sequence ((SI addr) (BI flag))
+ (set addr (load-store-addr rA simm16-split 4))
+ (set sys-sr-f (and atomic-reserve (eq addr atomic-address)))
+ (if sys-sr-f
+ (set USI (mem USI addr) (trunc USI rB))
+ )
+ (set atomic-reserve (const 0))
+ )
+ ()
+)
\f
; Shift and rotate instructions
+2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+
+ * or1k-desc.c: Regenerated.
+ * or1k-desc.h: Likewise.
+ * or1k-opc.c: Likewise.
+ * or1k-opc.h: Likewise.
+ * or1k-opinst.c: Likewise.
+
2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
{ "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
{ "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* atomic-reserve: atomic reserve flag */
+ { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* atomic-address: atomic address */
+ { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* uimm6: uimm6 */
{ "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
OR1K_INSN_L_LWS, "l-lws", "l.lws", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* l.lwa $rD,${simm16}($rA) */
+ {
+ OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
/* l.lbz $rD,${simm16}($rA) */
{
OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
OR1K_INSN_L_SH, "l-sh", "l.sh", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* l.swa ${simm16-split}($rA),$rB */
+ {
+ OR1K_INSN_L_SWA, "l-swa", "l.swa", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+ },
/* l.sll $rD,$rA,$rB */
{
OR1K_INSN_L_SLL, "l-sll", "l.sll", 32,
OPC_J = 0, OPC_JAL = 1, OPC_BNF = 3, OPC_BF = 4
, OPC_NOP = 5, OPC_MOVHIMACRC = 6, OPC_SYSTRAPSYNCS = 8, OPC_RFE = 9
, OPC_VECTOR = 10, OPC_JR = 17, OPC_JALR = 18, OPC_MACI = 19
- , OPC_CUST1 = 28, OPC_CUST2 = 29, OPC_CUST3 = 30, OPC_CUST4 = 31
- , OPC_LD = 32, OPC_LWZ = 33, OPC_LWS = 34, OPC_LBZ = 35
- , OPC_LBS = 36, OPC_LHZ = 37, OPC_LHS = 38, OPC_ADDI = 39
- , OPC_ADDIC = 40, OPC_ANDI = 41, OPC_ORI = 42, OPC_XORI = 43
- , OPC_MULI = 44, OPC_MFSPR = 45, OPC_SHROTI = 46, OPC_SFI = 47
- , OPC_MTSPR = 48, OPC_MAC = 49, OPC_FLOAT = 50, OPC_SD = 52
- , OPC_SW = 53, OPC_SB = 54, OPC_SH = 55, OPC_ALU = 56
- , OPC_SF = 57, OPC_CUST5 = 60, OPC_CUST6 = 61, OPC_CUST7 = 62
- , OPC_CUST8 = 63
+ , OPC_LWA = 27, OPC_CUST1 = 28, OPC_CUST2 = 29, OPC_CUST3 = 30
+ , OPC_CUST4 = 31, OPC_LD = 32, OPC_LWZ = 33, OPC_LWS = 34
+ , OPC_LBZ = 35, OPC_LBS = 36, OPC_LHZ = 37, OPC_LHS = 38
+ , OPC_ADDI = 39, OPC_ADDIC = 40, OPC_ANDI = 41, OPC_ORI = 42
+ , OPC_XORI = 43, OPC_MULI = 44, OPC_MFSPR = 45, OPC_SHROTI = 46
+ , OPC_SFI = 47, OPC_MTSPR = 48, OPC_MAC = 49, OPC_FLOAT = 50
+ , OPC_SWA = 51, OPC_SD = 52, OPC_SW = 53, OPC_SB = 54
+ , OPC_SH = 55, OPC_ALU = 56, OPC_SF = 57, OPC_CUST5 = 60
+ , OPC_CUST6 = 61, OPC_CUST7 = 62, OPC_CUST8 = 63
} INSN_OPCODE;
/* Enum declaration for systrapsync insn opcode enums. */
, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF
, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF
, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16, HW_H_UIMM16
- , HW_H_UIMM6, HW_MAX
+ , HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
OR1K_OPERAND_PC, OR1K_OPERAND_SYS_SR, OR1K_OPERAND_SYS_ESR0, OR1K_OPERAND_SYS_EPCR0
, OR1K_OPERAND_SYS_SR_LEE, OR1K_OPERAND_SYS_SR_F, OR1K_OPERAND_SYS_SR_CY, OR1K_OPERAND_SYS_SR_OV
, OR1K_OPERAND_SYS_SR_OVE, OR1K_OPERAND_SYS_CPUCFGR_OB64S, OR1K_OPERAND_SYS_CPUCFGR_ND, OR1K_OPERAND_SYS_FPCSR_RM
- , OR1K_OPERAND_MAC_MACHI, OR1K_OPERAND_MAC_MACLO, OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD
- , OR1K_OPERAND_RA, OR1K_OPERAND_RB, OR1K_OPERAND_DISP26, OR1K_OPERAND_SIMM16
- , OR1K_OPERAND_UIMM16, OR1K_OPERAND_SIMM16_SPLIT, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF
- , OR1K_OPERAND_RASF, OR1K_OPERAND_RBSF, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF
- , OR1K_OPERAND_RBDF, OR1K_OPERAND_MAX
+ , OR1K_OPERAND_MAC_MACHI, OR1K_OPERAND_MAC_MACLO, OR1K_OPERAND_ATOMIC_RESERVE, OR1K_OPERAND_ATOMIC_ADDRESS
+ , OR1K_OPERAND_UIMM6, OR1K_OPERAND_RD, OR1K_OPERAND_RA, OR1K_OPERAND_RB
+ , OR1K_OPERAND_DISP26, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16, OR1K_OPERAND_SIMM16_SPLIT
+ , OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF, OR1K_OPERAND_RBSF
+ , OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF, OR1K_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 29
+#define MAX_OPERANDS 31
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 9
};
static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R3) }, { F (F_SIMM16_SPLIT) }, { 0 } }
+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16_SPLIT) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_l_swa ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R2) }, { F (F_R3) }, { F (F_SIMM16) }, { 0 } }
};
static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = {
{ { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
& ifmt_l_lwz, { 0x88000000 }
},
+/* l.lwa $rD,${simm16}($rA) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
+ & ifmt_l_lwz, { 0x6c000000 }
+ },
/* l.lbz $rD,${simm16}($rA) */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
& ifmt_l_sw, { 0xdc000000 }
},
+/* l.swa ${simm16-split}($rA),$rB */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
+ & ifmt_l_swa, { 0xcc000000 }
+ },
/* l.sll $rD,$rA,$rB */
{
{ 0, 0, 0, 0 },
, OR1K_INSN_L_JALR, OR1K_INSN_L_BNF, OR1K_INSN_L_BF, OR1K_INSN_L_TRAP
, OR1K_INSN_L_SYS, OR1K_INSN_L_RFE, OR1K_INSN_L_NOP_IMM, OR1K_INSN_L_NOP
, OR1K_INSN_L_MOVHI, OR1K_INSN_L_MACRC, OR1K_INSN_L_MFSPR, OR1K_INSN_L_MTSPR
- , OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LBZ, OR1K_INSN_L_LBS
- , OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW, OR1K_INSN_L_SB
- , OR1K_INSN_L_SH, OR1K_INSN_L_SLL, OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL
- , OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA, OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR
- , OR1K_INSN_L_RORI, OR1K_INSN_L_AND, OR1K_INSN_L_OR, OR1K_INSN_L_XOR
- , OR1K_INSN_L_ADD, OR1K_INSN_L_SUB, OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL
- , OR1K_INSN_L_MULU, OR1K_INSN_L_DIV, OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1
- , OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI, OR1K_INSN_L_ORI, OR1K_INSN_L_XORI
- , OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC, OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS
- , OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ, OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS
- , OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV, OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGTSI
- , OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGTUI, OR1K_INSN_L_SFGES, OR1K_INSN_L_SFGESI
- , OR1K_INSN_L_SFGEU, OR1K_INSN_L_SFGEUI, OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLTSI
- , OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLTUI, OR1K_INSN_L_SFLES, OR1K_INSN_L_SFLESI
- , OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFLEUI, OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI
- , OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI, OR1K_INSN_L_MAC, OR1K_INSN_L_MSB
- , OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3
- , OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7
- , OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S, OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S
- , OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S
- , OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S, OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S
- , OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S
- , OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S, OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S
- , OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S, OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S
- , OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S, OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S
- , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D
+ , OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LWA, OR1K_INSN_L_LBZ
+ , OR1K_INSN_L_LBS, OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW
+ , OR1K_INSN_L_SB, OR1K_INSN_L_SH, OR1K_INSN_L_SWA, OR1K_INSN_L_SLL
+ , OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL, OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA
+ , OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR, OR1K_INSN_L_RORI, OR1K_INSN_L_AND
+ , OR1K_INSN_L_OR, OR1K_INSN_L_XOR, OR1K_INSN_L_ADD, OR1K_INSN_L_SUB
+ , OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL, OR1K_INSN_L_MULU, OR1K_INSN_L_DIV
+ , OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1, OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI
+ , OR1K_INSN_L_ORI, OR1K_INSN_L_XORI, OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC
+ , OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS, OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ
+ , OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS, OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV
+ , OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGTSI, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGTUI
+ , OR1K_INSN_L_SFGES, OR1K_INSN_L_SFGESI, OR1K_INSN_L_SFGEU, OR1K_INSN_L_SFGEUI
+ , OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLTSI, OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLTUI
+ , OR1K_INSN_L_SFLES, OR1K_INSN_L_SFLESI, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFLEUI
+ , OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI, OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI
+ , OR1K_INSN_L_MAC, OR1K_INSN_L_MSB, OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1
+ , OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5
+ , OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S
+ , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S
+ , OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S
+ , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S
+ , OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S
+ , OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S
+ , OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S
+ , OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S
+ , OR1K_INSN_LF_CUST1_D
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
+ { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
+ { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
};
static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
- { OUTPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
+ { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
- { OUTPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
+ { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
- { OUTPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_split_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
+ { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
+ { INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
+ { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
+ { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
+ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
+ { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF },
+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
& sfmt_l_mtspr_ops[0],
& sfmt_l_lwz_ops[0],
& sfmt_l_lws_ops[0],
+ & sfmt_l_lwa_ops[0],
& sfmt_l_lbz_ops[0],
& sfmt_l_lbs_ops[0],
& sfmt_l_lhz_ops[0],
& sfmt_l_sw_ops[0],
& sfmt_l_sb_ops[0],
& sfmt_l_sh_ops[0],
+ & sfmt_l_swa_ops[0],
& sfmt_l_sll_ops[0],
& sfmt_l_slli_ops[0],
& sfmt_l_sll_ops[0],
projects / binutils-gdb.git / commitdiff