clean up

diff --git a/examples/de0_nano/client/test_mila.py b/examples/de0_nano/client/test_mila.py
index 2b90492559e9b27c41baef4844b08e73aa7f6bfa..4887851bb251d89c89e16e8ff440dde7ada66155 100644 (file)
--- a/examples/de0_nano/client/test_mila.py
+++ b/examples/de0_nano/client/test_mila.py
@@ -31,8 +31,6 @@ mila = mila.MiLa(MILA_ADDR, trigger, recorder, csr)
 dat_vcd = VcdDat(dat_w)
 
 def capture(size):
-       global trigger
-       global recorder
        global dat_vcd
        sum_tt = gen_truth_table("term")
        mila.trigger.sum.set(sum_tt)

diff --git a/miscope/bridges/spi2csr/__init__.py b/miscope/bridges/spi2csr/__init__.py
index d396fa6873f69e8d3175e73594971b3dad4346c8..2416cb6c114d2ec9b30182340a02272c470917f8 100644 (file)
--- a/miscope/bridges/spi2csr/__init__.py
+++ b/miscope/bridges/spi2csr/__init__.py
@@ -4,13 +4,13 @@ from migen.genlib.cdc import *
 from migen.bus import csr
 
 class Spi2Csr(Module):
-       def __init__(self, a_w, d_w, burst_length=8):
-               self.a_w = a_w
-               self.d_w = d_w
+       def __init__(self, burst_length=8):
+               self.a_w = 14
+               self.d_w = 8
                self.burst_length = 8
                
                # Csr interface
-               self.csr = csr.Interface(self.a_w, self.d_w)
+               self.csr = csr.Interface()
                
                # Spi interface
                self.spi_clk = Signal()

diff --git a/miscope/bridges/uart2csr/__init__.py b/miscope/bridges/uart2csr/__init__.py
index 9cf0a8b4e0893f7b2bcb7254b65cf737ca2911a5..a9c20fa61bae934ed678a2e19ec3cecd837b964e 100644 (file)
--- a/miscope/bridges/uart2csr/__init__.py
+++ b/miscope/bridges/uart2csr/__init__.py
@@ -16,7 +16,7 @@ class Uart2Csr(Module):
                self.tx = Signal()
                
                # Csr interface
-               self.csr = csr.Interface(32, 8)
+               self.csr = csr.Interface()
                
        ###