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add images to wiki for ulx3s jtag stlinkv2 wires
authorCole Poirier <colepoirier@gmail.com>
Sun, 1 Nov 2020 22:17:06 +0000 (14:17 -0800)
committerCole Poirier <colepoirier@gmail.com>
Sun, 1 Nov 2020 22:17:06 +0000 (14:17 -0800)
HDL_workflow/jtag_wires_ulx3s_fpga.jpg [new file with mode: 0644] patch | blob
HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg [new file with mode: 0644] patch | blob

diff --git a/HDL_workflow/jtag_wires_ulx3s_fpga.jpg b/HDL_workflow/jtag_wires_ulx3s_fpga.jpg
new file mode 100644 (file)
index 0000000..155c076
Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_fpga.jpg differ
diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg
new file mode 100644 (file)
index 0000000..d56adc8
Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg differ
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