arm: Fix the failing mve scalar shift execution tests.

In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings
because of executing them on target hardware which doesn't support MVE instructions. This patch
restricts those tests to execute only on target hardware that support MVE instructions.

2020-06-22  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	* doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item.
	(arm_mve_hw): Likewise.

gcc/testsuite/
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: Modify.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.
	* lib/target-supports.exp (check_effective_target_arm_mve_hw): Define.

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index e5554c4666eb217844598352ced5a9597652f07c..a12af822443ad41afba816ed640d80d182859239 100644 (file)
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1925,6 +1925,15 @@ ARM target supports options to generate instructions from ARMv8.1-M with
 the M-Profile Vector Extension (MVE). Some multilibs may be incompatible
 with these options.
 
+@item arm_v8_1m_mve_fp_ok
+ARM target supports options to generate instructions from ARMv8.1-M with
+the Half-precision floating-point instructions (HP), Floating-point Extension
+(FP) along with M-Profile Vector Extension (MVE). Some multilibs may be
+incompatible with these options.
+
+@item arm_mve_hw
+Test system supports executing MVE instructions.
+
 @item arm_v8m_main_cde
 ARM target supports options to generate instructions from ARMv8-M with
 the Custom Datapath Extension (CDE). Some multilibs may be incompatible

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
index e1c136e7f302c1824f0b00b5e7bc468ff5fcfe27..db2335fc76ed3204fcfc033ef6777dc85dbd465f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
index 0b5a8edb15849913d4f2849ab86decb286692386..5a63d385cb7e7d18345974421035f3090f409554 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
index 7e3da54f5e62467e2cdaabd85df3db127f608802..f0d5ee32f829c482cbeb4f1fb1f714e01b43da87 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
index 8bee12f7fdfaef51daf7e2f5d3c1e284115d2649..283742fcf982b6cf2746e7745a3c5258e75d3982 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 862a0735b49582f7f35a9a4009f5752cf8f7e3ba..ab0ee32fc911622b4716c272df4e656698b81a70 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4671,6 +4671,24 @@ proc check_effective_target_arm_cmse_ok {} {
     } "-mcmse"];
 }
 
+# Return 1 if the target supports executing MVE instructions, 0
+# otherwise.
+
+proc check_effective_target_arm_mve_hw {} {
+    return [check_runtime arm_mve_hw_available {
+       int
+       main (void)
+       {
+         long long a = 16;
+         int b = 3;
+         asm ("sqrshrl %Q1, %R1, #64, %2"
+              : "=l" (a)
+              : "0" (a), "r" (b));
+         return (a != 2);
+       }
+    } ""]
+}
+
 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.