return Fragment(
[
asfifo.ins["read_en"].eq(1),
+ Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
self.busy.eq(0),
asfifo.ins["rst"].eq(0)
- ], [
- Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
],
instances=[asfifo])
parameter fifo_depth = (1 << address_width)
) (
/* Read port */
- output [data_width-1:0] data_out,
+ output reg [data_width-1:0] data_out,
output reg empty,
input read_en,
input clk_read,
reg status;
wire preset_full, preset_empty;
-assign data_out = mem[read_index];
+reg [data_width-1:0] data_out0;
+
+always @(posedge clk_read) begin
+ data_out0 <= mem[read_index];
+ data_out <= data_out0;
+end
always @(posedge clk_write) begin
if(write_en & !full)