framebuffer: fix FIFO read clocking
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 7 Jul 2012 09:30:27 +0000 (11:30 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 7 Jul 2012 09:30:27 +0000 (11:30 +0200)
milkymist/framebuffer/__init__.py
verilog/generic/asfifo.v

index 0431d648301a43e72d55f4d96d0b6558b5824b5f..f38eadbc0f1f65e38149965f1bb8bdd7f99652b5 100644 (file)
@@ -189,6 +189,7 @@ class FIFO(Actor):
                return Fragment(
                        [
                                asfifo.ins["read_en"].eq(1),
+                               Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
                                
                                self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
                                asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
@@ -196,8 +197,6 @@ class FIFO(Actor):
                                
                                self.busy.eq(0),
                                asfifo.ins["rst"].eq(0)
-                       ], [
-                               Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
                        ],
                        instances=[asfifo])
 
index 1618964b002e31be1627224dc2d8d176fc39f167..0cb1c203b8cbf1df43677d471cc629264a3b61c4 100644 (file)
@@ -10,7 +10,7 @@ module asfifo #(
        parameter fifo_depth = (1 << address_width)
 ) (
        /* Read port */
-       output [data_width-1:0] data_out,
+       output reg [data_width-1:0] data_out,
        output reg empty,
        input read_en,
        input clk_read,
@@ -33,7 +33,12 @@ wire set_status, clear_status;
 reg status;
 wire preset_full, preset_empty;
 
-assign data_out = mem[read_index];
+reg [data_width-1:0] data_out0;
+
+always @(posedge clk_read) begin
+       data_out0 <= mem[read_index];
+       data_out <= data_out0;
+end
 
 always @(posedge clk_write) begin
        if(write_en & !full)