sysv4.h (ASM_OUTPUT_REG_PUSH): Remove 64-bit support.

	* config/rs6000/sysv4.h (ASM_OUTPUT_REG_PUSH): Remove 64-bit support.
	(ASM_OUTPUT_REG_POP): Likewise.

From-SVN: r55545

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 044eda69809948a2f8c9799f6ed75d8a0de63fa1..d18e92c087c9d29df84bc04b91356c071dc9f870 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-07-18  Alan Modra  <amodra@bigpond.net.au>
+
+       * config/rs6000/sysv4.h (ASM_OUTPUT_REG_PUSH): Remove 64-bit support.
+       (ASM_OUTPUT_REG_POP): Likewise.
+
 2002-07-18  Alan Modra  <amodra@bigpond.net.au>
 
        * config/rs6000/rs6000.c (first_reg_to_save): Remove bogus

diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 7ec055c940aaa16131ba88c680392135ffa686d9..be0236ae6654910f9aeef8355ae29480286c2414 100644 (file)
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -747,9 +747,7 @@ do {                                                                        \
 do {                                                                   \
   if (DEFAULT_ABI == ABI_V4)                                           \
     asm_fprintf (FILE,                                                 \
-                (TARGET_32BIT                                          \
-                 ? "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n"   \
-                 : "\tstdu %s,-32(%s)\n\tstd %s,24(%s)\n"),            \
+                "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n",     \
                 reg_names[1], reg_names[1], reg_names[REGNO],          \
                 reg_names[1]);                                         \
 } while (0)
@@ -761,9 +759,7 @@ do {                                                                        \
 do {                                                                   \
   if (DEFAULT_ABI == ABI_V4)                                           \
     asm_fprintf (FILE,                                                 \
-                (TARGET_32BIT                                          \
-                 ? "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n"      \
-                 : "\tld %s,24(%s)\n\t{ai|addic} %s,%s,32\n"),         \
+                "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n",        \
                 reg_names[REGNO], reg_names[1], reg_names[1],          \
                 reg_names[1]);                                         \
 } while (0)