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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 5ae53b4a54687d104cd4e794bd7d1b7b20def111..11ed17be9b6f02a589694d3f92adec79e49d73f8 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -77,9 +77,9 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 |sz |SNZ| 0 RG  |   0 | dz  /   | normal mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
-|sz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-|sz |SNZ| 0 RG  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
-|sz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
+|zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+|zz |SNZ| 0 RG  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
+|zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |
 
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