* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.

	* cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index ef3c996364e63fa59591c438f7ba1b40ed3eef00..cea93d7e658c67752152ddcaa73aedf2a6d248d0 100644 (file)
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,16 @@
+Fri Dec  4 00:19:33 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+       * cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+start-sanitize-m32rx
+       * cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
+end-sanitize-m32rx
+
+1998-11-22  Doug Evans  <devans@tobor.to.cygnus.com>
+
+       * devices.c (device_io_write_buffer): Fix typo.
+       * sim-if.c (sim_open): Hack in call to dv_sockser_install.
+       * tconfig.in (HAVE_DV_SOCKSER): Add but comment out.
+
 1998-11-18  Doug Evans  <devans@casey.cygnus.com>
 
        * Makefile.in (M32R_OBJS): Delete extract.o.

diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index 8636b4080b7616f898af056dbc7b9fe59183672e..563deca232c0e1fbde2d9d4484f334c920d28bab 100644 (file)
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -126,179 +126,179 @@ struct argbuf {
   int written;
   union {
     struct { /* e.g. add $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_add;
     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_add3;
     struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       USI f_uimm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_and3;
     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       UHI f_uimm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_or3;
     struct { /* e.g. addi $dr,$simm8 */
-      SI * f_r1;
+      SI * i_dr;
       SI f_simm8;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_addi;
     struct { /* e.g. addv $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addv;
     struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       SI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addv3;
     struct { /* e.g. addx $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addx;
     struct { /* e.g. cmp $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_cmp;
     struct { /* e.g. cmpi $src2,$simm16 */
-      SI * f_r2;
+      SI * i_src2;
       SI f_simm16;
       unsigned char in_src2;
     } fmt_cmpi;
     struct { /* e.g. div $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_div;
     struct { /* e.g. ld $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ld;
     struct { /* e.g. ld $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ld_d;
     struct { /* e.g. ldb $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldb;
     struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldb_d;
     struct { /* e.g. ldh $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldh;
     struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldh_d;
     struct { /* e.g. ld $dr,@$sr+ */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
       unsigned char out_sr;
     } fmt_ld_plus;
     struct { /* e.g. ld24 $dr,$uimm24 */
-      SI * f_r1;
       ADDR f_uimm24;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ld24;
     struct { /* e.g. ldi8 $dr,$simm8 */
-      SI * f_r1;
       SI f_simm8;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ldi8;
     struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      SI * f_r1;
       HI f_simm16;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ldi16;
     struct { /* e.g. lock $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_lock;
     struct { /* e.g. machi $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_machi;
     struct { /* e.g. mulhi $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_mulhi;
     struct { /* e.g. mv $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_mv;
     struct { /* e.g. mvfachi $dr */
-      SI * f_r1;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_mvfachi;
     struct { /* e.g. mvfc $dr,$scr */
-      SI * f_r1;
       UINT f_r2;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_mvfc;
     struct { /* e.g. mvtachi $src1 */
-      SI * f_r1;
+      SI * i_src1;
       unsigned char in_src1;
     } fmt_mvtachi;
     struct { /* e.g. mvtc $sr,$dcr */
+      SI * i_sr;
       UINT f_r1;
-      SI * f_r2;
       unsigned char in_sr;
     } fmt_mvtc;
     struct { /* e.g. nop */
@@ -308,72 +308,72 @@ struct argbuf {
       int empty;
     } fmt_rac;
     struct { /* e.g. seth $dr,$hash$hi16 */
-      SI * f_r1;
       UHI f_hi16;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_seth;
     struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       SI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_sll3;
     struct { /* e.g. slli $dr,$uimm5 */
-      SI * f_r1;
+      SI * i_dr;
       USI f_uimm5;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_slli;
     struct { /* e.g. st $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
       unsigned char out_src2;
     } fmt_st_plus;
     struct { /* e.g. unlock $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_unlock;
@@ -387,14 +387,14 @@ struct argbuf {
       IADDR f_disp24;
     } fmt_bc24;
     struct { /* e.g. beq $src1,$src2,$disp16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       IADDR f_disp16;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_beq;
     struct { /* e.g. beqz $src2,$disp16 */
-      SI * f_r2;
+      SI * i_src2;
       IADDR f_disp16;
       unsigned char in_src2;
     } fmt_beqz;
@@ -413,12 +413,12 @@ struct argbuf {
       IADDR f_disp24;
     } fmt_bra24;
     struct { /* e.g. jl $sr */
-      SI * f_r2;
+      SI * i_sr;
       unsigned char in_sr;
       unsigned char out_h_gr_14;
     } fmt_jl;
     struct { /* e.g. jmp $sr */
-      SI * f_r2;
+      SI * i_sr;
       unsigned char in_sr;
     } fmt_jmp;
     struct { /* e.g. rte */
@@ -480,10 +480,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ADD3_VARS \
   /* Instruction fields.  */ \
@@ -491,15 +491,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ADD3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_AND3_VARS \
   /* Instruction fields.  */ \
@@ -511,11 +511,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_AND3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_OR3_VARS \
   /* Instruction fields.  */ \
@@ -527,23 +527,23 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_OR3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ADDI_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_simm8; \
+  INT f_simm8; \
   unsigned int length;
 #define EXTRACT_FMT_ADDI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 
 #define EXTRACT_FMT_ADDV_VARS \
   /* Instruction fields.  */ \
@@ -554,10 +554,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADDV_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ADDV3_VARS \
   /* Instruction fields.  */ \
@@ -565,15 +565,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ADDV3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ADDX_VARS \
   /* Instruction fields.  */ \
@@ -584,34 +584,34 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADDX_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_BC8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BC8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BC24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BC24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BEQ_VARS \
   /* Instruction fields.  */ \
@@ -619,15 +619,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_disp16; \
+  INT f_disp16; \
   unsigned int length;
 #define EXTRACT_FMT_BEQ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BEQZ_VARS \
   /* Instruction fields.  */ \
@@ -635,63 +635,63 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_disp16; \
+  INT f_disp16; \
   unsigned int length;
 #define EXTRACT_FMT_BEQZ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BL8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BL8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BL24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BL24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BRA8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BRA8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BRA24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BRA24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_CMP_VARS \
   /* Instruction fields.  */ \
@@ -702,10 +702,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_CMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_CMPI_VARS \
   /* Instruction fields.  */ \
@@ -713,15 +713,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_CMPI_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_DIV_VARS \
   /* Instruction fields.  */ \
@@ -729,15 +729,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_DIV_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_JL_VARS \
   /* Instruction fields.  */ \
@@ -748,10 +748,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_JL_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_JMP_VARS \
   /* Instruction fields.  */ \
@@ -762,10 +762,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_JMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD_VARS \
   /* Instruction fields.  */ \
@@ -776,10 +776,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD_D_VARS \
   /* Instruction fields.  */ \
@@ -787,15 +787,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LD_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LDB_VARS \
   /* Instruction fields.  */ \
@@ -806,10 +806,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LDB_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LDB_D_VARS \
   /* Instruction fields.  */ \
@@ -817,15 +817,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDB_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LDH_VARS \
   /* Instruction fields.  */ \
@@ -836,10 +836,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LDH_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LDH_D_VARS \
   /* Instruction fields.  */ \
@@ -847,15 +847,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDH_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LD_PLUS_VARS \
   /* Instruction fields.  */ \
@@ -866,10 +866,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD_PLUS_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD24_VARS \
   /* Instruction fields.  */ \
@@ -879,21 +879,21 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 
 #define EXTRACT_FMT_LDI8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_simm8; \
+  INT f_simm8; \
   unsigned int length;
 #define EXTRACT_FMT_LDI8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 
 #define EXTRACT_FMT_LDI16_VARS \
   /* Instruction fields.  */ \
@@ -901,15 +901,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDI16_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LOCK_VARS \
   /* Instruction fields.  */ \
@@ -920,10 +920,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LOCK_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MACHI_VARS \
   /* Instruction fields.  */ \
@@ -934,10 +934,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MACHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MULHI_VARS \
   /* Instruction fields.  */ \
@@ -948,10 +948,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MULHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MV_VARS \
   /* Instruction fields.  */ \
@@ -962,10 +962,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MV_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVFACHI_VARS \
   /* Instruction fields.  */ \
@@ -976,10 +976,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVFACHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVFC_VARS \
   /* Instruction fields.  */ \
@@ -990,10 +990,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVFC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVTACHI_VARS \
   /* Instruction fields.  */ \
@@ -1004,10 +1004,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVTACHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVTC_VARS \
   /* Instruction fields.  */ \
@@ -1018,10 +1018,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVTC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_NOP_VARS \
   /* Instruction fields.  */ \
@@ -1032,10 +1032,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_NOP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_RAC_VARS \
   /* Instruction fields.  */ \
@@ -1046,10 +1046,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_RAC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_RTE_VARS \
   /* Instruction fields.  */ \
@@ -1060,10 +1060,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_RTE_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_SETH_VARS \
   /* Instruction fields.  */ \
@@ -1075,11 +1075,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SETH_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SLL3_VARS \
   /* Instruction fields.  */ \
@@ -1087,15 +1087,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_SLL3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SLLI_VARS \
   /* Instruction fields.  */ \
@@ -1106,10 +1106,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SLLI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 
 #define EXTRACT_FMT_ST_VARS \
   /* Instruction fields.  */ \
@@ -1120,10 +1120,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ST_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ST_D_VARS \
   /* Instruction fields.  */ \
@@ -1131,15 +1131,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ST_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_STB_VARS \
   /* Instruction fields.  */ \
@@ -1150,10 +1150,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_STB_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_STB_D_VARS \
   /* Instruction fields.  */ \
@@ -1161,15 +1161,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_STB_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_STH_VARS \
   /* Instruction fields.  */ \
@@ -1180,10 +1180,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_STH_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_STH_D_VARS \
   /* Instruction fields.  */ \
@@ -1191,15 +1191,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_STH_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ST_PLUS_VARS \
   /* Instruction fields.  */ \
@@ -1210,10 +1210,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ST_PLUS_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_TRAP_VARS \
   /* Instruction fields.  */ \
@@ -1224,10 +1224,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_TRAP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_UNLOCK_VARS \
   /* Instruction fields.  */ \
@@ -1238,9 +1238,16 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_UNLOCK_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  PCADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
 
 #endif /* CPU_M32RBF_H */

diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index fb1ac9c0f96c0e347bbe42bb63a62a6e7f0b31e0..c3dcf6f2ef08af407b515a145b7928b3b58486bb 100644 (file)
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -122,276 +122,276 @@ struct argbuf {
   int written;
   union {
     struct { /* e.g. add $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_add;
     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_add3;
     struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       USI f_uimm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_and3;
     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       UHI f_uimm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_or3;
     struct { /* e.g. addi $dr,$simm8 */
-      SI * f_r1;
+      SI * i_dr;
       SI f_simm8;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_addi;
     struct { /* e.g. addv $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addv;
     struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       SI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addv3;
     struct { /* e.g. addx $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_dr;
+      SI * i_sr;
       unsigned char in_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_addx;
     struct { /* e.g. cmp $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_cmp;
     struct { /* e.g. cmpi $src2,$simm16 */
-      SI * f_r2;
+      SI * i_src2;
       SI f_simm16;
       unsigned char in_src2;
     } fmt_cmpi;
     struct { /* e.g. cmpz $src2 */
-      SI * f_r2;
+      SI * i_src2;
       unsigned char in_src2;
     } fmt_cmpz;
     struct { /* e.g. div $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_div;
     struct { /* e.g. ld $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ld;
     struct { /* e.g. ld $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ld_d;
     struct { /* e.g. ldb $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldb;
     struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldb_d;
     struct { /* e.g. ldh $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldh;
     struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       HI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_ldh_d;
     struct { /* e.g. ld $dr,@$sr+ */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
       unsigned char out_sr;
     } fmt_ld_plus;
     struct { /* e.g. ld24 $dr,$uimm24 */
-      SI * f_r1;
       ADDR f_uimm24;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ld24;
     struct { /* e.g. ldi8 $dr,$simm8 */
-      SI * f_r1;
       SI f_simm8;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ldi8;
     struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      SI * f_r1;
       HI f_simm16;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_ldi16;
     struct { /* e.g. lock $dr,@$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_lock;
     struct { /* e.g. machi $src1,$src2,$acc */
-      SI * f_r1;
       UINT f_acc;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
-      SI * f_r1;
+      SI * i_src1;
+      SI * i_src2;
       UINT f_acc;
-      SI * f_r2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_mv;
     struct { /* e.g. mvfachi $dr,$accs */
-      SI * f_r1;
       UINT f_accs;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
-      SI * f_r1;
       UINT f_r2;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
-      SI * f_r1;
       UINT f_accs;
+      SI * i_src1;
       unsigned char in_src1;
     } fmt_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
+      SI * i_sr;
       UINT f_r1;
-      SI * f_r2;
       unsigned char in_sr;
     } fmt_mvtc;
     struct { /* e.g. nop */
       int empty;
     } fmt_nop;
     struct { /* e.g. rac $accd,$accs,$imm1 */
-      UINT f_accd;
       UINT f_accs;
       USI f_imm1;
+      UINT f_accd;
     } fmt_rac_dsi;
     struct { /* e.g. seth $dr,$hash$hi16 */
-      SI * f_r1;
       UHI f_hi16;
+      SI * i_dr;
       unsigned char out_dr;
     } fmt_seth;
     struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
       SI f_simm16;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_sll3;
     struct { /* e.g. slli $dr,$uimm5 */
-      SI * f_r1;
+      SI * i_dr;
       USI f_uimm5;
       unsigned char in_dr;
       unsigned char out_dr;
     } fmt_slli;
     struct { /* e.g. st $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
       HI f_simm16;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
       unsigned char out_src2;
     } fmt_st_plus;
     struct { /* e.g. unlock $src1,@$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src2;
+      SI * i_src1;
       unsigned char in_src2;
       unsigned char in_src1;
     } fmt_unlock;
     struct { /* e.g. satb $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_satb;
     struct { /* e.g. sat $dr,$sr */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_sr;
+      SI * i_dr;
       unsigned char in_sr;
       unsigned char out_dr;
     } fmt_sat;
@@ -399,26 +399,23 @@ struct argbuf {
       int empty;
     } fmt_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_macwu1;
     struct { /* e.g. msblo $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_msblo;
     struct { /* e.g. mulwu1 $src1,$src2 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_mulwu1;
-    struct { /* e.g. sc */
-      int empty;
-    } fmt_sc;
   /* cti insns, kept separately so addr_cache is in fixed place */
   struct {
     union {
@@ -429,14 +426,14 @@ struct argbuf {
       IADDR f_disp24;
     } fmt_bc24;
     struct { /* e.g. beq $src1,$src2,$disp16 */
-      SI * f_r1;
-      SI * f_r2;
+      SI * i_src1;
+      SI * i_src2;
       IADDR f_disp16;
       unsigned char in_src1;
       unsigned char in_src2;
     } fmt_beq;
     struct { /* e.g. beqz $src2,$disp16 */
-      SI * f_r2;
+      SI * i_src2;
       IADDR f_disp16;
       unsigned char in_src2;
     } fmt_beqz;
@@ -463,16 +460,16 @@ struct argbuf {
       IADDR f_disp24;
     } fmt_bra24;
     struct { /* e.g. jc $sr */
-      SI * f_r2;
+      SI * i_sr;
       unsigned char in_sr;
     } fmt_jc;
     struct { /* e.g. jl $sr */
-      SI * f_r2;
+      SI * i_sr;
       unsigned char in_sr;
       unsigned char out_h_gr_14;
     } fmt_jl;
     struct { /* e.g. jmp $sr */
-      SI * f_r2;
+      SI * i_sr;
       unsigned char in_sr;
     } fmt_jmp;
     struct { /* e.g. rte */
@@ -481,6 +478,9 @@ struct argbuf {
     struct { /* e.g. trap $uimm4 */
       USI f_uimm4;
     } fmt_trap;
+    struct { /* e.g. sc */
+      int empty;
+    } fmt_sc;
     } fields;
 #if WITH_SCACHE_PBB_M32RXF
     SEM_PC addr_cache;
@@ -534,10 +534,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ADD3_VARS \
   /* Instruction fields.  */ \
@@ -545,15 +545,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ADD3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_AND3_VARS \
   /* Instruction fields.  */ \
@@ -565,11 +565,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_AND3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_OR3_VARS \
   /* Instruction fields.  */ \
@@ -581,23 +581,23 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_OR3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ADDI_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_simm8; \
+  INT f_simm8; \
   unsigned int length;
 #define EXTRACT_FMT_ADDI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 
 #define EXTRACT_FMT_ADDV_VARS \
   /* Instruction fields.  */ \
@@ -608,10 +608,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADDV_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ADDV3_VARS \
   /* Instruction fields.  */ \
@@ -619,15 +619,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ADDV3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ADDX_VARS \
   /* Instruction fields.  */ \
@@ -638,34 +638,34 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ADDX_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_BC8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BC8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BC24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BC24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BEQ_VARS \
   /* Instruction fields.  */ \
@@ -673,15 +673,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_disp16; \
+  INT f_disp16; \
   unsigned int length;
 #define EXTRACT_FMT_BEQ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BEQZ_VARS \
   /* Instruction fields.  */ \
@@ -689,87 +689,87 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_disp16; \
+  INT f_disp16; \
   unsigned int length;
 #define EXTRACT_FMT_BEQZ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BL8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BL8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BL24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BL24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BCL8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BCL8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BCL24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BCL24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_BRA8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp8; \
+  INT f_disp8; \
   unsigned int length;
 #define EXTRACT_FMT_BRA8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_FMT_BRA24_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_disp24; \
+  INT f_disp24; \
   unsigned int length;
 #define EXTRACT_FMT_BRA24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_FMT_CMP_VARS \
   /* Instruction fields.  */ \
@@ -780,10 +780,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_CMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_CMPI_VARS \
   /* Instruction fields.  */ \
@@ -791,15 +791,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_CMPI_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_CMPZ_VARS \
   /* Instruction fields.  */ \
@@ -810,10 +810,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_CMPZ_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_DIV_VARS \
   /* Instruction fields.  */ \
@@ -821,15 +821,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_DIV_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_JC_VARS \
   /* Instruction fields.  */ \
@@ -840,10 +840,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_JC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_JL_VARS \
   /* Instruction fields.  */ \
@@ -854,10 +854,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_JL_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_JMP_VARS \
   /* Instruction fields.  */ \
@@ -868,10 +868,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_JMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD_VARS \
   /* Instruction fields.  */ \
@@ -882,10 +882,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD_D_VARS \
   /* Instruction fields.  */ \
@@ -893,15 +893,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LD_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LDB_VARS \
   /* Instruction fields.  */ \
@@ -912,10 +912,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LDB_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LDB_D_VARS \
   /* Instruction fields.  */ \
@@ -923,15 +923,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDB_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LDH_VARS \
   /* Instruction fields.  */ \
@@ -942,10 +942,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LDH_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LDH_D_VARS \
   /* Instruction fields.  */ \
@@ -953,15 +953,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDH_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LD_PLUS_VARS \
   /* Instruction fields.  */ \
@@ -972,10 +972,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD_PLUS_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_LD24_VARS \
   /* Instruction fields.  */ \
@@ -985,21 +985,21 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LD24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 
 #define EXTRACT_FMT_LDI8_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
-  int f_simm8; \
+  INT f_simm8; \
   unsigned int length;
 #define EXTRACT_FMT_LDI8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 
 #define EXTRACT_FMT_LDI16_VARS \
   /* Instruction fields.  */ \
@@ -1007,15 +1007,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_LDI16_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_LOCK_VARS \
   /* Instruction fields.  */ \
@@ -1026,10 +1026,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_LOCK_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MACHI_A_VARS \
   /* Instruction fields.  */ \
@@ -1041,11 +1041,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MULHI_A_VARS \
   /* Instruction fields.  */ \
@@ -1057,11 +1057,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MULHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MV_VARS \
   /* Instruction fields.  */ \
@@ -1072,10 +1072,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MV_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVFACHI_A_VARS \
   /* Instruction fields.  */ \
@@ -1087,11 +1087,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVFACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
 
 #define EXTRACT_FMT_MVFC_VARS \
   /* Instruction fields.  */ \
@@ -1102,10 +1102,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVFC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MVTACHI_A_VARS \
   /* Instruction fields.  */ \
@@ -1117,11 +1117,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVTACHI_A_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
 
 #define EXTRACT_FMT_MVTC_VARS \
   /* Instruction fields.  */ \
@@ -1132,10 +1132,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MVTC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_NOP_VARS \
   /* Instruction fields.  */ \
@@ -1146,10 +1146,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_NOP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_RAC_DSI_VARS \
   /* Instruction fields.  */ \
@@ -1163,13 +1163,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_RAC_DSI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
-  f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
-  f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
-  f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
+  f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
+  f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
 
 #define EXTRACT_FMT_RTE_VARS \
   /* Instruction fields.  */ \
@@ -1180,10 +1180,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_RTE_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_SETH_VARS \
   /* Instruction fields.  */ \
@@ -1195,11 +1195,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SETH_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SLL3_VARS \
   /* Instruction fields.  */ \
@@ -1207,15 +1207,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_SLL3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SLLI_VARS \
   /* Instruction fields.  */ \
@@ -1226,10 +1226,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SLLI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 
 #define EXTRACT_FMT_ST_VARS \
   /* Instruction fields.  */ \
@@ -1240,10 +1240,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ST_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_ST_D_VARS \
   /* Instruction fields.  */ \
@@ -1251,15 +1251,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_ST_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_STB_VARS \
   /* Instruction fields.  */ \
@@ -1270,10 +1270,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_STB_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_STB_D_VARS \
   /* Instruction fields.  */ \
@@ -1281,15 +1281,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_STB_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_STH_VARS \
   /* Instruction fields.  */ \
@@ -1300,10 +1300,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_STH_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_STH_D_VARS \
   /* Instruction fields.  */ \
@@ -1311,15 +1311,15 @@ struct scache {
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
-  int f_simm16; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_FMT_STH_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_ST_PLUS_VARS \
   /* Instruction fields.  */ \
@@ -1330,10 +1330,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_ST_PLUS_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_TRAP_VARS \
   /* Instruction fields.  */ \
@@ -1344,10 +1344,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_TRAP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_UNLOCK_VARS \
   /* Instruction fields.  */ \
@@ -1358,10 +1358,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_UNLOCK_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_SATB_VARS \
   /* Instruction fields.  */ \
@@ -1373,11 +1373,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SATB_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SAT_VARS \
   /* Instruction fields.  */ \
@@ -1389,11 +1389,11 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SAT_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_FMT_SADD_VARS \
   /* Instruction fields.  */ \
@@ -1404,10 +1404,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SADD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MACWU1_VARS \
   /* Instruction fields.  */ \
@@ -1418,10 +1418,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MACWU1_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MSBLO_VARS \
   /* Instruction fields.  */ \
@@ -1432,10 +1432,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MSBLO_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_MULWU1_VARS \
   /* Instruction fields.  */ \
@@ -1446,10 +1446,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_MULWU1_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_FMT_SC_VARS \
   /* Instruction fields.  */ \
@@ -1460,10 +1460,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_FMT_SC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 
 /* Queued output values of an instruction.  */
 
@@ -1697,4 +1697,11 @@ struct parexec {
   int written;
 };
 
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  PCADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
 #endif /* CPU_M32RXF_H */

diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 6f9492607e2d5f29e480e3d562894a67d6af39e3..bc7625b3a0e31e405977bfc9faa7d4b1183b7917 100644 (file)
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -1,6 +1,6 @@
-/* Simulator instruction decoder for m32r.
+/* Simulator instruction decoder for m32rbf.
 
-This file is machine generated with CGEN.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
 
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
@@ -23,268 +23,276 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #define WANT_CPU
-#define WANT_CPU_M32R
+#define WANT_CPU_M32RBF
 
 #include "sim-main.h"
-#include "sim-xcat.h"
-#include "cpu-sim.h"
-#include "cpu-opc.h"
-
-/* FIXME: wip, may eventually only want one form so this would then go
-   away.  However, in the mean time, having both keeps a stable version
-   around while the cache version is being developed.
-   It may still be useful to allow two versions to exist though.  */
-#if WITH_SCACHE
-#define EX(fn) XCONCAT3 (m32r,_ex_,fn)
-#else
-#define EX(fn) 0
-#endif
-
-#ifdef HAVE_PARALLEL_EXEC
-#ifdef __GNUC__
-#define READ(n) 0
-#else
-#define READ(n) XCONCAT3 (READ,_,n)
-#endif
-#endif
+#include "sim-assert.h"
 
 /* FIXME: Need to review choices for the following.  */
 
 #if WITH_SEM_SWITCH_FULL
-#define FULL(fn) 0
+#define FULL(fn)
 #else
-#define FULL(fn) XCONCAT3 (m32r,_sem_,fn)
+#define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
 #endif
 
 #if WITH_FAST
 #if WITH_SEM_SWITCH_FAST
-#define FAST(fn) 0
+#define FAST(fn)
 #else
-#define FAST(fn) XCONCAT3 (m32r,_semf_,fn) /* f for fast */
+#define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
 #endif
 #else
-#define FAST(fn) 0
-#endif
-
-/*#define DECODE M32R_DECODE*/
-
-/* The decode_illegal case is currently non-static and the generator doesn't
-   prepend m32r_, so simplify things by handling it here.  */
-#define decode_illegal m32r_decode_illegal
-
-#define ITAB(n) m32r_cgen_insn_table_entries[n]
-
-static DECODE decode_add = { M32R_INSN_ADD, & ITAB (M32R_INSN_ADD), EX (fmt_0_add), FULL (add), FAST (add) };
-static DECODE decode_add3 = { M32R_INSN_ADD3, & ITAB (M32R_INSN_ADD3), EX (fmt_1_add3), FULL (add3), FAST (add3) };
-static DECODE decode_and = { M32R_INSN_AND, & ITAB (M32R_INSN_AND), EX (fmt_0_add), FULL (and), FAST (and) };
-static DECODE decode_and3 = { M32R_INSN_AND3, & ITAB (M32R_INSN_AND3), EX (fmt_2_and3), FULL (and3), FAST (and3) };
-static DECODE decode_or = { M32R_INSN_OR, & ITAB (M32R_INSN_OR), EX (fmt_0_add), FULL (or), FAST (or) };
-static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or3), FULL (or3), FAST (or3) };
-static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), FULL (xor), FAST (xor) };
-static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
-static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), FULL (addi), FAST (addi) };
-static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_5_addv), FULL (addv), FAST (addv) };
-static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_6_addv3), FULL (addv3), FAST (addv3) };
-static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_7_addx), FULL (addx), FAST (addx) };
-static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_8_bc8), FULL (bc8), FAST (bc8) };
-static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_9_bc24), FULL (bc24), FAST (bc24) };
-static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_10_beq), FULL (beq), FAST (beq) };
-static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_11_beqz), FULL (beqz), FAST (beqz) };
-static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_11_beqz), FULL (bgez), FAST (bgez) };
-static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_11_beqz), FULL (bgtz), FAST (bgtz) };
-static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_11_beqz), FULL (blez), FAST (blez) };
-static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_11_beqz), FULL (bltz), FAST (bltz) };
-static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_11_beqz), FULL (bnez), FAST (bnez) };
-static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_12_bl8), FULL (bl8), FAST (bl8) };
-static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_13_bl24), FULL (bl24), FAST (bl24) };
-static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_8_bc8), FULL (bnc8), FAST (bnc8) };
-static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_9_bc24), FULL (bnc24), FAST (bnc24) };
-static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_10_beq), FULL (bne), FAST (bne) };
-static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_14_bra8), FULL (bra8), FAST (bra8) };
-static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_15_bra24), FULL (bra24), FAST (bra24) };
-static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_16_cmp), FULL (cmp), FAST (cmp) };
-static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_17_cmpi), FULL (cmpi), FAST (cmpi) };
-static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_16_cmp), FULL (cmpu), FAST (cmpu) };
-static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_18_cmpui), FULL (cmpui), FAST (cmpui) };
-static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_19_div), FULL (div), FAST (div) };
-static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_19_div), FULL (divu), FAST (divu) };
-static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_19_div), FULL (rem), FAST (rem) };
-static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_19_div), FULL (remu), FAST (remu) };
-static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_20_jl), FULL (jl), FAST (jl) };
-static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_21_jmp), FULL (jmp), FAST (jmp) };
-static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_22_ld), FULL (ld), FAST (ld) };
-static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_23_ld_d), FULL (ld_d), FAST (ld_d) };
-static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_24_ldb), FULL (ldb), FAST (ldb) };
-static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_25_ldb_d), FULL (ldb_d), FAST (ldb_d) };
-static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_26_ldh), FULL (ldh), FAST (ldh) };
-static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_27_ldh_d), FULL (ldh_d), FAST (ldh_d) };
-static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_24_ldb), FULL (ldub), FAST (ldub) };
-static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_25_ldb_d), FULL (ldub_d), FAST (ldub_d) };
-static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_26_ldh), FULL (lduh), FAST (lduh) };
-static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_27_ldh_d), FULL (lduh_d), FAST (lduh_d) };
-static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_28_ld_plus), FULL (ld_plus), FAST (ld_plus) };
-static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_29_ld24), FULL (ld24), FAST (ld24) };
-static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_30_ldi8), FULL (ldi8), FAST (ldi8) };
-static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_31_ldi16), FULL (ldi16), FAST (ldi16) };
-static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_32_lock), FULL (lock), FAST (lock) };
-static DECODE decode_machi = { M32R_INSN_MACHI, & ITAB (M32R_INSN_MACHI), EX (fmt_33_machi), FULL (machi), FAST (machi) };
-static DECODE decode_maclo = { M32R_INSN_MACLO, & ITAB (M32R_INSN_MACLO), EX (fmt_33_machi), FULL (maclo), FAST (maclo) };
-static DECODE decode_macwhi = { M32R_INSN_MACWHI, & ITAB (M32R_INSN_MACWHI), EX (fmt_33_machi), FULL (macwhi), FAST (macwhi) };
-static DECODE decode_macwlo = { M32R_INSN_MACWLO, & ITAB (M32R_INSN_MACWLO), EX (fmt_33_machi), FULL (macwlo), FAST (macwlo) };
-static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), FULL (mul), FAST (mul) };
-static DECODE decode_mulhi = { M32R_INSN_MULHI, & ITAB (M32R_INSN_MULHI), EX (fmt_34_mulhi), FULL (mulhi), FAST (mulhi) };
-static DECODE decode_mullo = { M32R_INSN_MULLO, & ITAB (M32R_INSN_MULLO), EX (fmt_34_mulhi), FULL (mullo), FAST (mullo) };
-static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & ITAB (M32R_INSN_MULWHI), EX (fmt_34_mulhi), FULL (mulwhi), FAST (mulwhi) };
-static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & ITAB (M32R_INSN_MULWLO), EX (fmt_34_mulhi), FULL (mulwlo), FAST (mulwlo) };
-static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_35_mv), FULL (mv), FAST (mv) };
-static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & ITAB (M32R_INSN_MVFACHI), EX (fmt_36_mvfachi), FULL (mvfachi), FAST (mvfachi) };
-static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & ITAB (M32R_INSN_MVFACLO), EX (fmt_36_mvfachi), FULL (mvfaclo), FAST (mvfaclo) };
-static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & ITAB (M32R_INSN_MVFACMI), EX (fmt_36_mvfachi), FULL (mvfacmi), FAST (mvfacmi) };
-static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_37_mvfc), FULL (mvfc), FAST (mvfc) };
-static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & ITAB (M32R_INSN_MVTACHI), EX (fmt_38_mvtachi), FULL (mvtachi), FAST (mvtachi) };
-static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & ITAB (M32R_INSN_MVTACLO), EX (fmt_38_mvtachi), FULL (mvtaclo), FAST (mvtaclo) };
-static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_39_mvtc), FULL (mvtc), FAST (mvtc) };
-static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_35_mv), FULL (neg), FAST (neg) };
-static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_40_nop), FULL (nop), FAST (nop) };
-static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_35_mv), FULL (not), FAST (not) };
-static DECODE decode_rac = { M32R_INSN_RAC, & ITAB (M32R_INSN_RAC), EX (fmt_41_rac), FULL (rac), FAST (rac) };
-static DECODE decode_rach = { M32R_INSN_RACH, & ITAB (M32R_INSN_RACH), EX (fmt_41_rac), FULL (rach), FAST (rach) };
-static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_42_rte), FULL (rte), FAST (rte) };
-static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_43_seth), FULL (seth), FAST (seth) };
-static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), FULL (sll), FAST (sll) };
-static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_44_sll3), FULL (sll3), FAST (sll3) };
-static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_45_slli), FULL (slli), FAST (slli) };
-static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), FULL (sra), FAST (sra) };
-static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_44_sll3), FULL (sra3), FAST (sra3) };
-static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_45_slli), FULL (srai), FAST (srai) };
-static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), FULL (srl), FAST (srl) };
-static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_44_sll3), FULL (srl3), FAST (srl3) };
-static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_45_slli), FULL (srli), FAST (srli) };
-static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_46_st), FULL (st), FAST (st) };
-static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_47_st_d), FULL (st_d), FAST (st_d) };
-static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_48_stb), FULL (stb), FAST (stb) };
-static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_49_stb_d), FULL (stb_d), FAST (stb_d) };
-static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_50_sth), FULL (sth), FAST (sth) };
-static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_51_sth_d), FULL (sth_d), FAST (sth_d) };
-static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_52_st_plus), FULL (st_plus), FAST (st_plus) };
-static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_52_st_plus), FULL (st_minus), FAST (st_minus) };
-static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), FULL (sub), FAST (sub) };
-static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_5_addv), FULL (subv), FAST (subv) };
-static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_7_addx), FULL (subx), FAST (subx) };
-static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_53_trap), FULL (trap), FAST (trap) };
-static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_54_unlock), FULL (unlock), FAST (unlock) };
-
-DECODE m32r_decode_illegal = {
-  M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL),
-  EX (illegal), FULL (illegal), FAST (illegal)
+#define FAST(fn)
+#endif
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
+
+/* Instruction semantic handlers and support.
+   This struct defines the part of an IDESC that can be computed at
+   compile time.  */
+
+struct insn_sem {
+  /* The instruction type (a number that identifies each insn over the
+     entire architecture).  */
+  CGEN_INSN_TYPE type;
+
+  /* Index in IDESC table.  */
+  int index;
+
+  /* Routines to execute the insn.
+     The full version has all features (profiling,tracing) compiled in.
+     The fast version has none of that.  */
+#if ! WITH_SEM_SWITCH_FULL
+  SEMANTIC_FN *sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  SEMANTIC_FN *sem_fast;
+#endif
+
 };
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
+#define IDX(insn) CONCAT2 (M32RBF_,insn)
+#define TYPE(insn) CONCAT2 (M32R_,insn)
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
 
-/* The order must match that of `labels' in sem-switch.c/read.c.  */
-
-DECODE *m32r_decode_vars[] = {
-  & m32r_decode_illegal,
-  & decode_add,
-  & decode_add3,
-  & decode_and,
-  & decode_and3,
-  & decode_or,
-  & decode_or3,
-  & decode_xor,
-  & decode_xor3,
-  & decode_addi,
-  & decode_addv,
-  & decode_addv3,
-  & decode_addx,
-  & decode_bc8,
-  & decode_bc24,
-  & decode_beq,
-  & decode_beqz,
-  & decode_bgez,
-  & decode_bgtz,
-  & decode_blez,
-  & decode_bltz,
-  & decode_bnez,
-  & decode_bl8,
-  & decode_bl24,
-  & decode_bnc8,
-  & decode_bnc24,
-  & decode_bne,
-  & decode_bra8,
-  & decode_bra24,
-  & decode_cmp,
-  & decode_cmpi,
-  & decode_cmpu,
-  & decode_cmpui,
-  & decode_div,
-  & decode_divu,
-  & decode_rem,
-  & decode_remu,
-  & decode_jl,
-  & decode_jmp,
-  & decode_ld,
-  & decode_ld_d,
-  & decode_ldb,
-  & decode_ldb_d,
-  & decode_ldh,
-  & decode_ldh_d,
-  & decode_ldub,
-  & decode_ldub_d,
-  & decode_lduh,
-  & decode_lduh_d,
-  & decode_ld_plus,
-  & decode_ld24,
-  & decode_ldi8,
-  & decode_ldi16,
-  & decode_lock,
-  & decode_machi,
-  & decode_maclo,
-  & decode_macwhi,
-  & decode_macwlo,
-  & decode_mul,
-  & decode_mulhi,
-  & decode_mullo,
-  & decode_mulwhi,
-  & decode_mulwlo,
-  & decode_mv,
-  & decode_mvfachi,
-  & decode_mvfaclo,
-  & decode_mvfacmi,
-  & decode_mvfc,
-  & decode_mvtachi,
-  & decode_mvtaclo,
-  & decode_mvtc,
-  & decode_neg,
-  & decode_nop,
-  & decode_not,
-  & decode_rac,
-  & decode_rach,
-  & decode_rte,
-  & decode_seth,
-  & decode_sll,
-  & decode_sll3,
-  & decode_slli,
-  & decode_sra,
-  & decode_sra3,
-  & decode_srai,
-  & decode_srl,
-  & decode_srl3,
-  & decode_srli,
-  & decode_st,
-  & decode_st_d,
-  & decode_stb,
-  & decode_stb_d,
-  & decode_sth,
-  & decode_sth_d,
-  & decode_st_plus,
-  & decode_st_minus,
-  & decode_sub,
-  & decode_subv,
-  & decode_subx,
-  & decode_trap,
-  & decode_unlock,
-  0
+static const struct insn_sem m32rbf_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
+  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
+  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
+  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
+  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
+  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
+  { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
+  { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) },
+  { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
+  { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
+  { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
+  { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
+  { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
+  { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
+  { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
+  { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) },
+  { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) },
+  { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) },
+  { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) },
+  { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) },
+  { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
+  { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) },
+  { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) },
+  { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) },
+  { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) },
+  { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) },
+  { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) },
+  { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) },
+  { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) },
+  { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) },
+  { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) },
+  { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
+  { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) },
+  { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) },
+  { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
+  { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
+  { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) },
+  { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) },
+  { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) },
+  { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) },
+  { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) },
+  { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) },
+  { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) },
+  { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
+  { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
+  { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) },
+  { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) },
+  { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) },
+  { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) },
+  { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) },
+  { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
+  { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) },
+  { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
+  { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) },
+  { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
+  { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) },
+  { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
+  { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) },
+  { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) },
+  { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) },
+  { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) },
+  { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) },
+  { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) },
+  { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
+  { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) },
+  { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) },
+  { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) },
+  { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) },
+  { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) },
+  { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) },
+  { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) },
+  { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) },
+  { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) },
+  { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) },
+  { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) },
+  { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) },
+  { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) },
+  { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
+  { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
+  { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) },
+  { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) },
+  { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) },
+  { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) },
+  { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) },
+  { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) },
+  { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) },
+  { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) },
+  { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) },
+  { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) },
+  { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) },
+  { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) },
+  { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) },
+  { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
+  { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) },
+  { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
+  { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) },
+  { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
+  { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) },
+  { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) },
+  { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) },
+  { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
+  { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) },
+  { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) },
+  { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) },
+  { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) },
 };
 
+static const struct insn_sem m32rbf_insn_sem_invalid =
+{
+  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
+};
+
+#undef IDX
+#undef TYPE
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
+
+  id->num = t->index;
+  if ((int) t->type <= 0)
+    id->opcode = & cgen_virtual_opcode_table[- t->type];
+  else
+    id->opcode = & opcode_table[t->type];
+#if ! WITH_SEM_SWITCH_FULL
+  id->sem_full = t->sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  id->sem_fast = t->sem_fast;
+#endif
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+m32rbf_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = M32RBF_INSN_MAX;
+  IDESC *table = m32rbf_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & m32rbf_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Enum declaration for all instruction formats.  */
+typedef enum ifmt {
+  FMT_ADD, FMT_ADD3, FMT_AND3, FMT_OR3
+ , FMT_ADDI, FMT_ADDV, FMT_ADDV3, FMT_ADDX
+ , FMT_BC8, FMT_BC24, FMT_BEQ, FMT_BEQZ
+ , FMT_BL8, FMT_BL24, FMT_BRA8, FMT_BRA24
+ , FMT_CMP, FMT_CMPI, FMT_DIV, FMT_JL
+ , FMT_JMP, FMT_LD, FMT_LD_D, FMT_LDB
+ , FMT_LDB_D, FMT_LDH, FMT_LDH_D, FMT_LD_PLUS
+ , FMT_LD24, FMT_LDI8, FMT_LDI16, FMT_LOCK
+ , FMT_MACHI, FMT_MULHI, FMT_MV, FMT_MVFACHI
+ , FMT_MVFC, FMT_MVTACHI, FMT_MVTC, FMT_NOP
+ , FMT_RAC, FMT_RTE, FMT_SETH, FMT_SLL3
+ , FMT_SLLI, FMT_ST, FMT_ST_D, FMT_STB
+ , FMT_STB_D, FMT_STH, FMT_STH_D, FMT_ST_PLUS
+ , FMT_TRAP, FMT_UNLOCK
+} IFMT;
+
+/* The decoder uses this to record insns and direct extraction handling.  */
+
+typedef struct {
+  const IDESC *idesc;
+#ifdef __GNUC__
+  void *ifmt;
+#else
+  enum ifmt ifmt;
+#endif
+} DECODE_DESC;
+
+/* Macro to go from decode phase to extraction phase.  */
+
+#ifdef __GNUC__
+#define GOTO_EXTRACT(id) goto *(id)->ifmt
+#else
+#define GOTO_EXTRACT(id) goto extract
+#endif
+
 /* The decoder needs a slightly different computed goto switch control.  */
 #ifdef __GNUC__
 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
@@ -292,250 +300,1702 @@ DECODE *m32r_decode_vars[] = {
 #define DECODE_SWITCH(N, X) switch (X)
 #endif
 
-/* Given an instruction, return a pointer to its DECODE entry.  */
+/* Given an instruction, return a pointer to its IDESC entry.  */
 
-DECODE *
-m32r_decode (current_cpu, pc, insn)
-     SIM_CPU *current_cpu;
-     PCADDR pc;
-     insn_t insn;
+const IDESC *
+m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
+              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              ARGBUF *abuf)
 {
+  /* Result of decoder, used by extractor.  */
+  const DECODE_DESC *idecode;
+
+  /* First decode the instruction.  */
+
   {
+#define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
 #ifdef __GNUC__
-    static void *labels_0[256] = {
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_28, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && case_0_87, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && case_0_95, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
-      && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
-      && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
-      && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
-      && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
-      && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
-      && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
-    };
-#endif
-    static DECODE *insns[256] = {
-      &decode_subv, &decode_subx, &decode_sub, &decode_neg, 
-      &decode_cmp, &decode_cmpu, &decode_illegal, &decode_illegal, 
-      &decode_addv, &decode_addx, &decode_add, &decode_not, 
-      &decode_and, &decode_xor, &decode_or, &decode_illegal, 
-      &decode_srl, &decode_illegal, &decode_sra, &decode_illegal, 
-      &decode_sll, &decode_illegal, &decode_mul, &decode_illegal, 
-      &decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal, 
-      0, &decode_rte, &decode_illegal, &decode_trap, 
-      &decode_stb, &decode_illegal, &decode_sth, &decode_illegal, 
-      &decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus, 
-      &decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh, 
-      &decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal, 
-      &decode_mulhi, &decode_mullo, &decode_mulwhi, &decode_mulwlo, 
-      &decode_machi, &decode_maclo, &decode_macwhi, &decode_macwlo, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
-      &decode_slli, &decode_slli, &decode_illegal, 0, 
-      &decode_rach, &decode_rac, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, 0, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
-      &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
-      &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
-      &decode_div, &decode_divu, &decode_rem, &decode_remu, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
-      &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
-      &decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal, 
-      &decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d, 
-      &decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_beq, &decode_bne, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez, 
-      &decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_seth, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-    };
-    unsigned int val;
-    val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-    DECODE_SWITCH (0, val)
-      {
-      CASE (0, 28) :
-        {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_jl, &decode_jmp, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 87) :
-        {
-          static DECODE *insns[16] = {
-            &decode_mvtachi, &decode_mvtaclo, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val = (((insn >> 0) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 95) :
-        {
-          static DECODE *insns[16] = {
-            &decode_mvfachi, &decode_mvfaclo, &decode_mvfacmi, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val = (((insn >> 0) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 112) :
-        {
-          static DECODE *insns[16] = {
-            &decode_nop, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 113) : /* fall through */
-      CASE (0, 114) : /* fall through */
-      CASE (0, 115) : /* fall through */
-      CASE (0, 116) : /* fall through */
-      CASE (0, 117) : /* fall through */
-      CASE (0, 118) : /* fall through */
-      CASE (0, 119) : /* fall through */
-      CASE (0, 120) : /* fall through */
-      CASE (0, 121) : /* fall through */
-      CASE (0, 122) : /* fall through */
-      CASE (0, 123) : /* fall through */
-      CASE (0, 124) : /* fall through */
-      CASE (0, 125) : /* fall through */
-      CASE (0, 126) : /* fall through */
-      CASE (0, 127) :
-        {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 240) : /* fall through */
-      CASE (0, 241) : /* fall through */
-      CASE (0, 242) : /* fall through */
-      CASE (0, 243) : /* fall through */
-      CASE (0, 244) : /* fall through */
-      CASE (0, 245) : /* fall through */
-      CASE (0, 246) : /* fall through */
-      CASE (0, 247) : /* fall through */
-      CASE (0, 248) : /* fall through */
-      CASE (0, 249) : /* fall through */
-      CASE (0, 250) : /* fall through */
-      CASE (0, 251) : /* fall through */
-      CASE (0, 252) : /* fall through */
-      CASE (0, 253) : /* fall through */
-      CASE (0, 254) : /* fall through */
-      CASE (0, 255) :
+#define E(fmt) && case_ex_##fmt
+#else
+#define E(fmt) fmt
+#endif
+    CGEN_INSN_INT insn = base_insn;
+    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
+    {
+#ifdef __GNUC__
+      static const void *labels_0[256] = {
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_28, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_87, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_95, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
+        && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
+        && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
+        && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
+        && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
+        && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
+        && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
+      };
+#endif
+      static const DECODE_DESC insns[256] = {
+        { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, 
+        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, 
+        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, 
+        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, 
+        { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, 
+        { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, 
+        { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_RTE), E (FMT_RTE) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, 
+        { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, 
+        { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, 
+        { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, 
+        { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, 
+        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, 
+        { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) }, 
+        { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) }, 
+        { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) }, 
+        { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, 
+        { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, 
+        { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+        { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, 
+        { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) }, 
+        { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, 
+        { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, 
+        { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, 
+        { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, 
+        { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, 
+        { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+      };
+      unsigned int val;
+      val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      DECODE_SWITCH (0, val)
         {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
+        CASE (0, 28) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 87) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 0) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 95) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) }, 
+              { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 0) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 112) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
+              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 113) : /* fall through */
+        CASE (0, 114) : /* fall through */
+        CASE (0, 115) : /* fall through */
+        CASE (0, 116) : /* fall through */
+        CASE (0, 117) : /* fall through */
+        CASE (0, 118) : /* fall through */
+        CASE (0, 119) : /* fall through */
+        CASE (0, 120) : /* fall through */
+        CASE (0, 121) : /* fall through */
+        CASE (0, 122) : /* fall through */
+        CASE (0, 123) : /* fall through */
+        CASE (0, 124) : /* fall through */
+        CASE (0, 125) : /* fall through */
+        CASE (0, 126) : /* fall through */
+        CASE (0, 127) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
+              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 240) : /* fall through */
+        CASE (0, 241) : /* fall through */
+        CASE (0, 242) : /* fall through */
+        CASE (0, 243) : /* fall through */
+        CASE (0, 244) : /* fall through */
+        CASE (0, 245) : /* fall through */
+        CASE (0, 246) : /* fall through */
+        CASE (0, 247) : /* fall through */
+        CASE (0, 248) : /* fall through */
+        CASE (0, 249) : /* fall through */
+        CASE (0, 250) : /* fall through */
+        CASE (0, 251) : /* fall through */
+        CASE (0, 252) : /* fall through */
+        CASE (0, 253) : /* fall through */
+        CASE (0, 254) : /* fall through */
+        CASE (0, 255) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, 
+              { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        DEFAULT (0) :
+          idecode = &insns[val];
+          GOTO_EXTRACT (idecode);
         }
-      DEFAULT (0) : return insns[val];
+      ENDSWITCH (0)
+    }
+#undef I
+#undef E
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract:
+  {
+#ifndef __GNUC__
+    switch (idecode->ifmt)
+#endif
+      {
+
+  CASE (ex, FMT_ADD) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_add.f
+  EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADD3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_add3.f
+  EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ADD3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_add3", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_AND3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_and3.f
+  EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_AND3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_uimm16) = f_uimm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_and3", "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_OR3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_or3.f
+  EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_OR3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_uimm16) = f_uimm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_or3", "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addi.f
+  EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (f_simm8) = f_simm8;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addv.f
+  EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADDV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDV3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addv3.f
+  EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ADDV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addv3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDX) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addx.f
+  EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADDX_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BC8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BC8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BC24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BC24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BEQ) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_BEQ_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_disp16) = f_disp16;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BEQZ) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_BEQZ_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_disp16) = f_disp16;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BL8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+  EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BL8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BL24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+  EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BL24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BRA8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+  EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BRA8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BRA24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+  EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BRA24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_cmp.f
+  EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_CMP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_CMPI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_div.f
+  EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_DIV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JL) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+  EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_JL_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JMP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_JMP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld.f
+  EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld_d.f
+  EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LD_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDB) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldb.f
+  EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LDB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDB_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldb_d.f
+  EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDB_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldb_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldh.f
+  EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LDH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDH_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldh_d.f
+  EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDH_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldh_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_PLUS) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld_plus.f
+  EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LD_PLUS_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+      FLD (out_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld24.f
+  EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
+
+  EXTRACT_FMT_LD24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm24) = f_uimm24;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_LDI8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm8) = f_simm8;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI16) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldi16.f
+  EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDI16_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LOCK) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_lock.f
+  EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LOCK_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MACHI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_machi.f
+  EXTRACT_FMT_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MACHI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULHI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mulhi.f
+  EXTRACT_FMT_MULHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MULHI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mv.f
+  EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVFACHI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvfachi.f
+  EXTRACT_FMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVFACHI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVFC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvfc.f
+  EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVFC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvfc", "scr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVTACHI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvtachi.f
+  EXTRACT_FMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVTACHI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVTC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvtc.f
+  EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVTC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_r1) = f_r1;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvtc", "sr 0x%x", 'x', f_r2, "dcr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_nop.f
+  EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_NOP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_nop", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RAC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_rac.f
+  EXTRACT_FMT_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_RAC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_rac", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RTE) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+  EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_RTE_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_rte", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SETH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_seth.f
+  EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+
+  EXTRACT_FMT_SETH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hi16) = f_hi16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_seth", "hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SLL3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sll3.f
+  EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_SLL3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sll3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SLLI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_slli.f
+  EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+
+  EXTRACT_FMT_SLLI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (f_uimm5) = f_uimm5;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st.f
+  EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ST_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st_d.f
+  EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ST_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STB) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_stb.f
+  EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_STB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STB_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_stb_d.f
+  EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_STB_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_stb_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sth.f
+  EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_STH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STH_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sth_d.f
+  EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_STH_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sth_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_PLUS) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st_plus.f
+  EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ST_PLUS_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+      FLD (out_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_TRAP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+  EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+
+  EXTRACT_FMT_TRAP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm4) = f_uimm4;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_UNLOCK) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_unlock.f
+  EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_UNLOCK_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+      CASE (ex, FMT_EMPTY) :
+        BREAK (ex);
+
       }
-    ENDSWITCH (0)
+    ENDSWITCH (ex)
+
+    return idecode->idesc;
   }
 }

diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 75280a9fe4930fa08dba81e2e04c96462d56c1f6..b251360877b9763d22be3e824f2215265f7fb665 100644 (file)
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -1,6 +1,6 @@
-/* Simulator instruction decoder for m32r.
+/* Simulator instruction decoder for m32rxf.
 
-This file is machine generated with CGEN.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
 
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
@@ -23,299 +23,325 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #define WANT_CPU
-#define WANT_CPU_M32RX
+#define WANT_CPU_M32RXF
 
 #include "sim-main.h"
-#include "cpu-sim.h"
-#include "cpu-opc.h"
-
-/* FIXME: wip, may eventually only want one form so this would then go
-   away.  However, in the mean time, having both keeps a stable version
-   around while the cache version is being developed.
-   It may still be useful to allow two versions to exist though.  */
-#if WITH_SCACHE
-#define EX(fn) CONCAT3 (m32rx,_ex_,fn)
-#else
-#define EX(fn) 0
-#endif
+#include "sim-assert.h"
 
-#ifdef HAVE_PARALLEL_EXEC
 #ifdef __GNUC__
-#define READ(n) 0
+#define FMT(n)
 #else
-#define READ(n) CONCAT3 (READ,_,n)
-#endif
+#define FMT(n) CONCAT2 (M32RXF_,n) ,
 #endif
 
 /* FIXME: Need to review choices for the following.  */
 
 #if WITH_SEM_SWITCH_FULL
-#define FULL(fn) 0
+#define FULL(fn)
 #else
-#define FULL(fn) CONCAT3 (m32rx,_sem_,fn)
+#define FULL(fn) CONCAT3 (m32rxf,_sem_,fn) ,
 #endif
 
 #if WITH_FAST
 #if WITH_SEM_SWITCH_FAST
-#define FAST(fn) 0
+#define FAST(fn)
 #else
-#define FAST(fn) CONCAT3 (m32rx,_semf_,fn) /* f for fast */
+#define FAST(fn) CONCAT3 (m32rxf,_semf_,fn) , /* f for fast */
 #endif
 #else
-#define FAST(fn) 0
-#endif
-
-/*#define DECODE M32RX_DECODE*/
-
-/* The decode_illegal case is currently non-static and the generator doesn't
-   prepend m32rx_, so simplify things by handling it here.  */
-#define decode_illegal m32rx_decode_illegal
-
-#define ITAB(n) m32r_cgen_insn_table_entries[n]
-
-static DECODE decode_add = { M32R_INSN_ADD, & ITAB (M32R_INSN_ADD), EX (fmt_0_add), READ (FMT_0_ADD), FULL (add), FAST (add) };
-static DECODE decode_add3 = { M32R_INSN_ADD3, & ITAB (M32R_INSN_ADD3), EX (fmt_1_add3), READ (FMT_1_ADD3), FULL (add3), FAST (add3) };
-static DECODE decode_and = { M32R_INSN_AND, & ITAB (M32R_INSN_AND), EX (fmt_0_add), READ (FMT_0_ADD), FULL (and), FAST (and) };
-static DECODE decode_and3 = { M32R_INSN_AND3, & ITAB (M32R_INSN_AND3), EX (fmt_2_and3), READ (FMT_2_AND3), FULL (and3), FAST (and3) };
-static DECODE decode_or = { M32R_INSN_OR, & ITAB (M32R_INSN_OR), EX (fmt_0_add), READ (FMT_0_ADD), FULL (or), FAST (or) };
-static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or3), READ (FMT_3_OR3), FULL (or3), FAST (or3) };
-static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), READ (FMT_0_ADD), FULL (xor), FAST (xor) };
-static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), READ (FMT_2_AND3), FULL (xor3), FAST (xor3) };
-static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), READ (FMT_4_ADDI), FULL (addi), FAST (addi) };
-static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_5_addv), READ (FMT_5_ADDV), FULL (addv), FAST (addv) };
-static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_6_addv3), READ (FMT_6_ADDV3), FULL (addv3), FAST (addv3) };
-static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_7_addx), READ (FMT_7_ADDX), FULL (addx), FAST (addx) };
-static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_8_bc8), READ (FMT_8_BC8), FULL (bc8), FAST (bc8) };
-static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_9_bc24), READ (FMT_9_BC24), FULL (bc24), FAST (bc24) };
-static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_10_beq), READ (FMT_10_BEQ), FULL (beq), FAST (beq) };
-static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (beqz), FAST (beqz) };
-static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bgez), FAST (bgez) };
-static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bgtz), FAST (bgtz) };
-static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (blez), FAST (blez) };
-static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bltz), FAST (bltz) };
-static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bnez), FAST (bnez) };
-static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_12_bl8), READ (FMT_12_BL8), FULL (bl8), FAST (bl8) };
-static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_13_bl24), READ (FMT_13_BL24), FULL (bl24), FAST (bl24) };
-static DECODE decode_bcl8 = { M32R_INSN_BCL8, & ITAB (M32R_INSN_BCL8), EX (fmt_14_bcl8), READ (FMT_14_BCL8), FULL (bcl8), FAST (bcl8) };
-static DECODE decode_bcl24 = { M32R_INSN_BCL24, & ITAB (M32R_INSN_BCL24), EX (fmt_15_bcl24), READ (FMT_15_BCL24), FULL (bcl24), FAST (bcl24) };
-static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_8_bc8), READ (FMT_8_BC8), FULL (bnc8), FAST (bnc8) };
-static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_9_bc24), READ (FMT_9_BC24), FULL (bnc24), FAST (bnc24) };
-static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_10_beq), READ (FMT_10_BEQ), FULL (bne), FAST (bne) };
-static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_16_bra8), READ (FMT_16_BRA8), FULL (bra8), FAST (bra8) };
-static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_17_bra24), READ (FMT_17_BRA24), FULL (bra24), FAST (bra24) };
-static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & ITAB (M32R_INSN_BNCL8), EX (fmt_14_bcl8), READ (FMT_14_BCL8), FULL (bncl8), FAST (bncl8) };
-static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & ITAB (M32R_INSN_BNCL24), EX (fmt_15_bcl24), READ (FMT_15_BCL24), FULL (bncl24), FAST (bncl24) };
-static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmp), FAST (cmp) };
-static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_19_cmpi), READ (FMT_19_CMPI), FULL (cmpi), FAST (cmpi) };
-static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmpu), FAST (cmpu) };
-static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_20_cmpui), READ (FMT_20_CMPUI), FULL (cmpui), FAST (cmpui) };
-static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & ITAB (M32R_INSN_CMPEQ), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmpeq), FAST (cmpeq) };
-static DECODE decode_cmpz = { M32R_INSN_CMPZ, & ITAB (M32R_INSN_CMPZ), EX (fmt_21_cmpz), READ (FMT_21_CMPZ), FULL (cmpz), FAST (cmpz) };
-static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_22_div), READ (FMT_22_DIV), FULL (div), FAST (div) };
-static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_22_div), READ (FMT_22_DIV), FULL (divu), FAST (divu) };
-static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_22_div), READ (FMT_22_DIV), FULL (rem), FAST (rem) };
-static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_22_div), READ (FMT_22_DIV), FULL (remu), FAST (remu) };
-static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_22_div), READ (FMT_22_DIV), FULL (divh), FAST (divh) };
-static DECODE decode_jc = { M32R_INSN_JC, & ITAB (M32R_INSN_JC), EX (fmt_23_jc), READ (FMT_23_JC), FULL (jc), FAST (jc) };
-static DECODE decode_jnc = { M32R_INSN_JNC, & ITAB (M32R_INSN_JNC), EX (fmt_23_jc), READ (FMT_23_JC), FULL (jnc), FAST (jnc) };
-static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_24_jl), READ (FMT_24_JL), FULL (jl), FAST (jl) };
-static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_25_jmp), READ (FMT_25_JMP), FULL (jmp), FAST (jmp) };
-static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_26_ld), READ (FMT_26_LD), FULL (ld), FAST (ld) };
-static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_27_ld_d), READ (FMT_27_LD_D), FULL (ld_d), FAST (ld_d) };
-static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_28_ldb), READ (FMT_28_LDB), FULL (ldb), FAST (ldb) };
-static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_29_ldb_d), READ (FMT_29_LDB_D), FULL (ldb_d), FAST (ldb_d) };
-static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_30_ldh), READ (FMT_30_LDH), FULL (ldh), FAST (ldh) };
-static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_31_ldh_d), READ (FMT_31_LDH_D), FULL (ldh_d), FAST (ldh_d) };
-static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_28_ldb), READ (FMT_28_LDB), FULL (ldub), FAST (ldub) };
-static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_29_ldb_d), READ (FMT_29_LDB_D), FULL (ldub_d), FAST (ldub_d) };
-static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_30_ldh), READ (FMT_30_LDH), FULL (lduh), FAST (lduh) };
-static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_31_ldh_d), READ (FMT_31_LDH_D), FULL (lduh_d), FAST (lduh_d) };
-static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_32_ld_plus), READ (FMT_32_LD_PLUS), FULL (ld_plus), FAST (ld_plus) };
-static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_33_ld24), READ (FMT_33_LD24), FULL (ld24), FAST (ld24) };
-static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_34_ldi8), READ (FMT_34_LDI8), FULL (ldi8), FAST (ldi8) };
-static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_35_ldi16), READ (FMT_35_LDI16), FULL (ldi16), FAST (ldi16) };
-static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_36_lock), READ (FMT_36_LOCK), FULL (lock), FAST (lock) };
-static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & ITAB (M32R_INSN_MACHI_A), EX (fmt_37_machi_a), READ (FMT_37_MACHI_A), FULL (machi_a), FAST (machi_a) };
-static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & ITAB (M32R_INSN_MACLO_A), EX (fmt_37_machi_a), READ (FMT_37_MACHI_A), FULL (maclo_a), FAST (maclo_a) };
-static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (mul), FAST (mul) };
-static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & ITAB (M32R_INSN_MULHI_A), EX (fmt_38_mulhi_a), READ (FMT_38_MULHI_A), FULL (mulhi_a), FAST (mulhi_a) };
-static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & ITAB (M32R_INSN_MULLO_A), EX (fmt_38_mulhi_a), READ (FMT_38_MULHI_A), FULL (mullo_a), FAST (mullo_a) };
-static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_39_mv), READ (FMT_39_MV), FULL (mv), FAST (mv) };
-static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & ITAB (M32R_INSN_MVFACHI_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfachi_a), FAST (mvfachi_a) };
-static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & ITAB (M32R_INSN_MVFACLO_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfaclo_a), FAST (mvfaclo_a) };
-static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & ITAB (M32R_INSN_MVFACMI_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfacmi_a), FAST (mvfacmi_a) };
-static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_41_mvfc), READ (FMT_41_MVFC), FULL (mvfc), FAST (mvfc) };
-static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & ITAB (M32R_INSN_MVTACHI_A), EX (fmt_42_mvtachi_a), READ (FMT_42_MVTACHI_A), FULL (mvtachi_a), FAST (mvtachi_a) };
-static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & ITAB (M32R_INSN_MVTACLO_A), EX (fmt_42_mvtachi_a), READ (FMT_42_MVTACHI_A), FULL (mvtaclo_a), FAST (mvtaclo_a) };
-static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_43_mvtc), READ (FMT_43_MVTC), FULL (mvtc), FAST (mvtc) };
-static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_39_mv), READ (FMT_39_MV), FULL (neg), FAST (neg) };
-static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_44_nop), READ (FMT_44_NOP), FULL (nop), FAST (nop) };
-static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_39_mv), READ (FMT_39_MV), FULL (not), FAST (not) };
-static DECODE decode_rac_dsi = { M32R_INSN_RAC_DSI, & ITAB (M32R_INSN_RAC_DSI), EX (fmt_45_rac_dsi), READ (FMT_45_RAC_DSI), FULL (rac_dsi), FAST (rac_dsi) };
-static DECODE decode_rach_dsi = { M32R_INSN_RACH_DSI, & ITAB (M32R_INSN_RACH_DSI), EX (fmt_45_rac_dsi), READ (FMT_45_RAC_DSI), FULL (rach_dsi), FAST (rach_dsi) };
-static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_46_rte), READ (FMT_46_RTE), FULL (rte), FAST (rte) };
-static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_47_seth), READ (FMT_47_SETH), FULL (seth), FAST (seth) };
-static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sll), FAST (sll) };
-static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (sll3), FAST (sll3) };
-static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (slli), FAST (slli) };
-static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sra), FAST (sra) };
-static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (sra3), FAST (sra3) };
-static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (srai), FAST (srai) };
-static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (srl), FAST (srl) };
-static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (srl3), FAST (srl3) };
-static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (srli), FAST (srli) };
-static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_50_st), READ (FMT_50_ST), FULL (st), FAST (st) };
-static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_51_st_d), READ (FMT_51_ST_D), FULL (st_d), FAST (st_d) };
-static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_52_stb), READ (FMT_52_STB), FULL (stb), FAST (stb) };
-static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_53_stb_d), READ (FMT_53_STB_D), FULL (stb_d), FAST (stb_d) };
-static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_54_sth), READ (FMT_54_STH), FULL (sth), FAST (sth) };
-static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_55_sth_d), READ (FMT_55_STH_D), FULL (sth_d), FAST (sth_d) };
-static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_56_st_plus), READ (FMT_56_ST_PLUS), FULL (st_plus), FAST (st_plus) };
-static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_56_st_plus), READ (FMT_56_ST_PLUS), FULL (st_minus), FAST (st_minus) };
-static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sub), FAST (sub) };
-static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_5_addv), READ (FMT_5_ADDV), FULL (subv), FAST (subv) };
-static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_7_addx), READ (FMT_7_ADDX), FULL (subx), FAST (subx) };
-static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_57_trap), READ (FMT_57_TRAP), FULL (trap), FAST (trap) };
-static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_58_unlock), READ (FMT_58_UNLOCK), FULL (unlock), FAST (unlock) };
-static DECODE decode_satb = { M32R_INSN_SATB, & ITAB (M32R_INSN_SATB), EX (fmt_59_satb), READ (FMT_59_SATB), FULL (satb), FAST (satb) };
-static DECODE decode_sath = { M32R_INSN_SATH, & ITAB (M32R_INSN_SATH), EX (fmt_59_satb), READ (FMT_59_SATB), FULL (sath), FAST (sath) };
-static DECODE decode_sat = { M32R_INSN_SAT, & ITAB (M32R_INSN_SAT), EX (fmt_60_sat), READ (FMT_60_SAT), FULL (sat), FAST (sat) };
-static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & ITAB (M32R_INSN_PCMPBZ), EX (fmt_21_cmpz), READ (FMT_21_CMPZ), FULL (pcmpbz), FAST (pcmpbz) };
-static DECODE decode_sadd = { M32R_INSN_SADD, & ITAB (M32R_INSN_SADD), EX (fmt_61_sadd), READ (FMT_61_SADD), FULL (sadd), FAST (sadd) };
-static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & ITAB (M32R_INSN_MACWU1), EX (fmt_62_macwu1), READ (FMT_62_MACWU1), FULL (macwu1), FAST (macwu1) };
-static DECODE decode_msblo = { M32R_INSN_MSBLO, & ITAB (M32R_INSN_MSBLO), EX (fmt_63_msblo), READ (FMT_63_MSBLO), FULL (msblo), FAST (msblo) };
-static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & ITAB (M32R_INSN_MULWU1), EX (fmt_64_mulwu1), READ (FMT_64_MULWU1), FULL (mulwu1), FAST (mulwu1) };
-static DECODE decode_maclh1 = { M32R_INSN_MACLH1, & ITAB (M32R_INSN_MACLH1), EX (fmt_62_macwu1), READ (FMT_62_MACWU1), FULL (maclh1), FAST (maclh1) };
-static DECODE decode_sc = { M32R_INSN_SC, & ITAB (M32R_INSN_SC), EX (fmt_65_sc), READ (FMT_65_SC), FULL (sc), FAST (sc) };
-static DECODE decode_snc = { M32R_INSN_SNC, & ITAB (M32R_INSN_SNC), EX (fmt_65_sc), READ (FMT_65_SC), FULL (snc), FAST (snc) };
-
-DECODE m32rx_decode_illegal = {
-  M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL),
-  EX (illegal), FULL (illegal), FAST (illegal)
+#define FAST(fn)
+#endif
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
+
+/* Instruction semantic handlers and support.
+   This struct defines the part of an IDESC that can be computed at
+   compile time.  */
+
+struct insn_sem {
+  /* The instruction type (a number that identifies each insn over the
+     entire architecture).  */
+  CGEN_INSN_TYPE type;
+
+  /* Index in IDESC table.  */
+  int index;
+
+  /* Index in IDESC table of parallel handler.  */
+  int par_index;
+
+  /* Index in IDESC table of writeback handler.  */
+  int write_index;
+
+  /* Routines to execute the insn.
+     The full version has all features (profiling,tracing) compiled in.
+     The fast version has none of that.  */
+#if ! WITH_SEM_SWITCH_FULL
+  SEMANTIC_FN *sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  SEMANTIC_FN *sem_fast;
+#endif
+
+};
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
+#define IDX(insn) CONCAT2 (M32RXF_,insn)
+#define TYPE(insn) CONCAT2 (M32R_,insn)
+
+/* Insn can't be executed in parallel.
+   Or is that "do NOt Pass to Air defense Radar"? :-) */
+#define NOPAR (-1)
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
+
+static const struct insn_sem m32rxf_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), NOPAR, NOPAR, FULL (x_invalid) FAST (x_invalid) },
+  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), NOPAR, NOPAR, FULL (x_after) FAST (x_after) },
+  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), NOPAR, NOPAR, FULL (x_before) FAST (x_before) },
+  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), NOPAR, NOPAR, FULL (x_cti_chain) FAST (x_cti_chain) },
+  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), NOPAR, NOPAR, FULL (x_chain) FAST (x_chain) },
+  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), NOPAR, NOPAR, FULL (x_begin) FAST (x_begin) },
+  { TYPE (INSN_ADD), IDX (INSN_ADD), IDX (INSN_PAR_ADD), IDX (INSN_WRITE_ADD), FULL (add) FAST (add) },
+  { TYPE (INSN_ADD3), IDX (INSN_ADD3), NOPAR, NOPAR, FULL (add3) FAST (add3) },
+  { TYPE (INSN_AND), IDX (INSN_AND), IDX (INSN_PAR_AND), IDX (INSN_WRITE_AND), FULL (and) FAST (and) },
+  { TYPE (INSN_AND3), IDX (INSN_AND3), NOPAR, NOPAR, FULL (and3) FAST (and3) },
+  { TYPE (INSN_OR), IDX (INSN_OR), IDX (INSN_PAR_OR), IDX (INSN_WRITE_OR), FULL (or) FAST (or) },
+  { TYPE (INSN_OR3), IDX (INSN_OR3), NOPAR, NOPAR, FULL (or3) FAST (or3) },
+  { TYPE (INSN_XOR), IDX (INSN_XOR), IDX (INSN_PAR_XOR), IDX (INSN_WRITE_XOR), FULL (xor) FAST (xor) },
+  { TYPE (INSN_XOR3), IDX (INSN_XOR3), NOPAR, NOPAR, FULL (xor3) FAST (xor3) },
+  { TYPE (INSN_ADDI), IDX (INSN_ADDI), IDX (INSN_PAR_ADDI), IDX (INSN_WRITE_ADDI), FULL (addi) FAST (addi) },
+  { TYPE (INSN_ADDV), IDX (INSN_ADDV), IDX (INSN_PAR_ADDV), IDX (INSN_WRITE_ADDV), FULL (addv) FAST (addv) },
+  { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), NOPAR, NOPAR, FULL (addv3) FAST (addv3) },
+  { TYPE (INSN_ADDX), IDX (INSN_ADDX), IDX (INSN_PAR_ADDX), IDX (INSN_WRITE_ADDX), FULL (addx) FAST (addx) },
+  { TYPE (INSN_BC8), IDX (INSN_BC8), IDX (INSN_PAR_BC8), IDX (INSN_WRITE_BC8), FULL (bc8) FAST (bc8) },
+  { TYPE (INSN_BC24), IDX (INSN_BC24), NOPAR, NOPAR, FULL (bc24) FAST (bc24) },
+  { TYPE (INSN_BEQ), IDX (INSN_BEQ), NOPAR, NOPAR, FULL (beq) FAST (beq) },
+  { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), NOPAR, NOPAR, FULL (beqz) FAST (beqz) },
+  { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), NOPAR, NOPAR, FULL (bgez) FAST (bgez) },
+  { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), NOPAR, NOPAR, FULL (bgtz) FAST (bgtz) },
+  { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), NOPAR, NOPAR, FULL (blez) FAST (blez) },
+  { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), NOPAR, NOPAR, FULL (bltz) FAST (bltz) },
+  { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), NOPAR, NOPAR, FULL (bnez) FAST (bnez) },
+  { TYPE (INSN_BL8), IDX (INSN_BL8), IDX (INSN_PAR_BL8), IDX (INSN_WRITE_BL8), FULL (bl8) FAST (bl8) },
+  { TYPE (INSN_BL24), IDX (INSN_BL24), NOPAR, NOPAR, FULL (bl24) FAST (bl24) },
+  { TYPE (INSN_BCL8), IDX (INSN_BCL8), IDX (INSN_PAR_BCL8), IDX (INSN_WRITE_BCL8), FULL (bcl8) FAST (bcl8) },
+  { TYPE (INSN_BCL24), IDX (INSN_BCL24), NOPAR, NOPAR, FULL (bcl24) FAST (bcl24) },
+  { TYPE (INSN_BNC8), IDX (INSN_BNC8), IDX (INSN_PAR_BNC8), IDX (INSN_WRITE_BNC8), FULL (bnc8) FAST (bnc8) },
+  { TYPE (INSN_BNC24), IDX (INSN_BNC24), NOPAR, NOPAR, FULL (bnc24) FAST (bnc24) },
+  { TYPE (INSN_BNE), IDX (INSN_BNE), NOPAR, NOPAR, FULL (bne) FAST (bne) },
+  { TYPE (INSN_BRA8), IDX (INSN_BRA8), IDX (INSN_PAR_BRA8), IDX (INSN_WRITE_BRA8), FULL (bra8) FAST (bra8) },
+  { TYPE (INSN_BRA24), IDX (INSN_BRA24), NOPAR, NOPAR, FULL (bra24) FAST (bra24) },
+  { TYPE (INSN_BNCL8), IDX (INSN_BNCL8), IDX (INSN_PAR_BNCL8), IDX (INSN_WRITE_BNCL8), FULL (bncl8) FAST (bncl8) },
+  { TYPE (INSN_BNCL24), IDX (INSN_BNCL24), NOPAR, NOPAR, FULL (bncl24) FAST (bncl24) },
+  { TYPE (INSN_CMP), IDX (INSN_CMP), IDX (INSN_PAR_CMP), IDX (INSN_WRITE_CMP), FULL (cmp) FAST (cmp) },
+  { TYPE (INSN_CMPI), IDX (INSN_CMPI), NOPAR, NOPAR, FULL (cmpi) FAST (cmpi) },
+  { TYPE (INSN_CMPU), IDX (INSN_CMPU), IDX (INSN_PAR_CMPU), IDX (INSN_WRITE_CMPU), FULL (cmpu) FAST (cmpu) },
+  { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), NOPAR, NOPAR, FULL (cmpui) FAST (cmpui) },
+  { TYPE (INSN_CMPEQ), IDX (INSN_CMPEQ), IDX (INSN_PAR_CMPEQ), IDX (INSN_WRITE_CMPEQ), FULL (cmpeq) FAST (cmpeq) },
+  { TYPE (INSN_CMPZ), IDX (INSN_CMPZ), IDX (INSN_PAR_CMPZ), IDX (INSN_WRITE_CMPZ), FULL (cmpz) FAST (cmpz) },
+  { TYPE (INSN_DIV), IDX (INSN_DIV), NOPAR, NOPAR, FULL (div) FAST (div) },
+  { TYPE (INSN_DIVU), IDX (INSN_DIVU), NOPAR, NOPAR, FULL (divu) FAST (divu) },
+  { TYPE (INSN_REM), IDX (INSN_REM), NOPAR, NOPAR, FULL (rem) FAST (rem) },
+  { TYPE (INSN_REMU), IDX (INSN_REMU), NOPAR, NOPAR, FULL (remu) FAST (remu) },
+  { TYPE (INSN_DIVH), IDX (INSN_DIVH), NOPAR, NOPAR, FULL (divh) FAST (divh) },
+  { TYPE (INSN_JC), IDX (INSN_JC), IDX (INSN_PAR_JC), IDX (INSN_WRITE_JC), FULL (jc) FAST (jc) },
+  { TYPE (INSN_JNC), IDX (INSN_JNC), IDX (INSN_PAR_JNC), IDX (INSN_WRITE_JNC), FULL (jnc) FAST (jnc) },
+  { TYPE (INSN_JL), IDX (INSN_JL), IDX (INSN_PAR_JL), IDX (INSN_WRITE_JL), FULL (jl) FAST (jl) },
+  { TYPE (INSN_JMP), IDX (INSN_JMP), IDX (INSN_PAR_JMP), IDX (INSN_WRITE_JMP), FULL (jmp) FAST (jmp) },
+  { TYPE (INSN_LD), IDX (INSN_LD), IDX (INSN_PAR_LD), IDX (INSN_WRITE_LD), FULL (ld) FAST (ld) },
+  { TYPE (INSN_LD_D), IDX (INSN_LD_D), NOPAR, NOPAR, FULL (ld_d) FAST (ld_d) },
+  { TYPE (INSN_LDB), IDX (INSN_LDB), IDX (INSN_PAR_LDB), IDX (INSN_WRITE_LDB), FULL (ldb) FAST (ldb) },
+  { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), NOPAR, NOPAR, FULL (ldb_d) FAST (ldb_d) },
+  { TYPE (INSN_LDH), IDX (INSN_LDH), IDX (INSN_PAR_LDH), IDX (INSN_WRITE_LDH), FULL (ldh) FAST (ldh) },
+  { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), NOPAR, NOPAR, FULL (ldh_d) FAST (ldh_d) },
+  { TYPE (INSN_LDUB), IDX (INSN_LDUB), IDX (INSN_PAR_LDUB), IDX (INSN_WRITE_LDUB), FULL (ldub) FAST (ldub) },
+  { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), NOPAR, NOPAR, FULL (ldub_d) FAST (ldub_d) },
+  { TYPE (INSN_LDUH), IDX (INSN_LDUH), IDX (INSN_PAR_LDUH), IDX (INSN_WRITE_LDUH), FULL (lduh) FAST (lduh) },
+  { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), NOPAR, NOPAR, FULL (lduh_d) FAST (lduh_d) },
+  { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), IDX (INSN_PAR_LD_PLUS), IDX (INSN_WRITE_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
+  { TYPE (INSN_LD24), IDX (INSN_LD24), NOPAR, NOPAR, FULL (ld24) FAST (ld24) },
+  { TYPE (INSN_LDI8), IDX (INSN_LDI8), IDX (INSN_PAR_LDI8), IDX (INSN_WRITE_LDI8), FULL (ldi8) FAST (ldi8) },
+  { TYPE (INSN_LDI16), IDX (INSN_LDI16), NOPAR, NOPAR, FULL (ldi16) FAST (ldi16) },
+  { TYPE (INSN_LOCK), IDX (INSN_LOCK), IDX (INSN_PAR_LOCK), IDX (INSN_WRITE_LOCK), FULL (lock) FAST (lock) },
+  { TYPE (INSN_MACHI_A), IDX (INSN_MACHI_A), IDX (INSN_PAR_MACHI_A), IDX (INSN_WRITE_MACHI_A), FULL (machi_a) FAST (machi_a) },
+  { TYPE (INSN_MACLO_A), IDX (INSN_MACLO_A), IDX (INSN_PAR_MACLO_A), IDX (INSN_WRITE_MACLO_A), FULL (maclo_a) FAST (maclo_a) },
+  { TYPE (INSN_MACWHI_A), IDX (INSN_MACWHI_A), IDX (INSN_PAR_MACWHI_A), IDX (INSN_WRITE_MACWHI_A), FULL (macwhi_a) FAST (macwhi_a) },
+  { TYPE (INSN_MACWLO_A), IDX (INSN_MACWLO_A), IDX (INSN_PAR_MACWLO_A), IDX (INSN_WRITE_MACWLO_A), FULL (macwlo_a) FAST (macwlo_a) },
+  { TYPE (INSN_MUL), IDX (INSN_MUL), IDX (INSN_PAR_MUL), IDX (INSN_WRITE_MUL), FULL (mul) FAST (mul) },
+  { TYPE (INSN_MULHI_A), IDX (INSN_MULHI_A), IDX (INSN_PAR_MULHI_A), IDX (INSN_WRITE_MULHI_A), FULL (mulhi_a) FAST (mulhi_a) },
+  { TYPE (INSN_MULLO_A), IDX (INSN_MULLO_A), IDX (INSN_PAR_MULLO_A), IDX (INSN_WRITE_MULLO_A), FULL (mullo_a) FAST (mullo_a) },
+  { TYPE (INSN_MULWHI_A), IDX (INSN_MULWHI_A), IDX (INSN_PAR_MULWHI_A), IDX (INSN_WRITE_MULWHI_A), FULL (mulwhi_a) FAST (mulwhi_a) },
+  { TYPE (INSN_MULWLO_A), IDX (INSN_MULWLO_A), IDX (INSN_PAR_MULWLO_A), IDX (INSN_WRITE_MULWLO_A), FULL (mulwlo_a) FAST (mulwlo_a) },
+  { TYPE (INSN_MV), IDX (INSN_MV), IDX (INSN_PAR_MV), IDX (INSN_WRITE_MV), FULL (mv) FAST (mv) },
+  { TYPE (INSN_MVFACHI_A), IDX (INSN_MVFACHI_A), IDX (INSN_PAR_MVFACHI_A), IDX (INSN_WRITE_MVFACHI_A), FULL (mvfachi_a) FAST (mvfachi_a) },
+  { TYPE (INSN_MVFACLO_A), IDX (INSN_MVFACLO_A), IDX (INSN_PAR_MVFACLO_A), IDX (INSN_WRITE_MVFACLO_A), FULL (mvfaclo_a) FAST (mvfaclo_a) },
+  { TYPE (INSN_MVFACMI_A), IDX (INSN_MVFACMI_A), IDX (INSN_PAR_MVFACMI_A), IDX (INSN_WRITE_MVFACMI_A), FULL (mvfacmi_a) FAST (mvfacmi_a) },
+  { TYPE (INSN_MVFC), IDX (INSN_MVFC), IDX (INSN_PAR_MVFC), IDX (INSN_WRITE_MVFC), FULL (mvfc) FAST (mvfc) },
+  { TYPE (INSN_MVTACHI_A), IDX (INSN_MVTACHI_A), IDX (INSN_PAR_MVTACHI_A), IDX (INSN_WRITE_MVTACHI_A), FULL (mvtachi_a) FAST (mvtachi_a) },
+  { TYPE (INSN_MVTACLO_A), IDX (INSN_MVTACLO_A), IDX (INSN_PAR_MVTACLO_A), IDX (INSN_WRITE_MVTACLO_A), FULL (mvtaclo_a) FAST (mvtaclo_a) },
+  { TYPE (INSN_MVTC), IDX (INSN_MVTC), IDX (INSN_PAR_MVTC), IDX (INSN_WRITE_MVTC), FULL (mvtc) FAST (mvtc) },
+  { TYPE (INSN_NEG), IDX (INSN_NEG), IDX (INSN_PAR_NEG), IDX (INSN_WRITE_NEG), FULL (neg) FAST (neg) },
+  { TYPE (INSN_NOP), IDX (INSN_NOP), IDX (INSN_PAR_NOP), IDX (INSN_WRITE_NOP), FULL (nop) FAST (nop) },
+  { TYPE (INSN_NOT), IDX (INSN_NOT), IDX (INSN_PAR_NOT), IDX (INSN_WRITE_NOT), FULL (not) FAST (not) },
+  { TYPE (INSN_RAC_DSI), IDX (INSN_RAC_DSI), IDX (INSN_PAR_RAC_DSI), IDX (INSN_WRITE_RAC_DSI), FULL (rac_dsi) FAST (rac_dsi) },
+  { TYPE (INSN_RACH_DSI), IDX (INSN_RACH_DSI), IDX (INSN_PAR_RACH_DSI), IDX (INSN_WRITE_RACH_DSI), FULL (rach_dsi) FAST (rach_dsi) },
+  { TYPE (INSN_RTE), IDX (INSN_RTE), IDX (INSN_PAR_RTE), IDX (INSN_WRITE_RTE), FULL (rte) FAST (rte) },
+  { TYPE (INSN_SETH), IDX (INSN_SETH), NOPAR, NOPAR, FULL (seth) FAST (seth) },
+  { TYPE (INSN_SLL), IDX (INSN_SLL), IDX (INSN_PAR_SLL), IDX (INSN_WRITE_SLL), FULL (sll) FAST (sll) },
+  { TYPE (INSN_SLL3), IDX (INSN_SLL3), NOPAR, NOPAR, FULL (sll3) FAST (sll3) },
+  { TYPE (INSN_SLLI), IDX (INSN_SLLI), IDX (INSN_PAR_SLLI), IDX (INSN_WRITE_SLLI), FULL (slli) FAST (slli) },
+  { TYPE (INSN_SRA), IDX (INSN_SRA), IDX (INSN_PAR_SRA), IDX (INSN_WRITE_SRA), FULL (sra) FAST (sra) },
+  { TYPE (INSN_SRA3), IDX (INSN_SRA3), NOPAR, NOPAR, FULL (sra3) FAST (sra3) },
+  { TYPE (INSN_SRAI), IDX (INSN_SRAI), IDX (INSN_PAR_SRAI), IDX (INSN_WRITE_SRAI), FULL (srai) FAST (srai) },
+  { TYPE (INSN_SRL), IDX (INSN_SRL), IDX (INSN_PAR_SRL), IDX (INSN_WRITE_SRL), FULL (srl) FAST (srl) },
+  { TYPE (INSN_SRL3), IDX (INSN_SRL3), NOPAR, NOPAR, FULL (srl3) FAST (srl3) },
+  { TYPE (INSN_SRLI), IDX (INSN_SRLI), IDX (INSN_PAR_SRLI), IDX (INSN_WRITE_SRLI), FULL (srli) FAST (srli) },
+  { TYPE (INSN_ST), IDX (INSN_ST), IDX (INSN_PAR_ST), IDX (INSN_WRITE_ST), FULL (st) FAST (st) },
+  { TYPE (INSN_ST_D), IDX (INSN_ST_D), NOPAR, NOPAR, FULL (st_d) FAST (st_d) },
+  { TYPE (INSN_STB), IDX (INSN_STB), IDX (INSN_PAR_STB), IDX (INSN_WRITE_STB), FULL (stb) FAST (stb) },
+  { TYPE (INSN_STB_D), IDX (INSN_STB_D), NOPAR, NOPAR, FULL (stb_d) FAST (stb_d) },
+  { TYPE (INSN_STH), IDX (INSN_STH), IDX (INSN_PAR_STH), IDX (INSN_WRITE_STH), FULL (sth) FAST (sth) },
+  { TYPE (INSN_STH_D), IDX (INSN_STH_D), NOPAR, NOPAR, FULL (sth_d) FAST (sth_d) },
+  { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), IDX (INSN_PAR_ST_PLUS), IDX (INSN_WRITE_ST_PLUS), FULL (st_plus) FAST (st_plus) },
+  { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), IDX (INSN_PAR_ST_MINUS), IDX (INSN_WRITE_ST_MINUS), FULL (st_minus) FAST (st_minus) },
+  { TYPE (INSN_SUB), IDX (INSN_SUB), IDX (INSN_PAR_SUB), IDX (INSN_WRITE_SUB), FULL (sub) FAST (sub) },
+  { TYPE (INSN_SUBV), IDX (INSN_SUBV), IDX (INSN_PAR_SUBV), IDX (INSN_WRITE_SUBV), FULL (subv) FAST (subv) },
+  { TYPE (INSN_SUBX), IDX (INSN_SUBX), IDX (INSN_PAR_SUBX), IDX (INSN_WRITE_SUBX), FULL (subx) FAST (subx) },
+  { TYPE (INSN_TRAP), IDX (INSN_TRAP), IDX (INSN_PAR_TRAP), IDX (INSN_WRITE_TRAP), FULL (trap) FAST (trap) },
+  { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), IDX (INSN_PAR_UNLOCK), IDX (INSN_WRITE_UNLOCK), FULL (unlock) FAST (unlock) },
+  { TYPE (INSN_SATB), IDX (INSN_SATB), NOPAR, NOPAR, FULL (satb) FAST (satb) },
+  { TYPE (INSN_SATH), IDX (INSN_SATH), NOPAR, NOPAR, FULL (sath) FAST (sath) },
+  { TYPE (INSN_SAT), IDX (INSN_SAT), NOPAR, NOPAR, FULL (sat) FAST (sat) },
+  { TYPE (INSN_PCMPBZ), IDX (INSN_PCMPBZ), IDX (INSN_PAR_PCMPBZ), IDX (INSN_WRITE_PCMPBZ), FULL (pcmpbz) FAST (pcmpbz) },
+  { TYPE (INSN_SADD), IDX (INSN_SADD), IDX (INSN_PAR_SADD), IDX (INSN_WRITE_SADD), FULL (sadd) FAST (sadd) },
+  { TYPE (INSN_MACWU1), IDX (INSN_MACWU1), IDX (INSN_PAR_MACWU1), IDX (INSN_WRITE_MACWU1), FULL (macwu1) FAST (macwu1) },
+  { TYPE (INSN_MSBLO), IDX (INSN_MSBLO), IDX (INSN_PAR_MSBLO), IDX (INSN_WRITE_MSBLO), FULL (msblo) FAST (msblo) },
+  { TYPE (INSN_MULWU1), IDX (INSN_MULWU1), IDX (INSN_PAR_MULWU1), IDX (INSN_WRITE_MULWU1), FULL (mulwu1) FAST (mulwu1) },
+  { TYPE (INSN_MACLH1), IDX (INSN_MACLH1), IDX (INSN_PAR_MACLH1), IDX (INSN_WRITE_MACLH1), FULL (maclh1) FAST (maclh1) },
+  { TYPE (INSN_SC), IDX (INSN_SC), IDX (INSN_PAR_SC), IDX (INSN_WRITE_SC), FULL (sc) FAST (sc) },
+  { TYPE (INSN_SNC), IDX (INSN_SNC), IDX (INSN_PAR_SNC), IDX (INSN_WRITE_SNC), FULL (snc) FAST (snc) },
 };
 
-/* The order must match that of `labels' in sem-switch.c/read.c.  */
-
-DECODE *m32rx_decode_vars[] = {
-  & m32rx_decode_illegal,
-  & decode_add,
-  & decode_add3,
-  & decode_and,
-  & decode_and3,
-  & decode_or,
-  & decode_or3,
-  & decode_xor,
-  & decode_xor3,
-  & decode_addi,
-  & decode_addv,
-  & decode_addv3,
-  & decode_addx,
-  & decode_bc8,
-  & decode_bc24,
-  & decode_beq,
-  & decode_beqz,
-  & decode_bgez,
-  & decode_bgtz,
-  & decode_blez,
-  & decode_bltz,
-  & decode_bnez,
-  & decode_bl8,
-  & decode_bl24,
-  & decode_bcl8,
-  & decode_bcl24,
-  & decode_bnc8,
-  & decode_bnc24,
-  & decode_bne,
-  & decode_bra8,
-  & decode_bra24,
-  & decode_bncl8,
-  & decode_bncl24,
-  & decode_cmp,
-  & decode_cmpi,
-  & decode_cmpu,
-  & decode_cmpui,
-  & decode_cmpeq,
-  & decode_cmpz,
-  & decode_div,
-  & decode_divu,
-  & decode_rem,
-  & decode_remu,
-  & decode_divh,
-  & decode_jc,
-  & decode_jnc,
-  & decode_jl,
-  & decode_jmp,
-  & decode_ld,
-  & decode_ld_d,
-  & decode_ldb,
-  & decode_ldb_d,
-  & decode_ldh,
-  & decode_ldh_d,
-  & decode_ldub,
-  & decode_ldub_d,
-  & decode_lduh,
-  & decode_lduh_d,
-  & decode_ld_plus,
-  & decode_ld24,
-  & decode_ldi8,
-  & decode_ldi16,
-  & decode_lock,
-  & decode_machi_a,
-  & decode_maclo_a,
-  & decode_mul,
-  & decode_mulhi_a,
-  & decode_mullo_a,
-  & decode_mv,
-  & decode_mvfachi_a,
-  & decode_mvfaclo_a,
-  & decode_mvfacmi_a,
-  & decode_mvfc,
-  & decode_mvtachi_a,
-  & decode_mvtaclo_a,
-  & decode_mvtc,
-  & decode_neg,
-  & decode_nop,
-  & decode_not,
-  & decode_rac_dsi,
-  & decode_rach_dsi,
-  & decode_rte,
-  & decode_seth,
-  & decode_sll,
-  & decode_sll3,
-  & decode_slli,
-  & decode_sra,
-  & decode_sra3,
-  & decode_srai,
-  & decode_srl,
-  & decode_srl3,
-  & decode_srli,
-  & decode_st,
-  & decode_st_d,
-  & decode_stb,
-  & decode_stb_d,
-  & decode_sth,
-  & decode_sth_d,
-  & decode_st_plus,
-  & decode_st_minus,
-  & decode_sub,
-  & decode_subv,
-  & decode_subx,
-  & decode_trap,
-  & decode_unlock,
-  & decode_satb,
-  & decode_sath,
-  & decode_sat,
-  & decode_pcmpbz,
-  & decode_sadd,
-  & decode_macwu1,
-  & decode_msblo,
-  & decode_mulwu1,
-  & decode_maclh1,
-  & decode_sc,
-  & decode_snc,
-  0
+static const struct insn_sem m32rxf_insn_sem_invalid =
+{
+  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), IDX (INSN_X_INVALID), 0 /*unused*/, FULL (x_invalid) FAST (x_invalid)
 };
 
+#undef IDX
+#undef TYPE
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
+
+  id->num = t->index;
+  if ((int) t->type <= 0)
+    id->opcode = & cgen_virtual_opcode_table[- t->type];
+  else
+    id->opcode = & opcode_table[t->type];
+#if ! WITH_SEM_SWITCH_FULL
+  id->sem_full = t->sem_full;
+#endif
+#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
+  id->sem_fast = t->sem_fast;
+#endif
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+m32rxf_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = M32RXF_INSN_MAX;
+  IDESC *table = m32rxf_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & m32rxf_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+      if (t->par_index != NOPAR)
+       {
+         init_idesc (cpu, &table[t->par_index], t);
+         table[t->index].par_idesc = &table[t->par_index];
+       }
+      if (t->par_index != NOPAR)
+       {
+         init_idesc (cpu, &table[t->write_index], t);
+         table[t->par_index].par_idesc = &table[t->write_index];
+       }
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Enum declaration for all instruction formats.  */
+typedef enum ifmt {
+  FMT_ADD, FMT_ADD3, FMT_AND3, FMT_OR3
+ , FMT_ADDI, FMT_ADDV, FMT_ADDV3, FMT_ADDX
+ , FMT_BC8, FMT_BC24, FMT_BEQ, FMT_BEQZ
+ , FMT_BL8, FMT_BL24, FMT_BCL8, FMT_BCL24
+ , FMT_BRA8, FMT_BRA24, FMT_CMP, FMT_CMPI
+ , FMT_CMPZ, FMT_DIV, FMT_JC, FMT_JL
+ , FMT_JMP, FMT_LD, FMT_LD_D, FMT_LDB
+ , FMT_LDB_D, FMT_LDH, FMT_LDH_D, FMT_LD_PLUS
+ , FMT_LD24, FMT_LDI8, FMT_LDI16, FMT_LOCK
+ , FMT_MACHI_A, FMT_MULHI_A, FMT_MV, FMT_MVFACHI_A
+ , FMT_MVFC, FMT_MVTACHI_A, FMT_MVTC, FMT_NOP
+ , FMT_RAC_DSI, FMT_RTE, FMT_SETH, FMT_SLL3
+ , FMT_SLLI, FMT_ST, FMT_ST_D, FMT_STB
+ , FMT_STB_D, FMT_STH, FMT_STH_D, FMT_ST_PLUS
+ , FMT_TRAP, FMT_UNLOCK, FMT_SATB, FMT_SAT
+ , FMT_SADD, FMT_MACWU1, FMT_MSBLO, FMT_MULWU1
+ , FMT_SC
+} IFMT;
+
+/* The decoder uses this to record insns and direct extraction handling.  */
+
+typedef struct {
+  const IDESC *idesc;
+#ifdef __GNUC__
+  void *ifmt;
+#else
+  enum ifmt ifmt;
+#endif
+} DECODE_DESC;
+
+/* Macro to go from decode phase to extraction phase.  */
+
+#ifdef __GNUC__
+#define GOTO_EXTRACT(id) goto *(id)->ifmt
+#else
+#define GOTO_EXTRACT(id) goto extract
+#endif
+
 /* The decoder needs a slightly different computed goto switch control.  */
 #ifdef __GNUC__
 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
@@ -323,353 +349,2090 @@ DECODE *m32rx_decode_vars[] = {
 #define DECODE_SWITCH(N, X) switch (X)
 #endif
 
-/* Given an instruction, return a pointer to its DECODE entry.  */
+/* Given an instruction, return a pointer to its IDESC entry.  */
 
-DECODE *
-m32rx_decode (current_cpu, pc, insn)
-     SIM_CPU *current_cpu;
-     PCADDR pc;
-     insn_t insn;
+const IDESC *
+m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
+              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              ARGBUF *abuf)
 {
+  /* Result of decoder, used by extractor.  */
+  const DECODE_DESC *idecode;
+
+  /* First decode the instruction.  */
+
   {
+#define I(insn) & m32rxf_insn_data[CONCAT2 (M32RXF_,insn)]
 #ifdef __GNUC__
-    static void *labels_0[256] = {
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && case_0_7, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_28, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && case_0_87, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && case_0_95, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
-      && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
-      && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
-      && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
-      && case_0_128, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_144, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && default_0, && default_0, && default_0, && default_0, 
-      && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
-      && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
-      && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
-      && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
-    };
-#endif
-    static DECODE *insns[256] = {
-      &decode_subv, &decode_subx, &decode_sub, &decode_neg, 
-      &decode_cmp, &decode_cmpu, &decode_cmpeq, 0, 
-      &decode_addv, &decode_addx, &decode_add, &decode_not, 
-      &decode_and, &decode_xor, &decode_or, &decode_illegal, 
-      &decode_srl, &decode_illegal, &decode_sra, &decode_illegal, 
-      &decode_sll, &decode_illegal, &decode_mul, &decode_illegal, 
-      &decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal, 
-      0, &decode_rte, &decode_illegal, &decode_trap, 
-      &decode_stb, &decode_illegal, &decode_sth, &decode_illegal, 
-      &decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus, 
-      &decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh, 
-      &decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal, 
-      &decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal, 
-      &decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal, 
-      &decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal, 
-      &decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
-      &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
-      &decode_slli, &decode_slli, &decode_illegal, 0, 
-      &decode_rach_dsi, &decode_rac_dsi, &decode_mulwu1, &decode_macwu1, 
-      &decode_maclh1, &decode_msblo, &decode_sadd, 0, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
-      &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
-      &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
-      0, &decode_divu, &decode_rem, &decode_remu, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
-      &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
-      &decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal, 
-      &decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d, 
-      &decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_beq, &decode_bne, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez, 
-      &decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_seth, &decode_illegal, &decode_illegal, &decode_illegal, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      &decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-      0, 0, 0, 0, 
-    };
-    unsigned int val;
-    val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-    DECODE_SWITCH (0, val)
-      {
-      CASE (0, 7) :
-        {
-          static DECODE *insns[16] = {
-            &decode_cmpz, &decode_illegal, &decode_illegal, &decode_pcmpbz, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 28) :
-        {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_jc, &decode_jnc, &decode_jl, &decode_jmp, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 87) :
-        {
-          static DECODE *insns[4] = {
-            &decode_mvtachi_a, &decode_mvtaclo_a, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          return insns[val];
-        }
-      CASE (0, 95) :
-        {
-          static DECODE *insns[4] = {
-            &decode_mvfachi_a, &decode_mvfaclo_a, &decode_mvfacmi_a, &decode_illegal, 
-          };
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          return insns[val];
-        }
-      CASE (0, 112) :
-        {
-          static DECODE *insns[16] = {
-            &decode_nop, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_sc, &decode_snc, &decode_illegal, &decode_illegal, 
-            &decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal, 
-            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 113) : /* fall through */
-      CASE (0, 114) : /* fall through */
-      CASE (0, 115) : /* fall through */
-      CASE (0, 116) : /* fall through */
-      CASE (0, 117) : /* fall through */
-      CASE (0, 118) : /* fall through */
-      CASE (0, 119) : /* fall through */
-      CASE (0, 120) : /* fall through */
-      CASE (0, 121) : /* fall through */
-      CASE (0, 122) : /* fall through */
-      CASE (0, 123) : /* fall through */
-      CASE (0, 124) : /* fall through */
-      CASE (0, 125) : /* fall through */
-      CASE (0, 126) : /* fall through */
-      CASE (0, 127) :
-        {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal, 
-            &decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
-        }
-      CASE (0, 128) :
+#define E(fmt) && case_ex_##fmt
+#else
+#define E(fmt) fmt
+#endif
+    CGEN_INSN_INT insn = base_insn;
+    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
+    {
+#ifdef __GNUC__
+      static const void *labels_0[256] = {
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_7, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_28, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_87, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && case_0_95, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
+        && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
+        && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
+        && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && case_0_134, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_144, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && default_0, && default_0, && default_0, && default_0, 
+        && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
+        && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
+        && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
+        && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
+      };
+#endif
+      static const DECODE_DESC insns[256] = {
+        { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, 
+        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, 
+        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, 
+        { I (INSN_CMPEQ), E (FMT_CMP) }, { 0 }, 
+        { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, 
+        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, 
+        { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, 
+        { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, 
+        { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_RTE), E (FMT_RTE) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, 
+        { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, 
+        { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, 
+        { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, 
+        { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, 
+        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, 
+        { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) }, 
+        { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) }, 
+        { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) }, 
+        { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) }, 
+        { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) }, 
+        { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) }, 
+        { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) }, 
+        { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
+        { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, 
+        { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, 
+        { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
+        { I (INSN_RACH_DSI), E (FMT_RAC_DSI) }, { I (INSN_RAC_DSI), E (FMT_RAC_DSI) }, 
+        { I (INSN_MULWU1), E (FMT_MULWU1) }, { I (INSN_MACWU1), E (FMT_MACWU1) }, 
+        { I (INSN_MACLH1), E (FMT_MACWU1) }, { I (INSN_MSBLO), E (FMT_MSBLO) }, 
+        { I (INSN_SADD), E (FMT_SADD) }, { 0 }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, 
+        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, 
+        { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { 0 }, { I (INSN_DIVU), E (FMT_DIV) }, 
+        { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, 
+        { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, 
+        { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, 
+        { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, 
+        { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, 
+        { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+        { 0 }, { 0 }, 
+      };
+      unsigned int val;
+      val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      DECODE_SWITCH (0, val)
         {
+        CASE (0, 7) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_CMPZ), E (FMT_CMPZ) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_PCMPBZ), E (FMT_CMPZ) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 28) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_JC), E (FMT_JC) }, { I (INSN_JNC), E (FMT_JC) }, 
+              { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 87) :
+          {
+            static const DECODE_DESC insns[4] = {
+              { I (INSN_MVTACHI_A), E (FMT_MVTACHI_A) }, { I (INSN_MVTACLO_A), E (FMT_MVTACHI_A) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 95) :
+          {
+            static const DECODE_DESC insns[4] = {
+              { I (INSN_MVFACHI_A), E (FMT_MVFACHI_A) }, { I (INSN_MVFACLO_A), E (FMT_MVFACHI_A) }, 
+              { I (INSN_MVFACMI_A), E (FMT_MVFACHI_A) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val = (((insn >> 0) & (3 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 112) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_SC), E (FMT_SC) }, { I (INSN_SNC), E (FMT_SC) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
+              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 113) : /* fall through */
+        CASE (0, 114) : /* fall through */
+        CASE (0, 115) : /* fall through */
+        CASE (0, 116) : /* fall through */
+        CASE (0, 117) : /* fall through */
+        CASE (0, 118) : /* fall through */
+        CASE (0, 119) : /* fall through */
+        CASE (0, 120) : /* fall through */
+        CASE (0, 121) : /* fall through */
+        CASE (0, 122) : /* fall through */
+        CASE (0, 123) : /* fall through */
+        CASE (0, 124) : /* fall through */
+        CASE (0, 125) : /* fall through */
+        CASE (0, 126) : /* fall through */
+        CASE (0, 127) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
+              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        CASE (0, 134) :
+          {
 #ifdef __GNUC__
-          static void *labels_0_128[16] = {
-            && case_0_128_0, && default_0_128, && default_0_128, && default_0_128, 
-            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
-            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
-            && default_0_128, && default_0_128, && default_0_128, && default_0_128, 
-          };
-#endif
-          static DECODE *insns[16] = {
-            0, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val;
-          /* Must fetch more bits.  */
-          insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
-          val = (((insn >> 12) & (15 << 0)));
-          DECODE_SWITCH (0_128, val)
-            {
-            CASE (0_128, 0) :
+            static const void *labels_0_134[16] = {
+              && case_0_134_0, && default_0_134, && default_0_134, && default_0_134, 
+              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
+              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
+              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            /* Must fetch more bits.  */
+            insn = GETIMEMUHI (current_cpu, pc + 2);
+            val = (((insn >> 12) & (15 << 0)));
+            DECODE_SWITCH (0_134, val)
               {
-                static DECODE *insns[16] = {
-                  &decode_sat, &decode_satb, &decode_sath, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                };
-                unsigned int val = (((insn >> 8) & (15 << 0)));
-                return insns[val];
+              CASE (0_134, 0) :
+                {
+                  static const DECODE_DESC insns[16] = {
+                    { I (INSN_SAT), E (FMT_SAT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_SATH), E (FMT_SATB) }, { I (INSN_SATB), E (FMT_SATB) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val = (((insn >> 8) & (15 << 0)));
+                  idecode = &insns[val];
+                  GOTO_EXTRACT (idecode);
+                }
+              DEFAULT (0_134) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
               }
-            DEFAULT (0_128) : return insns[val];
-            }
-          ENDSWITCH (0_128)
-        }
-      CASE (0, 144) :
-        {
+            ENDSWITCH (0_134)
+          }
+        CASE (0, 144) :
+          {
 #ifdef __GNUC__
-          static void *labels_0_144[16] = {
-            && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, 
-            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-          };
-#endif
-          static DECODE *insns[16] = {
-            0, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-          };
-          unsigned int val;
-          /* Must fetch more bits.  */
-          insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
-          val = (((insn >> 12) & (15 << 0)));
-          DECODE_SWITCH (0_144, val)
-            {
-            CASE (0_144, 0) :
+            static const void *labels_0_144[16] = {
+              && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, 
+              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+            };
+#endif
+            static const DECODE_DESC insns[16] = {
+              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+            };
+            unsigned int val;
+            /* Must fetch more bits.  */
+            insn = GETIMEMUHI (current_cpu, pc + 2);
+            val = (((insn >> 12) & (15 << 0)));
+            DECODE_SWITCH (0_144, val)
               {
+              CASE (0_144, 0) :
+                {
 #ifdef __GNUC__
-                static void *labels_0_144_0[16] = {
-                  && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                };
-#endif
-                static DECODE *insns[16] = {
-                  0, &decode_illegal, &decode_illegal, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                };
-                unsigned int val;
-                val = (((insn >> 8) & (15 << 0)));
-                DECODE_SWITCH (0_144_0, val)
-                  {
-                  CASE (0_144_0, 0) :
+                  static const void *labels_0_144_0[16] = {
+                    && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  };
+#endif
+                  static const DECODE_DESC insns[16] = {
+                    { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                  };
+                  unsigned int val;
+                  val = (((insn >> 8) & (15 << 0)));
+                  DECODE_SWITCH (0_144_0, val)
                     {
-                      static DECODE *insns[16] = {
-                        &decode_div, &decode_divh, &decode_illegal, &decode_illegal, 
-                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-                      };
-                      unsigned int val = (((insn >> 4) & (15 << 0)));
-                      return insns[val];
+                    CASE (0_144_0, 0) :
+                      {
+                        static const DECODE_DESC insns[16] = {
+                          { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVH), E (FMT_DIV) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+                        };
+                        unsigned int val = (((insn >> 4) & (15 << 0)));
+                        idecode = &insns[val];
+                        GOTO_EXTRACT (idecode);
+                      }
+                    DEFAULT (0_144_0) :
+                      idecode = &insns[val];
+                      GOTO_EXTRACT (idecode);
                     }
-                  DEFAULT (0_144_0) : return insns[val];
-                  }
-                ENDSWITCH (0_144_0)
+                  ENDSWITCH (0_144_0)
+                }
+              DEFAULT (0_144) :
+                idecode = &insns[val];
+                GOTO_EXTRACT (idecode);
               }
-            DEFAULT (0_144) : return insns[val];
-            }
-          ENDSWITCH (0_144)
-        }
-      CASE (0, 240) : /* fall through */
-      CASE (0, 241) : /* fall through */
-      CASE (0, 242) : /* fall through */
-      CASE (0, 243) : /* fall through */
-      CASE (0, 244) : /* fall through */
-      CASE (0, 245) : /* fall through */
-      CASE (0, 246) : /* fall through */
-      CASE (0, 247) : /* fall through */
-      CASE (0, 248) : /* fall through */
-      CASE (0, 249) : /* fall through */
-      CASE (0, 250) : /* fall through */
-      CASE (0, 251) : /* fall through */
-      CASE (0, 252) : /* fall through */
-      CASE (0, 253) : /* fall through */
-      CASE (0, 254) : /* fall through */
-      CASE (0, 255) :
-        {
-          static DECODE *insns[16] = {
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
-            &decode_bcl24, &decode_bncl24, &decode_illegal, &decode_illegal, 
-            &decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24, 
-          };
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          return insns[val];
+            ENDSWITCH (0_144)
+          }
+        CASE (0, 240) : /* fall through */
+        CASE (0, 241) : /* fall through */
+        CASE (0, 242) : /* fall through */
+        CASE (0, 243) : /* fall through */
+        CASE (0, 244) : /* fall through */
+        CASE (0, 245) : /* fall through */
+        CASE (0, 246) : /* fall through */
+        CASE (0, 247) : /* fall through */
+        CASE (0, 248) : /* fall through */
+        CASE (0, 249) : /* fall through */
+        CASE (0, 250) : /* fall through */
+        CASE (0, 251) : /* fall through */
+        CASE (0, 252) : /* fall through */
+        CASE (0, 253) : /* fall through */
+        CASE (0, 254) : /* fall through */
+        CASE (0, 255) :
+          {
+            static const DECODE_DESC insns[16] = {
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BCL24), E (FMT_BCL24) }, { I (INSN_BNCL24), E (FMT_BCL24) }, 
+              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
+              { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, 
+              { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, 
+            };
+            unsigned int val = (((insn >> 8) & (15 << 0)));
+            idecode = &insns[val];
+            GOTO_EXTRACT (idecode);
+          }
+        DEFAULT (0) :
+          idecode = &insns[val];
+          GOTO_EXTRACT (idecode);
         }
-      DEFAULT (0) : return insns[val];
-      }
-    ENDSWITCH (0)
+      ENDSWITCH (0)
+    }
+#undef I
+#undef E
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract:
+  {
+#ifndef __GNUC__
+    switch (idecode->ifmt)
+#endif
+      {
+
+  CASE (ex, FMT_ADD) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_add.f
+  EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADD3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_add3.f
+  EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ADD3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_add3", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_AND3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_and3.f
+  EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_AND3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_uimm16) = f_uimm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_and3", "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_OR3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_or3.f
+  EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_OR3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_uimm16) = f_uimm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_or3", "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addi.f
+  EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_ADDI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (f_simm8) = f_simm8;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addv.f
+  EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADDV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDV3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addv3.f
+  EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ADDV3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addv3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ADDX) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_addx.f
+  EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ADDX_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BC8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BC8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BC24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BC24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BEQ) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_BEQ_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_disp16) = f_disp16;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BEQZ) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_BEQZ_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_disp16) = f_disp16;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BL8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+  EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BL8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BL24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+  EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BL24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BCL8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+  EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BCL8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BCL24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
+  EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BCL24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BRA8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+  EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_BRA8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp8) = f_disp8;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_BRA24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+  EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_BRA24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_disp24) = f_disp24;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_cmp.f
+  EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_CMP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_CMPI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_CMPZ) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_cmpz.f
+  EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_CMPZ_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_cmpz", "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_DIV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_div.f
+  EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_DIV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+  EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_JC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_jc", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JL) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+  EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_JL_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_h_gr_14) = 14;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_JMP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_JMP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld.f
+  EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld_d.f
+  EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LD_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDB) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldb.f
+  EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LDB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDB_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldb_d.f
+  EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDB_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldb_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldh.f
+  EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LDH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDH_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldh_d.f
+  EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDH_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldh_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD_PLUS) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld_plus.f
+  EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LD_PLUS_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+      FLD (out_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LD24) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ld24.f
+  EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
+
+  EXTRACT_FMT_LD24_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm24) = f_uimm24;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI8) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_LDI8_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm8) = f_simm8;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LDI16) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_ldi16.f
+  EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_LDI16_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_LOCK) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_lock.f
+  EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_LOCK_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MACHI_A) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_machi_a.f
+  EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+
+  EXTRACT_FMT_MACHI_A_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_acc) = f_acc;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_machi_a", "acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULHI_A) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+  EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+
+  EXTRACT_FMT_MULHI_A_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_acc) = f_acc;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mulhi_a", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "acc 0x%x", 'x', f_acc, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MV) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mv.f
+  EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MV_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVFACHI_A) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+  EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+
+  EXTRACT_FMT_MVFACHI_A_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvfachi_a", "accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVFC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvfc.f
+  EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVFC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvfc", "scr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVTACHI_A) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+  EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+
+  EXTRACT_FMT_MVTACHI_A_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvtachi_a", "accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MVTC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mvtc.f
+  EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MVTC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_r1) = f_r1;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mvtc", "sr 0x%x", 'x', f_r2, "dcr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_NOP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_nop.f
+  EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_NOP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_nop", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RAC_DSI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+  EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+
+  EXTRACT_FMT_RAC_DSI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (f_imm1) = f_imm1;
+  FLD (f_accd) = f_accd;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_rac_dsi", "accs 0x%x", 'x', f_accs, "imm1 0x%x", 'x', f_imm1, "accd 0x%x", 'x', f_accd, (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_RTE) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+  EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_RTE_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_rte", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SETH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_seth.f
+  EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+
+  EXTRACT_FMT_SETH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hi16) = f_hi16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_seth", "hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SLL3) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sll3.f
+  EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_SLL3_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sll3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SLLI) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_slli.f
+  EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+
+  EXTRACT_FMT_SLLI_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (f_uimm5) = f_uimm5;
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st.f
+  EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ST_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st_d.f
+  EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_ST_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STB) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_stb.f
+  EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_STB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STB_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_stb_d.f
+  EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_STB_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_stb_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STH) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sth.f
+  EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_STH_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_STH_D) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sth_d.f
+  EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_STH_D_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (f_simm16) = f_simm16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sth_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_ST_PLUS) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_st_plus.f
+  EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_ST_PLUS_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+      FLD (out_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_TRAP) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+  EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+
+  EXTRACT_FMT_TRAP_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm4) = f_uimm4;
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_UNLOCK) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_unlock.f
+  EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_UNLOCK_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SATB) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_satb.f
+  EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_SATB_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_satb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SAT) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sat.f
+  EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_SAT_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sat", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SADD) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_sadd.f
+  EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_SADD_CODE
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sadd", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MACWU1) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_macwu1.f
+  EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MACWU1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_macwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MSBLO) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_msblo.f
+  EXTRACT_FMT_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MSBLO_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_msblo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_MULWU1) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_mulwu1.f
+  EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_MULWU1_CODE
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_mulwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+  BREAK (ex);
+  }
+
+  CASE (ex, FMT_SC) :
+  {
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+  EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_SC_CODE
+
+  /* Record the fields for the semantic handler.  */
+  SEM_BRANCH_INIT_EXTRACT (abuf);
+  TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_sc", (char *) 0));
+
+#undef FLD
+  BREAK (ex);
+  }
+
+      CASE (ex, FMT_EMPTY) :
+        BREAK (ex);
+
+      }
+    ENDSWITCH (ex)
+
+    return idecode->idesc;
   }
 }

diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index d3cff9239c57437bfa57048d5b6860dbcf23b206..3cb0f7e2db9321e4240b9a44511d842c642826d2 100644 (file)
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -1,4 +1,4 @@
-/* Simulator instruction semantics for m32rb.
+/* Simulator instruction semantics for m32rbf.
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
@@ -23,7 +23,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #ifdef DEFINE_LABELS
-#undef DEFINE_LABELS
 
   /* The labels have the case they have because the enum of insn types
      is all uppercase and in the non-stdc case the insn symbol is built
@@ -33,122 +32,132 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     int index;
     void *label;
   } labels[] = {
-    { M32RB_XINSN_ILLEGAL, && case_sem_INSN_ILLEGAL },
-    { M32RB_XINSN_ADD, && case_sem_INSN_ADD },
-    { M32RB_XINSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32RB_XINSN_AND, && case_sem_INSN_AND },
-    { M32RB_XINSN_AND3, && case_sem_INSN_AND3 },
-    { M32RB_XINSN_OR, && case_sem_INSN_OR },
-    { M32RB_XINSN_OR3, && case_sem_INSN_OR3 },
-    { M32RB_XINSN_XOR, && case_sem_INSN_XOR },
-    { M32RB_XINSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32RB_XINSN_ADDI, && case_sem_INSN_ADDI },
-    { M32RB_XINSN_ADDV, && case_sem_INSN_ADDV },
-    { M32RB_XINSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32RB_XINSN_ADDX, && case_sem_INSN_ADDX },
-    { M32RB_XINSN_BC8, && case_sem_INSN_BC8 },
-    { M32RB_XINSN_BC24, && case_sem_INSN_BC24 },
-    { M32RB_XINSN_BEQ, && case_sem_INSN_BEQ },
-    { M32RB_XINSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32RB_XINSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32RB_XINSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32RB_XINSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32RB_XINSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32RB_XINSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32RB_XINSN_BL8, && case_sem_INSN_BL8 },
-    { M32RB_XINSN_BL24, && case_sem_INSN_BL24 },
-    { M32RB_XINSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32RB_XINSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32RB_XINSN_BNE, && case_sem_INSN_BNE },
-    { M32RB_XINSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32RB_XINSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32RB_XINSN_CMP, && case_sem_INSN_CMP },
-    { M32RB_XINSN_CMPI, && case_sem_INSN_CMPI },
-    { M32RB_XINSN_CMPU, && case_sem_INSN_CMPU },
-    { M32RB_XINSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32RB_XINSN_DIV, && case_sem_INSN_DIV },
-    { M32RB_XINSN_DIVU, && case_sem_INSN_DIVU },
-    { M32RB_XINSN_REM, && case_sem_INSN_REM },
-    { M32RB_XINSN_REMU, && case_sem_INSN_REMU },
-    { M32RB_XINSN_JL, && case_sem_INSN_JL },
-    { M32RB_XINSN_JMP, && case_sem_INSN_JMP },
-    { M32RB_XINSN_LD, && case_sem_INSN_LD },
-    { M32RB_XINSN_LD_D, && case_sem_INSN_LD_D },
-    { M32RB_XINSN_LDB, && case_sem_INSN_LDB },
-    { M32RB_XINSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32RB_XINSN_LDH, && case_sem_INSN_LDH },
-    { M32RB_XINSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32RB_XINSN_LDUB, && case_sem_INSN_LDUB },
-    { M32RB_XINSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32RB_XINSN_LDUH, && case_sem_INSN_LDUH },
-    { M32RB_XINSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32RB_XINSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32RB_XINSN_LD24, && case_sem_INSN_LD24 },
-    { M32RB_XINSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32RB_XINSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32RB_XINSN_LOCK, && case_sem_INSN_LOCK },
-    { M32RB_XINSN_MACHI, && case_sem_INSN_MACHI },
-    { M32RB_XINSN_MACLO, && case_sem_INSN_MACLO },
-    { M32RB_XINSN_MACWHI, && case_sem_INSN_MACWHI },
-    { M32RB_XINSN_MACWLO, && case_sem_INSN_MACWLO },
-    { M32RB_XINSN_MUL, && case_sem_INSN_MUL },
-    { M32RB_XINSN_MULHI, && case_sem_INSN_MULHI },
-    { M32RB_XINSN_MULLO, && case_sem_INSN_MULLO },
-    { M32RB_XINSN_MULWHI, && case_sem_INSN_MULWHI },
-    { M32RB_XINSN_MULWLO, && case_sem_INSN_MULWLO },
-    { M32RB_XINSN_MV, && case_sem_INSN_MV },
-    { M32RB_XINSN_MVFACHI, && case_sem_INSN_MVFACHI },
-    { M32RB_XINSN_MVFACLO, && case_sem_INSN_MVFACLO },
-    { M32RB_XINSN_MVFACMI, && case_sem_INSN_MVFACMI },
-    { M32RB_XINSN_MVFC, && case_sem_INSN_MVFC },
-    { M32RB_XINSN_MVTACHI, && case_sem_INSN_MVTACHI },
-    { M32RB_XINSN_MVTACLO, && case_sem_INSN_MVTACLO },
-    { M32RB_XINSN_MVTC, && case_sem_INSN_MVTC },
-    { M32RB_XINSN_NEG, && case_sem_INSN_NEG },
-    { M32RB_XINSN_NOP, && case_sem_INSN_NOP },
-    { M32RB_XINSN_NOT, && case_sem_INSN_NOT },
-    { M32RB_XINSN_RAC, && case_sem_INSN_RAC },
-    { M32RB_XINSN_RACH, && case_sem_INSN_RACH },
-    { M32RB_XINSN_RTE, && case_sem_INSN_RTE },
-    { M32RB_XINSN_SETH, && case_sem_INSN_SETH },
-    { M32RB_XINSN_SLL, && case_sem_INSN_SLL },
-    { M32RB_XINSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32RB_XINSN_SLLI, && case_sem_INSN_SLLI },
-    { M32RB_XINSN_SRA, && case_sem_INSN_SRA },
-    { M32RB_XINSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32RB_XINSN_SRAI, && case_sem_INSN_SRAI },
-    { M32RB_XINSN_SRL, && case_sem_INSN_SRL },
-    { M32RB_XINSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32RB_XINSN_SRLI, && case_sem_INSN_SRLI },
-    { M32RB_XINSN_ST, && case_sem_INSN_ST },
-    { M32RB_XINSN_ST_D, && case_sem_INSN_ST_D },
-    { M32RB_XINSN_STB, && case_sem_INSN_STB },
-    { M32RB_XINSN_STB_D, && case_sem_INSN_STB_D },
-    { M32RB_XINSN_STH, && case_sem_INSN_STH },
-    { M32RB_XINSN_STH_D, && case_sem_INSN_STH_D },
-    { M32RB_XINSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32RB_XINSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32RB_XINSN_SUB, && case_sem_INSN_SUB },
-    { M32RB_XINSN_SUBV, && case_sem_INSN_SUBV },
-    { M32RB_XINSN_SUBX, && case_sem_INSN_SUBX },
-    { M32RB_XINSN_TRAP, && case_sem_INSN_TRAP },
-    { M32RB_XINSN_UNLOCK, && case_sem_INSN_UNLOCK },
+    { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+    { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+    { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+    { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+    { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+    { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+    { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
+    { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
+    { M32RBF_INSN_AND, && case_sem_INSN_AND },
+    { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
+    { M32RBF_INSN_OR, && case_sem_INSN_OR },
+    { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
+    { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
+    { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
+    { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
+    { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
+    { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
+    { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
+    { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
+    { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
+    { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
+    { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
+    { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
+    { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
+    { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
+    { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
+    { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
+    { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
+    { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
+    { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
+    { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
+    { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
+    { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
+    { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
+    { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
+    { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
+    { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
+    { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
+    { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
+    { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
+    { M32RBF_INSN_REM, && case_sem_INSN_REM },
+    { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
+    { M32RBF_INSN_JL, && case_sem_INSN_JL },
+    { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
+    { M32RBF_INSN_LD, && case_sem_INSN_LD },
+    { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
+    { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
+    { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
+    { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
+    { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
+    { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
+    { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
+    { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
+    { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
+    { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
+    { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
+    { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
+    { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
+    { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
+    { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
+    { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
+    { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
+    { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
+    { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
+    { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
+    { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
+    { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
+    { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
+    { M32RBF_INSN_MV, && case_sem_INSN_MV },
+    { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
+    { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
+    { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
+    { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
+    { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
+    { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
+    { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
+    { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
+    { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
+    { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
+    { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
+    { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
+    { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
+    { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
+    { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
+    { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
+    { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
+    { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
+    { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
+    { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
+    { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
+    { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
+    { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
+    { M32RBF_INSN_ST, && case_sem_INSN_ST },
+    { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
+    { M32RBF_INSN_STB, && case_sem_INSN_STB },
+    { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
+    { M32RBF_INSN_STH, && case_sem_INSN_STH },
+    { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
+    { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
+    { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
+    { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
+    { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
+    { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
+    { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
+    { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
     { 0, 0 }
   };
   int i;
 
   for (i = 0; labels[i].label != 0; ++i)
+#if FAST_P
     CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
 
+#undef DEFINE_LABELS
 #endif /* DEFINE_LABELS */
 
 #ifdef DEFINE_SWITCH
-#undef DEFINE_SWITCH
 
 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
    off frills like tracing and profiling.  */
 /* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  */
+   that can cause it to be optimized out.  Another way would be to emit
+   special handlers into the instruction "stream".  */
 
 #if FAST_P
 #undef TRACE_RESULT
@@ -159,171 +168,357 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
 
 {
-  SEM_ARG sem_arg = sc;
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc;
 
-  SWITCH (sem, sem_arg->semantic.sem_case)
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop.  */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
     {
 
-  CASE (sem, INSN_ILLEGAL) :
+  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    m32rbf_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    m32rbf_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
+                              pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
+                              CPU_PBB_BR_NPC_PTR (current_cpu),
+                              CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 {
-  sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, NULL_CIA/*FIXME*/,
-                  sim_stopped, SIM_SIGILL);
-  BREAK (sem);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+#undef FLD
 }
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
 
   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ADDSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ADDSI (* FLD (f_r2), FLD (f_simm16));
-    * FLD (f_r1) = opval;
+    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_AND) : /* and $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_and3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ANDSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_OR) : /* or $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ORSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_or3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ORSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = XORSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_and3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = XORSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ADDSI (* FLD (f_r1), FLD (f_simm8));
-    * FLD (f_r1) = opval;
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addv.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
-  temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
@@ -331,24 +526,28 @@ do {
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addv3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0);
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
+  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
@@ -356,24 +555,28 @@ do {
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addx.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+  BI temp1;SI temp0;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
@@ -381,1392 +584,1798 @@ do {
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BC8) : /* bc.s $disp8 */
 {
-#define FLD(f) abuf->fields.fmt_bc8.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 if (CPU (h_cond)) {
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BC24) : /* bc.l $disp24 */
 {
-#define FLD(f) abuf->fields.fmt_bc24.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 if (CPU (h_cond)) {
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beq.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
+if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (EQSI (* FLD (f_r2), 0)) {
+if (EQSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (GESI (* FLD (f_r2), 0)) {
+if (GESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (GTSI (* FLD (f_r2), 0)) {
+if (GTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (LESI (* FLD (f_r2), 0)) {
+if (LESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (LTSI (* FLD (f_r2), 0)) {
+if (LTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BL8) : /* bl.s $disp8 */
 {
-#define FLD(f) abuf->fields.fmt_bl8.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    SI opval = ADDSI (ANDSI (CPU (h_pc), -4), 4);
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BL24) : /* bl.l $disp24 */
 {
-#define FLD(f) abuf->fields.fmt_bl24.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 do {
   {
-    SI opval = ADDSI (CPU (h_pc), 4);
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
 {
-#define FLD(f) abuf->fields.fmt_bc8.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
 {
-#define FLD(f) abuf->fields.fmt_bc24.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 {
-#define FLD(f) abuf->fields.fmt_beq.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r1), * FLD (f_r2))) {
+if (NESI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
+  abuf->written = written;
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
 {
-#define FLD(f) abuf->fields.fmt_bra8.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
 {
-#define FLD(f) abuf->fields.fmt_bra24.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_cmp.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    UBI opval = LTSI (* FLD (f_r1), * FLD (f_r2));
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_cmpi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    UBI opval = LTSI (* FLD (f_r2), FLD (f_simm16));
+    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_cmp.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    UBI opval = LTUSI (* FLD (f_r1), * FLD (f_r2));
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_cmpi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    UBI opval = LTUSI (* FLD (f_r2), FLD (f_simm16));
+    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_DIV) : /* div $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_div.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = DIVSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
+  abuf->written = written;
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_div.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = UDIVSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
+  abuf->written = written;
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_REM) : /* rem $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_div.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = MODSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
+  abuf->written = written;
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_div.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = UMODSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
+  abuf->written = written;
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_JL) : /* jl $sr */
 {
-#define FLD(f) abuf->fields.fmt_jl.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
-  temp1 = ANDSI (* FLD (f_r2), -4);
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
   {
     SI opval = temp0;
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = temp1;
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_JMP) : /* jmp $sr */
 {
-#define FLD(f) abuf->fields.fmt_jmp.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    USI opval = ANDSI (* FLD (f_r2), -4);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ld.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = GETMEMSI (current_cpu, * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ld_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldb.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldb_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldh.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldh_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldb.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldb_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldh.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldh_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ld_plus.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
-  temp1 = ADDSI (* FLD (f_r2), 4);
+  temp0 = GETMEMSI (current_cpu, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
     SI opval = temp1;
-    * FLD (f_r2) = opval;
+    * FLD (i_sr) = opval;
     TRACE_RESULT (current_cpu, "sr", 'x', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ld24.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = FLD (f_uimm24);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldi8.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
     SI opval = FLD (f_simm8);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_ldi16.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = FLD (f_simm16);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_lock.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    UBI opval = 1;
+    BI opval = 1;
     CPU (h_lock) = opval;
     TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
   }
   {
-    SI opval = GETMEMSI (current_cpu, * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_machi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_machi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_machi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_machi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = MULSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mulhi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mulhi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mulhi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mulhi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MV) : /* mv $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mv.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = * FLD (f_r2);
-    * FLD (f_r1) = opval;
+    SI opval = * FLD (i_sr);
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvfachi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (SRADI (m32rb_h_accum_get (current_cpu), 32));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 32));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvfachi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (m32rb_h_accum_get (current_cpu));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (m32rbf_h_accum_get (current_cpu));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvfachi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (SRADI (m32rb_h_accum_get (current_cpu), 16));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvfc.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = m32rb_h_cr_get (current_cpu, FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = m32rbf_h_cr_get (current_cpu, FLD (f_r2));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvtachi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = ORDI (ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvtachi.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = ORDI (ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (f_r1)));
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mvtc.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    USI opval = * FLD (f_r2);
-    m32rb_h_cr_set (current_cpu, FLD (f_r1), opval);
+    USI opval = * FLD (i_sr);
+    m32rbf_h_cr_set (current_cpu, FLD (f_r1), opval);
     TRACE_RESULT (current_cpu, "dcr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mv.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = NEGSI (* FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = NEGSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_NOP) : /* nop */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_nop.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_NOT) : /* not $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_mv.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = INVSI (* FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = INVSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_RAC) : /* rac */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_rac.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (m32rb_h_accum_get (current_cpu), 1);
+  tmp_tmp1 = SLLDI (m32rbf_h_accum_get (current_cpu), 1);
   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
   {
     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    m32rb_h_accum_set (current_cpu, opval);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_RACH) : /* rach */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_rac.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
+  tmp_tmp1 = ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
   tmp_tmp1 = MAKEDI (16383, 0x80000000);
 } else {
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
   tmp_tmp1 = MAKEDI (16760832, 0);
 } else {
-  tmp_tmp1 = ANDDI (ADDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
+  tmp_tmp1 = ANDDI (ADDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
 }
 }
   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
   {
     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    m32rb_h_accum_set (current_cpu, opval);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_RTE) : /* rte */
 {
-#define FLD(f) abuf->fields.fmt_rte.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    UBI opval = CPU (h_bsm);
-    CPU (h_sm) = opval;
-    TRACE_RESULT (current_cpu, "sm-0", 'x', opval);
+    USI opval = ANDSI (m32rbf_h_cr_get (current_cpu, ((UINT) 6)), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
   {
-    UBI opval = CPU (h_bie);
-    CPU (h_ie) = opval;
-    TRACE_RESULT (current_cpu, "ie-0", 'x', opval);
+    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 14));
+    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
   }
   {
-    UBI opval = CPU (h_bcond);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+    UQI opval = CPU (h_bpsw);
+    m32rbf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
   }
   {
-    USI opval = ANDSI (CPU (h_bpc), -4);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
-    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+    UQI opval = CPU (h_bbpsw);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
   }
 } while (0);
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_seth.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_sll3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_slli.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SLLSI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_sll3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_slli.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRASI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_sll3.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_slli.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRLSI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_st.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, * FLD (f_r2), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_st_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_stb.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    QI opval = * FLD (f_r1);
-    SETMEMQI (current_cpu, * FLD (f_r2), opval);
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_stb_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = * FLD (f_r1);
-    SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_sth.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    HI opval = * FLD (f_r1);
-    SETMEMHI (current_cpu, * FLD (f_r2), opval);
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_sth_d.f
-  new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    HI opval = * FLD (f_r1);
-    SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_st_plus.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (f_r2), 4);
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
   {
-    SI opval = * FLD (f_r1);
+    SI opval = * FLD (i_src1);
     SETMEMSI (current_cpu, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
   {
     SI opval = tmp_new_src2;
-    * FLD (f_r2) = opval;
+    * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, "src2", 'x', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_st_plus.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (f_r2), 4);
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
   {
-    SI opval = * FLD (f_r1);
+    SI opval = * FLD (i_src1);
     SETMEMSI (current_cpu, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
   {
     SI opval = tmp_new_src2;
-    * FLD (f_r2) = opval;
+    * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, "src2", 'x', opval);
   }
 } while (0);
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_add.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SUBSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addv.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
-  temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+  BI temp1;SI temp0;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
@@ -1774,24 +2383,28 @@ do {
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_addx.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+  BI temp1;SI temp0;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
@@ -1799,64 +2412,92 @@ do {
 
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_TRAP) : /* trap $uimm4 */
 {
-#define FLD(f) abuf->fields.fmt_trap.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    USI opval = ADDSI (CPU (h_pc), 4);
-    m32rb_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
+    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 6));
+    m32rbf_h_cr_set (current_cpu, ((UINT) 14), opval);
+    TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
     TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
   }
   {
-    USI opval = ANDSI (SLLSI (m32rb_h_cr_get (current_cpu, ((HOSTUINT) 0)), 8), 65408);
-    m32rb_h_cr_set (current_cpu, ((HOSTUINT) 0), opval);
-    TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
+    UQI opval = CPU (h_bpsw);
+    CPU (h_bbpsw) = opval;
+    TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
   }
   {
-    SI opval = m32r_trap (current_cpu, CPU (h_pc), FLD (f_uimm4));
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
+    UQI opval = m32rbf_h_psw_get (current_cpu);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (m32rbf_h_psw_get (current_cpu), 128);
+    m32rbf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
+  SEM_BRANCH_FINI
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
 {
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 #define FLD(f) abuf->fields.fmt_unlock.f
-  new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
 if (CPU (h_lock)) {
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, * FLD (f_r2), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 }
   {
-    UBI opval = 0;
+    BI opval = 0;
     CPU (h_lock) = opval;
     TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
   }
 } while (0);
 
+  abuf->written = written;
 #undef FLD
 }
-  BREAK (sem);
+  NEXT (vpc);
 
 
     }
   ENDSWITCH (sem) /* End of semantic switch.  */
 
-  PC = new_pc;
+  /* At this point `vpc' contains the next insn to execute.  */
 }
 
+#undef DEFINE_SWITCH
 #endif /* DEFINE_SWITCH */

diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 0251a80bf6aba75ddce050a60aa54389c191248e..a08c88e555c959d69444743e9f01e16e7bc6115a 100644 (file)
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -1,4 +1,4 @@
-/* Simulator instruction semantics for m32rb.
+/* Simulator instruction semantics for m32rbf.
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
@@ -23,3164 +23,2522 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #define WANT_CPU
-#define WANT_CPU_M32RB
+#define WANT_CPU_M32RBF
 
 #include "sim-main.h"
 #include "cgen-mem.h"
 #include "cgen-ops.h"
-#include "cpu-sim.h"
-
-#if WITH_SCACHE
 
 #undef GET_ATTR
 #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
 
-/* add: add $dr,$sr.  */
+/* x-invalid: --invalid-- */
 
-CIA
-SEM_FN_NAME (m32rb,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
   {
-    SI opval = ADDSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
-    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+SEM_PC
+SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
+  {
+#if WITH_SCACHE_PBB
+    m32rbf_pbb_after (current_cpu, sem_arg);
 #endif
+  }
 
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* add3: add3 $dr,$sr,$hash$slo16.  */
+/* x-before: --before-- */
 
-CIA
-SEM_FN_NAME (m32rb,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
   {
-    SI opval = ADDSI (* FLD (f_r2), FLD (f_simm16));
-    * FLD (f_r1) = opval;
-    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+#if WITH_SCACHE_PBB
+    m32rbf_pbb_before (current_cpu, sem_arg);
+#endif
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+SEM_PC
+SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
+                              pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
+                              CPU_PBB_BR_NPC_PTR (current_cpu),
+                              CPU_PBB_BR_NPC (current_cpu));
 #endif
+#endif
+  }
 
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* and: and $dr,$sr.  */
+/* x-chain: --chain-- */
 
-CIA
-SEM_FN_NAME (m32rb,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
   {
-    SI opval = ANDSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
-    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+#if WITH_SCACHE_PBB
+    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+SEM_PC
+SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
 #endif
+  }
 
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* and3: and3 $dr,$sr,$uimm16.  */
+/* add: add $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
+/* add3: add3 $dr,$sr,$hash$slo16 */
 
-  return new_pc;
+SEM_PC
+SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_add3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+  return vpc;
 #undef FLD
 }
 
-/* or: or $dr,$sr.  */
+/* and: and $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ORSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
+
+/* and3: and3 $dr,$sr,$uimm16 */
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
+SEM_PC
+SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_and3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-  return new_pc;
+  {
+    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+  return vpc;
 #undef FLD
 }
 
-/* or3: or3 $dr,$sr,$hash$ulo16.  */
+/* or: or $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ORSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
+  return vpc;
+#undef FLD
+}
 
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
+/* or3: or3 $dr,$sr,$hash$ulo16 */
+
+SEM_PC
+SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_or3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
 
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* xor: xor $dr,$sr.  */
+/* xor: xor $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = XORSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* xor3: xor3 $dr,$sr,$uimm16.  */
+/* xor3: xor3 $dr,$sr,$uimm16 */
 
-CIA
-SEM_FN_NAME (m32rb,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = XORSI (* FLD (f_r2), FLD (f_uimm16));
-    * FLD (f_r1) = opval;
+    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* addi: addi $dr,$simm8.  */
+/* addi: addi $dr,$simm8 */
 
-CIA
-SEM_FN_NAME (m32rb,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ADDSI (* FLD (f_r1), FLD (f_simm8));
-    * FLD (f_r1) = opval;
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* addv: addv $dr,$sr.  */
+/* addv: addv $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
-  temp1 = ADDOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* addv3: addv3 $dr,$sr,$simm16.  */
+/* addv3: addv3 $dr,$sr,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addv3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (f_r2), FLD (f_simm16), 0);
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
+  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* addx: addx $dr,$sr.  */
+/* addx: addx $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+  BI temp1;SI temp0;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* bc8: bc.s $disp8.  */
+/* bc8: bc.s $disp8 */
 
-CIA
-SEM_FN_NAME (m32rb,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bc8.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 if (CPU (h_cond)) {
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bc24: bc.l $disp24.  */
+/* bc24: bc.l $disp24 */
 
-CIA
-SEM_FN_NAME (m32rb,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bc24.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 if (CPU (h_cond)) {
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* beq: beq $src1,$src2,$disp16.  */
+/* beq: beq $src1,$src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beq.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
+if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* beqz: beqz $src2,$disp16.  */
+/* beqz: beqz $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (EQSI (* FLD (f_r2), 0)) {
+if (EQSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bgez: bgez $src2,$disp16.  */
+/* bgez: bgez $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (GESI (* FLD (f_r2), 0)) {
+if (GESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bgtz: bgtz $src2,$disp16.  */
+/* bgtz: bgtz $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (GTSI (* FLD (f_r2), 0)) {
+if (GTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* blez: blez $src2,$disp16.  */
+/* blez: blez $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (LESI (* FLD (f_r2), 0)) {
+if (LESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bltz: bltz $src2,$disp16.  */
+/* bltz: bltz $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (LTSI (* FLD (f_r2), 0)) {
+if (LTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bnez: bnez $src2,$disp16.  */
+/* bnez: bnez $src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beqz.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bl8: bl.s $disp8.  */
+/* bl8: bl.s $disp8 */
 
-CIA
-SEM_FN_NAME (m32rb,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bl8.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    SI opval = ADDSI (ANDSI (CPU (h_pc), -4), 4);
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bl24: bl.l $disp24.  */
+/* bl24: bl.l $disp24 */
 
-CIA
-SEM_FN_NAME (m32rb,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bl24.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 do {
   {
-    SI opval = ADDSI (CPU (h_pc), 4);
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bnc8: bnc.s $disp8.  */
+/* bnc8: bnc.s $disp8 */
 
-CIA
-SEM_FN_NAME (m32rb,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bc8.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bnc24: bnc.l $disp24.  */
+/* bnc24: bnc.l $disp24 */
 
-CIA
-SEM_FN_NAME (m32rb,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bc24.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bne: bne $src1,$src2,$disp16.  */
+/* bne: bne $src1,$src2,$disp16 */
 
-CIA
-SEM_FN_NAME (m32rb,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_beq.f
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r1), * FLD (f_r2))) {
+if (NESI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (f_disp16);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bra8: bra.s $disp8.  */
+/* bra8: bra.s $disp8 */
 
-CIA
-SEM_FN_NAME (m32rb,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bra8.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
     USI opval = FLD (f_disp8);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* bra24: bra.l $disp24.  */
+/* bra24: bra.l $disp24 */
 
-CIA
-SEM_FN_NAME (m32rb,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_bra24.f
+#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     USI opval = FLD (f_disp24);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* cmp: cmp $src1,$src2.  */
+/* cmp: cmp $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    UBI opval = LTSI (* FLD (f_r1), * FLD (f_r2));
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* cmpi: cmpi $src2,$simm16.  */
+/* cmpi: cmpi $src2,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_cmpi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    UBI opval = LTSI (* FLD (f_r2), FLD (f_simm16));
+    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* cmpu: cmpu $src1,$src2.  */
+/* cmpu: cmpu $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_cmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    UBI opval = LTUSI (* FLD (f_r1), * FLD (f_r2));
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* cmpui: cmpui $src2,$simm16.  */
+/* cmpui: cmpui $src2,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_cmpi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    UBI opval = LTUSI (* FLD (f_r2), FLD (f_simm16));
+    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* div: div $dr,$sr.  */
+/* div: div $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = DIVSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  return vpc;
 #undef FLD
 }
 
-/* divu: divu $dr,$sr.  */
+/* divu: divu $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = UDIVSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  return vpc;
 #undef FLD
 }
 
-/* rem: rem $dr,$sr.  */
+/* rem: rem $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = MODSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  return vpc;
 #undef FLD
 }
 
-/* remu: remu $dr,$sr.  */
+/* remu: remu $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_div.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if (NESI (* FLD (f_r2), 0)) {
+if (NESI (* FLD (i_sr), 0)) {
   {
-    SI opval = UMODSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  return vpc;
 #undef FLD
 }
 
-/* jl: jl $sr.  */
+/* jl: jl $sr */
 
-CIA
-SEM_FN_NAME (m32rb,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_jl.f
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
-  temp1 = ANDSI (* FLD (f_r2), -4);
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
   {
     SI opval = temp0;
-    CPU (h_gr[((HOSTUINT) 14)]) = opval;
+    CPU (h_gr[((UINT) 14)]) = opval;
     TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
   }
   {
     USI opval = temp1;
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
-    taken_p = 1;
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* jmp: jmp $sr.  */
+/* jmp: jmp $sr */
 
-CIA
-SEM_FN_NAME (m32rb,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_jmp.f
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    USI opval = ANDSI (* FLD (f_r2), -4);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
-    taken_p = 1;
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* ld: ld $dr,@$sr.  */
+/* ld: ld $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ld.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = GETMEMSI (current_cpu, * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ld-d: ld $dr,@($slo16,$sr).  */
+/* ld-d: ld $dr,@($slo16,$sr) */
 
-CIA
-SEM_FN_NAME (m32rb,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ld_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldb: ldb $dr,@$sr.  */
+/* ldb: ldb $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldb-d: ldb $dr,@($slo16,$sr).  */
+/* ldb-d: ldb $dr,@($slo16,$sr) */
 
-CIA
-SEM_FN_NAME (m32rb,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldh: ldh $dr,@$sr.  */
+/* ldh: ldh $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldh-d: ldh $dr,@($slo16,$sr).  */
+/* ldh-d: ldh $dr,@($slo16,$sr) */
 
-CIA
-SEM_FN_NAME (m32rb,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldub: ldub $dr,@$sr.  */
+/* ldub: ldub $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldub-d: ldub $dr,@($slo16,$sr).  */
+/* ldub-d: ldub $dr,@($slo16,$sr) */
 
-CIA
-SEM_FN_NAME (m32rb,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* lduh: lduh $dr,@$sr.  */
+/* lduh: lduh $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldh.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* lduh-d: lduh $dr,@($slo16,$sr).  */
+/* lduh-d: lduh $dr,@($slo16,$sr) */
 
-CIA
-SEM_FN_NAME (m32rb,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldh_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
-    * FLD (f_r1) = opval;
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ld-plus: ld $dr,@$sr+.  */
+/* ld-plus: ld $dr,@$sr+ */
 
-CIA
-SEM_FN_NAME (m32rb,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
-  temp1 = ADDSI (* FLD (f_r2), 4);
+  temp0 = GETMEMSI (current_cpu, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
     SI opval = temp1;
-    * FLD (f_r2) = opval;
+    * FLD (i_sr) = opval;
     TRACE_RESULT (current_cpu, "sr", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ld24: ld24 $dr,$uimm24.  */
+/* ld24: ld24 $dr,$uimm24 */
 
-CIA
-SEM_FN_NAME (m32rb,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ld24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = FLD (f_uimm24);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldi8: ldi8 $dr,$simm8.  */
+/* ldi8: ldi8 $dr,$simm8 */
 
-CIA
-SEM_FN_NAME (m32rb,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldi8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
     SI opval = FLD (f_simm8);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* ldi16: ldi16 $dr,$hash$slo16.  */
+/* ldi16: ldi16 $dr,$hash$slo16 */
 
-CIA
-SEM_FN_NAME (m32rb,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_ldi16.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = FLD (f_simm16);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* lock: lock $dr,@$sr.  */
+/* lock: lock $dr,@$sr */
 
-CIA
-SEM_FN_NAME (m32rb,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_lock.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    UBI opval = 1;
+    BI opval = 1;
     CPU (h_lock) = opval;
     TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
   }
   {
-    SI opval = GETMEMSI (current_cpu, * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* machi: machi $src1,$src2.  */
+/* machi: machi $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* maclo: maclo $src1,$src2.  */
+/* maclo: maclo $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* macwhi: macwhi $src1,$src2.  */
+/* macwhi: macwhi $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* macwlo: macwlo $src1,$src2.  */
+/* macwlo: macwlo $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_machi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (ADDDI (m32rb_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mul: mul $dr,$sr.  */
+/* mul: mul $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = MULSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mulhi: mulhi $src1,$src2.  */
+/* mulhi: mulhi $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mulhi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mullo: mullo $src1,$src2.  */
+/* mullo: mullo $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mulhi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mulwhi: mulwhi $src1,$src2.  */
+/* mulwhi: mulwhi $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mulhi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mulwlo: mulwlo $src1,$src2.  */
+/* mulwlo: mulwlo $src1,$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mulhi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mv: mv $dr,$sr.  */
+/* mv: mv $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = * FLD (f_r2);
-    * FLD (f_r1) = opval;
+    SI opval = * FLD (i_sr);
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvfachi: mvfachi $dr.  */
+/* mvfachi: mvfachi $dr */
 
-CIA
-SEM_FN_NAME (m32rb,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (SRADI (m32rb_h_accum_get (current_cpu), 32));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 32));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvfaclo: mvfaclo $dr.  */
+/* mvfaclo: mvfaclo $dr */
 
-CIA
-SEM_FN_NAME (m32rb,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (m32rb_h_accum_get (current_cpu));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (m32rbf_h_accum_get (current_cpu));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvfacmi: mvfacmi $dr.  */
+/* mvfacmi: mvfacmi $dr */
 
-CIA
-SEM_FN_NAME (m32rb,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvfachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = TRUNCDISI (SRADI (m32rb_h_accum_get (current_cpu), 16));
-    * FLD (f_r1) = opval;
+    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 16));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvfc: mvfc $dr,$scr.  */
+/* mvfc: mvfc $dr,$scr */
 
-CIA
-SEM_FN_NAME (m32rb,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvfc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = m32rb_h_cr_get (current_cpu, FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = m32rbf_h_cr_get (current_cpu, FLD (f_r2));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvtachi: mvtachi $src1.  */
+/* mvtachi: mvtachi $src1 */
 
-CIA
-SEM_FN_NAME (m32rb,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvtachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = ORDI (ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvtaclo: mvtaclo $src1.  */
+/* mvtaclo: mvtaclo $src1 */
 
-CIA
-SEM_FN_NAME (m32rb,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvtachi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    DI opval = ORDI (ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (f_r1)));
-    m32rb_h_accum_set (current_cpu, opval);
+    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* mvtc: mvtc $sr,$dcr.  */
+/* mvtc: mvtc $sr,$dcr */
 
-CIA
-SEM_FN_NAME (m32rb,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mvtc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    USI opval = * FLD (f_r2);
-    m32rb_h_cr_set (current_cpu, FLD (f_r1), opval);
+    USI opval = * FLD (i_sr);
+    m32rbf_h_cr_set (current_cpu, FLD (f_r1), opval);
     TRACE_RESULT (current_cpu, "dcr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* neg: neg $dr,$sr.  */
+/* neg: neg $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = NEGSI (* FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = NEGSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* nop: nop.  */
+/* nop: nop */
 
-CIA
-SEM_FN_NAME (m32rb,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_nop.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* not: not $dr,$sr.  */
+/* not: not $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_mv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = INVSI (* FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = INVSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* rac: rac.  */
+/* rac: rac */
 
-CIA
-SEM_FN_NAME (m32rb,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_rac.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (m32rb_h_accum_get (current_cpu), 1);
+  tmp_tmp1 = SLLDI (m32rbf_h_accum_get (current_cpu), 1);
   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
   {
     DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    m32rb_h_accum_set (current_cpu, opval);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* rach: rach.  */
+/* rach: rach */
 
-CIA
-SEM_FN_NAME (m32rb,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_rac.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (m32rb_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
+  tmp_tmp1 = ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
   tmp_tmp1 = MAKEDI (16383, 0x80000000);
 } else {
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
   tmp_tmp1 = MAKEDI (16760832, 0);
 } else {
-  tmp_tmp1 = ANDDI (ADDDI (m32rb_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
+  tmp_tmp1 = ANDDI (ADDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
 }
 }
   tmp_tmp1 = SLLDI (tmp_tmp1, 1);
   {
     DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    m32rb_h_accum_set (current_cpu, opval);
+    m32rbf_h_accum_set (current_cpu, opval);
     TRACE_RESULT (current_cpu, "accum", 'D', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* rte: rte.  */
+/* rte: rte */
 
-CIA
-SEM_FN_NAME (m32rb,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rte.f
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    UBI opval = CPU (h_bsm);
-    CPU (h_sm) = opval;
-    TRACE_RESULT (current_cpu, "sm-0", 'x', opval);
+    USI opval = ANDSI (m32rbf_h_cr_get (current_cpu, ((UINT) 6)), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
   {
-    UBI opval = CPU (h_bie);
-    CPU (h_ie) = opval;
-    TRACE_RESULT (current_cpu, "ie-0", 'x', opval);
+    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 14));
+    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
   }
   {
-    UBI opval = CPU (h_bcond);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+    UQI opval = CPU (h_bpsw);
+    m32rbf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
   }
   {
-    USI opval = ANDSI (CPU (h_bpc), -4);
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
-    taken_p = 1;
-    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+    UQI opval = CPU (h_bbpsw);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* seth: seth $dr,$hash$hi16.  */
+/* seth: seth $dr,$hash$hi16 */
 
-CIA
-SEM_FN_NAME (m32rb,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
     SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sll: sll $dr,$sr.  */
+/* sll: sll $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sll3: sll3 $dr,$sr,$simm16.  */
+/* sll3: sll3 $dr,$sr,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_sll3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* slli: slli $dr,$uimm5.  */
+/* slli: slli $dr,$uimm5 */
 
-CIA
-SEM_FN_NAME (m32rb,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SLLSI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sra: sra $dr,$sr.  */
+/* sra: sra $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sra3: sra3 $dr,$sr,$simm16.  */
+/* sra3: sra3 $dr,$sr,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_sll3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* srai: srai $dr,$uimm5.  */
+/* srai: srai $dr,$uimm5 */
 
-CIA
-SEM_FN_NAME (m32rb,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRASI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* srl: srl $dr,$sr.  */
+/* srl: srl $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* srl3: srl3 $dr,$sr,$simm16.  */
+/* srl3: srl3 $dr,$sr,$simm16 */
 
-CIA
-SEM_FN_NAME (m32rb,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_sll3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* srli: srli $dr,$uimm5.  */
+/* srli: srli $dr,$uimm5 */
 
-CIA
-SEM_FN_NAME (m32rb,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SRLSI (* FLD (f_r1), FLD (f_uimm5));
-    * FLD (f_r1) = opval;
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* st: st $src1,@$src2.  */
+/* st: st $src1,@$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_st.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, * FLD (f_r2), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* st-d: st $src1,@($slo16,$src2).  */
+/* st-d: st $src1,@($slo16,$src2) */
 
-CIA
-SEM_FN_NAME (m32rb,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* stb: stb $src1,@$src2.  */
+/* stb: stb $src1,@$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_stb.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    QI opval = * FLD (f_r1);
-    SETMEMQI (current_cpu, * FLD (f_r2), opval);
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* stb-d: stb $src1,@($slo16,$src2).  */
+/* stb-d: stb $src1,@($slo16,$src2) */
 
-CIA
-SEM_FN_NAME (m32rb,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_stb_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = * FLD (f_r1);
-    SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sth: sth $src1,@$src2.  */
+/* sth: sth $src1,@$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_sth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    HI opval = * FLD (f_r1);
-    SETMEMHI (current_cpu, * FLD (f_r2), opval);
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, * FLD (i_src2), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sth-d: sth $src1,@($slo16,$src2).  */
+/* sth-d: sth $src1,@($slo16,$src2) */
 
-CIA
-SEM_FN_NAME (m32rb,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_sth_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 4);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    HI opval = * FLD (f_r1);
-    SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), opval);
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* st-plus: st $src1,@+$src2.  */
+/* st-plus: st $src1,@+$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (f_r2), 4);
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
   {
-    SI opval = * FLD (f_r1);
+    SI opval = * FLD (i_src1);
     SETMEMSI (current_cpu, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
   {
     SI opval = tmp_new_src2;
-    * FLD (f_r2) = opval;
+    * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, "src2", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* st-minus: st $src1,@-$src2.  */
+/* st-minus: st $src1,@-$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (f_r2), 4);
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
   {
-    SI opval = * FLD (f_r1);
+    SI opval = * FLD (i_src1);
     SETMEMSI (current_cpu, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
   {
     SI opval = tmp_new_src2;
-    * FLD (f_r2) = opval;
+    * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, "src2", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* sub: sub $dr,$sr.  */
+/* sub: sub $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = SUBSI (* FLD (f_r1), * FLD (f_r2));
-    * FLD (f_r1) = opval;
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* subv: subv $dr,$sr.  */
+/* subv: subv $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addv.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
-  temp1 = SUBOFSI (* FLD (f_r1), * FLD (f_r2), 0);
+  BI temp1;SI temp0;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* subx: subx $dr,$sr.  */
+/* subx: subx $dr,$sr */
 
-CIA
-SEM_FN_NAME (m32rb,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_addx.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
-  UBI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
+  BI temp1;SI temp0;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
     SI opval = temp0;
-    * FLD (f_r1) = opval;
+    * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, "dr", 'x', opval);
   }
   {
-    UBI opval = temp1;
+    BI opval = temp1;
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, "condbit", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_mark_set_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  return vpc;
 #undef FLD
 }
 
-/* trap: trap $uimm4.  */
+/* trap: trap $uimm4 */
 
-CIA
-SEM_FN_NAME (m32rb,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_trap.f
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
-  int taken_p = 0;
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
   {
-    USI opval = ADDSI (CPU (h_pc), 4);
-    m32rb_h_cr_set (current_cpu, ((HOSTUINT) 6), opval);
+    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 6));
+    m32rbf_h_cr_set (current_cpu, ((UINT) 14), opval);
+    TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
     TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
   }
   {
-    USI opval = ANDSI (SLLSI (m32rb_h_cr_get (current_cpu, ((HOSTUINT) 0)), 8), 65408);
-    m32rb_h_cr_set (current_cpu, ((HOSTUINT) 0), opval);
-    TRACE_RESULT (current_cpu, "cr-0", 'x', opval);
+    UQI opval = CPU (h_bpsw);
+    CPU (h_bbpsw) = opval;
+    TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = m32rbf_h_psw_get (current_cpu);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
   }
   {
-    SI opval = m32r_trap (current_cpu, CPU (h_pc), FLD (f_uimm4));
-    BRANCH_NEW_PC (new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, opval));
-    taken_p = 1;
+    UQI opval = ANDQI (m32rbf_h_psw_get (current_cpu), 128);
+    m32rbf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, "pc", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_profile_cti_insn (current_cpu, abuf, taken_p);
-    }
-#endif
-
-  return new_pc;
+  SEM_BRANCH_FINI
+  return vpc;
 #undef FLD
 }
 
-/* unlock: unlock $src1,@$src2.  */
+/* unlock: unlock $src1,@$src2 */
 
-CIA
-SEM_FN_NAME (m32rb,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_PC
+SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_unlock.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  CIA new_pc = SEM_NEXT_PC (sem_arg, 2);
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 do {
 if (CPU (h_lock)) {
   {
-    SI opval = * FLD (f_r1);
-    SETMEMSI (current_cpu, * FLD (f_r2), opval);
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
+    written |= (1 << 3);
     TRACE_RESULT (current_cpu, "memory", 'x', opval);
   }
 }
   {
-    UBI opval = 0;
+    BI opval = 0;
     CPU (h_lock) = opval;
     TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
   }
 } while (0);
 
-  PROFILE_COUNT_INSN (current_cpu, 0, abuf->idesc->num);
-
-#if WITH_PROFILE_MODEL_P
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      m32rb_model_mark_get_h_gr (current_cpu, abuf);
-      m32rb_model_profile_insn (current_cpu, abuf);
-    }
-#endif
-
-  return new_pc;
+  abuf->written = written;
+  return vpc;
 #undef FLD
 }
 
-CIA
-SEM_FN_NAME (m32rb,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-  sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
-  return 0;
-}
-
-#endif /* WANT_CPU */

diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
new file mode 100644 (file)
index 0000000..6ee1808
--- /dev/null
+++ b/sim/m32r/semx-switch.c
@@ -0,0 +1,6274 @@
+/* Simulator instruction semantics for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+  /* The labels have the case they have because the enum of insn types
+     is all uppercase and in the non-stdc case the insn symbol is built
+     into the enum name.  */
+
+  static struct {
+    int index;
+    void *label;
+  } labels[] = {
+    { M32RXF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+    { M32RXF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+    { M32RXF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+    { M32RXF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+    { M32RXF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+    { M32RXF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+    { M32RXF_INSN_ADD, && case_sem_INSN_ADD },
+    { M32RXF_INSN_ADD3, && case_sem_INSN_ADD3 },
+    { M32RXF_INSN_AND, && case_sem_INSN_AND },
+    { M32RXF_INSN_AND3, && case_sem_INSN_AND3 },
+    { M32RXF_INSN_OR, && case_sem_INSN_OR },
+    { M32RXF_INSN_OR3, && case_sem_INSN_OR3 },
+    { M32RXF_INSN_XOR, && case_sem_INSN_XOR },
+    { M32RXF_INSN_XOR3, && case_sem_INSN_XOR3 },
+    { M32RXF_INSN_ADDI, && case_sem_INSN_ADDI },
+    { M32RXF_INSN_ADDV, && case_sem_INSN_ADDV },
+    { M32RXF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
+    { M32RXF_INSN_ADDX, && case_sem_INSN_ADDX },
+    { M32RXF_INSN_BC8, && case_sem_INSN_BC8 },
+    { M32RXF_INSN_BC24, && case_sem_INSN_BC24 },
+    { M32RXF_INSN_BEQ, && case_sem_INSN_BEQ },
+    { M32RXF_INSN_BEQZ, && case_sem_INSN_BEQZ },
+    { M32RXF_INSN_BGEZ, && case_sem_INSN_BGEZ },
+    { M32RXF_INSN_BGTZ, && case_sem_INSN_BGTZ },
+    { M32RXF_INSN_BLEZ, && case_sem_INSN_BLEZ },
+    { M32RXF_INSN_BLTZ, && case_sem_INSN_BLTZ },
+    { M32RXF_INSN_BNEZ, && case_sem_INSN_BNEZ },
+    { M32RXF_INSN_BL8, && case_sem_INSN_BL8 },
+    { M32RXF_INSN_BL24, && case_sem_INSN_BL24 },
+    { M32RXF_INSN_BCL8, && case_sem_INSN_BCL8 },
+    { M32RXF_INSN_BCL24, && case_sem_INSN_BCL24 },
+    { M32RXF_INSN_BNC8, && case_sem_INSN_BNC8 },
+    { M32RXF_INSN_BNC24, && case_sem_INSN_BNC24 },
+    { M32RXF_INSN_BNE, && case_sem_INSN_BNE },
+    { M32RXF_INSN_BRA8, && case_sem_INSN_BRA8 },
+    { M32RXF_INSN_BRA24, && case_sem_INSN_BRA24 },
+    { M32RXF_INSN_BNCL8, && case_sem_INSN_BNCL8 },
+    { M32RXF_INSN_BNCL24, && case_sem_INSN_BNCL24 },
+    { M32RXF_INSN_CMP, && case_sem_INSN_CMP },
+    { M32RXF_INSN_CMPI, && case_sem_INSN_CMPI },
+    { M32RXF_INSN_CMPU, && case_sem_INSN_CMPU },
+    { M32RXF_INSN_CMPUI, && case_sem_INSN_CMPUI },
+    { M32RXF_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
+    { M32RXF_INSN_CMPZ, && case_sem_INSN_CMPZ },
+    { M32RXF_INSN_DIV, && case_sem_INSN_DIV },
+    { M32RXF_INSN_DIVU, && case_sem_INSN_DIVU },
+    { M32RXF_INSN_REM, && case_sem_INSN_REM },
+    { M32RXF_INSN_REMU, && case_sem_INSN_REMU },
+    { M32RXF_INSN_DIVH, && case_sem_INSN_DIVH },
+    { M32RXF_INSN_JC, && case_sem_INSN_JC },
+    { M32RXF_INSN_JNC, && case_sem_INSN_JNC },
+    { M32RXF_INSN_JL, && case_sem_INSN_JL },
+    { M32RXF_INSN_JMP, && case_sem_INSN_JMP },
+    { M32RXF_INSN_LD, && case_sem_INSN_LD },
+    { M32RXF_INSN_LD_D, && case_sem_INSN_LD_D },
+    { M32RXF_INSN_LDB, && case_sem_INSN_LDB },
+    { M32RXF_INSN_LDB_D, && case_sem_INSN_LDB_D },
+    { M32RXF_INSN_LDH, && case_sem_INSN_LDH },
+    { M32RXF_INSN_LDH_D, && case_sem_INSN_LDH_D },
+    { M32RXF_INSN_LDUB, && case_sem_INSN_LDUB },
+    { M32RXF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
+    { M32RXF_INSN_LDUH, && case_sem_INSN_LDUH },
+    { M32RXF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
+    { M32RXF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
+    { M32RXF_INSN_LD24, && case_sem_INSN_LD24 },
+    { M32RXF_INSN_LDI8, && case_sem_INSN_LDI8 },
+    { M32RXF_INSN_LDI16, && case_sem_INSN_LDI16 },
+    { M32RXF_INSN_LOCK, && case_sem_INSN_LOCK },
+    { M32RXF_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
+    { M32RXF_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
+    { M32RXF_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
+    { M32RXF_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
+    { M32RXF_INSN_MUL, && case_sem_INSN_MUL },
+    { M32RXF_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
+    { M32RXF_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
+    { M32RXF_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
+    { M32RXF_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
+    { M32RXF_INSN_MV, && case_sem_INSN_MV },
+    { M32RXF_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
+    { M32RXF_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
+    { M32RXF_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
+    { M32RXF_INSN_MVFC, && case_sem_INSN_MVFC },
+    { M32RXF_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
+    { M32RXF_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
+    { M32RXF_INSN_MVTC, && case_sem_INSN_MVTC },
+    { M32RXF_INSN_NEG, && case_sem_INSN_NEG },
+    { M32RXF_INSN_NOP, && case_sem_INSN_NOP },
+    { M32RXF_INSN_NOT, && case_sem_INSN_NOT },
+    { M32RXF_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
+    { M32RXF_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
+    { M32RXF_INSN_RTE, && case_sem_INSN_RTE },
+    { M32RXF_INSN_SETH, && case_sem_INSN_SETH },
+    { M32RXF_INSN_SLL, && case_sem_INSN_SLL },
+    { M32RXF_INSN_SLL3, && case_sem_INSN_SLL3 },
+    { M32RXF_INSN_SLLI, && case_sem_INSN_SLLI },
+    { M32RXF_INSN_SRA, && case_sem_INSN_SRA },
+    { M32RXF_INSN_SRA3, && case_sem_INSN_SRA3 },
+    { M32RXF_INSN_SRAI, && case_sem_INSN_SRAI },
+    { M32RXF_INSN_SRL, && case_sem_INSN_SRL },
+    { M32RXF_INSN_SRL3, && case_sem_INSN_SRL3 },
+    { M32RXF_INSN_SRLI, && case_sem_INSN_SRLI },
+    { M32RXF_INSN_ST, && case_sem_INSN_ST },
+    { M32RXF_INSN_ST_D, && case_sem_INSN_ST_D },
+    { M32RXF_INSN_STB, && case_sem_INSN_STB },
+    { M32RXF_INSN_STB_D, && case_sem_INSN_STB_D },
+    { M32RXF_INSN_STH, && case_sem_INSN_STH },
+    { M32RXF_INSN_STH_D, && case_sem_INSN_STH_D },
+    { M32RXF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
+    { M32RXF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
+    { M32RXF_INSN_SUB, && case_sem_INSN_SUB },
+    { M32RXF_INSN_SUBV, && case_sem_INSN_SUBV },
+    { M32RXF_INSN_SUBX, && case_sem_INSN_SUBX },
+    { M32RXF_INSN_TRAP, && case_sem_INSN_TRAP },
+    { M32RXF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
+    { M32RXF_INSN_SATB, && case_sem_INSN_SATB },
+    { M32RXF_INSN_SATH, && case_sem_INSN_SATH },
+    { M32RXF_INSN_SAT, && case_sem_INSN_SAT },
+    { M32RXF_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
+    { M32RXF_INSN_SADD, && case_sem_INSN_SADD },
+    { M32RXF_INSN_MACWU1, && case_sem_INSN_MACWU1 },
+    { M32RXF_INSN_MSBLO, && case_sem_INSN_MSBLO },
+    { M32RXF_INSN_MULWU1, && case_sem_INSN_MULWU1 },
+    { M32RXF_INSN_MACLH1, && case_sem_INSN_MACLH1 },
+    { M32RXF_INSN_SC, && case_sem_INSN_SC },
+    { M32RXF_INSN_SNC, && case_sem_INSN_SNC },
+    { M32RXF_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
+    { M32RXF_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
+    { M32RXF_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
+    { M32RXF_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
+    { M32RXF_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
+    { M32RXF_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
+    { M32RXF_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
+    { M32RXF_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
+    { M32RXF_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
+    { M32RXF_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
+    { M32RXF_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
+    { M32RXF_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
+    { M32RXF_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
+    { M32RXF_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
+    { M32RXF_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
+    { M32RXF_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
+    { M32RXF_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
+    { M32RXF_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
+    { M32RXF_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
+    { M32RXF_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
+    { M32RXF_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
+    { M32RXF_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
+    { M32RXF_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
+    { M32RXF_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
+    { M32RXF_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
+    { M32RXF_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
+    { M32RXF_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
+    { M32RXF_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
+    { M32RXF_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
+    { M32RXF_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
+    { M32RXF_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
+    { M32RXF_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
+    { M32RXF_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
+    { M32RXF_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
+    { M32RXF_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
+    { M32RXF_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
+    { M32RXF_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
+    { M32RXF_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
+    { M32RXF_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
+    { M32RXF_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
+    { M32RXF_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
+    { M32RXF_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
+    { M32RXF_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
+    { M32RXF_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
+    { M32RXF_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
+    { M32RXF_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
+    { M32RXF_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
+    { M32RXF_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
+    { M32RXF_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
+    { M32RXF_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
+    { M32RXF_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
+    { M32RXF_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
+    { M32RXF_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
+    { M32RXF_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
+    { M32RXF_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
+    { M32RXF_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
+    { M32RXF_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
+    { M32RXF_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
+    { M32RXF_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
+    { M32RXF_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
+    { M32RXF_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
+    { M32RXF_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
+    { M32RXF_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
+    { M32RXF_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
+    { M32RXF_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
+    { M32RXF_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
+    { M32RXF_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
+    { M32RXF_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
+    { M32RXF_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
+    { M32RXF_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
+    { M32RXF_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
+    { M32RXF_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
+    { M32RXF_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
+    { M32RXF_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
+    { M32RXF_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
+    { M32RXF_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
+    { M32RXF_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
+    { M32RXF_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
+    { M32RXF_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
+    { M32RXF_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
+    { M32RXF_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
+    { M32RXF_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
+    { M32RXF_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
+    { M32RXF_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
+    { M32RXF_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
+    { M32RXF_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
+    { M32RXF_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
+    { M32RXF_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
+    { M32RXF_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
+    { M32RXF_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
+    { M32RXF_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
+    { M32RXF_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
+    { M32RXF_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
+    { M32RXF_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
+    { M32RXF_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
+    { M32RXF_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
+    { M32RXF_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
+    { M32RXF_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
+    { M32RXF_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
+    { M32RXF_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
+    { M32RXF_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
+    { M32RXF_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
+    { M32RXF_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
+    { M32RXF_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
+    { M32RXF_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
+    { M32RXF_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
+    { M32RXF_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
+    { M32RXF_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
+    { M32RXF_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
+    { M32RXF_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
+    { M32RXF_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
+    { M32RXF_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
+    { M32RXF_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
+    { M32RXF_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
+    { M32RXF_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
+    { M32RXF_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
+    { M32RXF_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
+    { M32RXF_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
+    { M32RXF_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
+    { M32RXF_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
+    { M32RXF_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
+    { M32RXF_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
+    { M32RXF_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
+    { M32RXF_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
+    { M32RXF_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
+    { M32RXF_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
+    { M32RXF_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
+    { M32RXF_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
+    { M32RXF_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
+    { M32RXF_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
+    { M32RXF_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
+    { M32RXF_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
+    { M32RXF_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
+    { M32RXF_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
+    { M32RXF_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
+    { M32RXF_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
+    { M32RXF_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
+    { M32RXF_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
+    { M32RXF_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
+    { M32RXF_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
+    { M32RXF_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
+    { M32RXF_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
+    { M32RXF_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
+    { M32RXF_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
+    { M32RXF_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
+    { M32RXF_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
+    { M32RXF_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
+    { M32RXF_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
+    { M32RXF_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
+    { M32RXF_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
+    { M32RXF_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
+    { M32RXF_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
+    { 0, 0 }
+  };
+  int i;
+
+  for (i = 0; labels[i].label != 0; ++i)
+#if FAST_P
+    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+   off frills like tracing and profiling.  */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+   that can cause it to be optimized out.  Another way would be to emit
+   special handlers into the instruction "stream".  */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop.  */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+    {
+
+  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE
+    /* Update the recorded pc in the cpu state struct.  */
+    SET_H_PC (pc);
+#endif
+    sim_engine_invalid_insn (current_cpu, pc);
+    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
+    /* NOTREACHED */
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    m32rxf_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    m32rxf_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
+                              pbb_br_npc_ptr, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
+                              CPU_PBB_BR_NPC_PTR (current_cpu),
+                              CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+    vpc = m32rxf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB
+#ifdef DEFINE_SWITCH
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = m32rxf_pbb_begin (current_cpu, FAST_P);
+#else
+    vpc = m32rxf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD) : /* add $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND) : /* and $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_and3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR) : /* or $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_or3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_and3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addv3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
+  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addx.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src1), * FLD (i_src2))) {
+  {
+    USI opval = FLD (f_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+do {
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src2), 0);
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV) : /* div $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REM) : /* rem $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_div.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JC) : /* jc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JNC) : /* jnc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JL) : /* jl $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  USI temp1;SI temp0;
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
+  {
+    SI opval = temp0;
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = temp1;
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JMP) : /* jmp $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI temp1;SI temp0;
+  temp0 = GETMEMSI (current_cpu, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    SI opval = temp1;
+    * FLD (i_sr) = opval;
+    TRACE_RESULT (current_cpu, "sr", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld24.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_uimm24);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_simm8);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi16.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_simm16);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lock.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = 1;
+    CPU (h_lock) = opval;
+    TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+    m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MV) : /* mv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_sr);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 32));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = m32rxf_h_cr_get (current_cpu, FLD (f_r2));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    m32rxf_h_accums_set (current_cpu, FLD (f_accs), opval);
+    TRACE_RESULT (current_cpu, "accs", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    m32rxf_h_accums_set (current_cpu, FLD (f_accs), opval);
+    TRACE_RESULT (current_cpu, "accs", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_sr);
+    m32rxf_h_cr_set (current_cpu, FLD (f_r1), opval);
+    TRACE_RESULT (current_cpu, "dcr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = NEGSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_nop.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT) : /* not $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = INVSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+    m32rxf_h_accums_set (current_cpu, FLD (f_accd), opval);
+    TRACE_RESULT (current_cpu, "accd", 'D', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+    m32rxf_h_accums_set (current_cpu, FLD (f_accd), opval);
+    TRACE_RESULT (current_cpu, "accd", 'D', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RTE) : /* rte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = ANDSI (m32rxf_h_cr_get (current_cpu, ((UINT) 6)), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+  {
+    USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 14));
+    m32rxf_h_cr_set (current_cpu, ((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    m32rxf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bbpsw);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_seth.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_hi16), 16);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sll3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sll3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sll3.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stb_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sth.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sth_d.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_new_src2;
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, "src2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_new_src2;
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, "src2", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addx.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 6));
+    m32rxf_h_cr_set (current_cpu, ((UINT) 14), opval);
+    TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    m32rxf_h_cr_set (current_cpu, ((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    CPU (h_bbpsw) = opval;
+    TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = m32rxf_h_psw_get (current_cpu);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (m32rxf_h_psw_get (current_cpu), 128);
+    m32rxf_h_psw_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_unlock.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_lock)) {
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, * FLD (i_src2), opval);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+}
+  {
+    BI opval = 0;
+    CPU (h_lock) = opval;
+    TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SATB) : /* satb $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_satb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SATH) : /* sath $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_satb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SAT) : /* sat $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sat.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SADD) : /* sadd */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sadd.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (SRADI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), 16), m32rxf_h_accums_get (current_cpu, ((UINT) 0)));
+    m32rxf_h_accums_set (current_cpu, ((UINT) 0), opval);
+    TRACE_RESULT (current_cpu, "accums-0", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_macwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+    m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_msblo.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (SUBDI (m32rxf_h_accum_get (current_cpu), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+    m32rxf_h_accum_set (current_cpu, opval);
+    TRACE_RESULT (current_cpu, "accum", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+    m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_macwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+    m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SC) : /* sc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+SEM_SKIP_INSN (current_cpu, 1);
+}
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SNC) : /* snc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+SEM_SKIP_INSN (current_cpu, 1);
+}
+
+  SEM_BRANCH_FINI
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addi.f
+#define OPRND(f) par_exec->operands.fmt_addi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_addi.f
+#define OPRND(f) par_exec->operands.fmt_addi.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addv.f
+#define OPRND(f) par_exec->operands.fmt_addv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_addv.f
+#define OPRND(f) par_exec->operands.fmt_addv.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addx.f
+#define OPRND(f) par_exec->operands.fmt_addx.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_addx.f
+#define OPRND(f) par_exec->operands.fmt_addx.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define OPRND(f) par_exec->operands.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define OPRND(f) par_exec->operands.fmt_bc8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define OPRND(f) par_exec->operands.fmt_bl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_14) = opval;
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define OPRND(f) par_exec->operands.fmt_bl8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define OPRND(f) par_exec->operands.fmt_bcl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_14) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define OPRND(f) par_exec->operands.fmt_bcl8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 3))
+    {
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+    }
+  if (written & (1 << 4))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define OPRND(f) par_exec->operands.fmt_bc8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define OPRND(f) par_exec->operands.fmt_bc8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define OPRND(f) par_exec->operands.fmt_bra8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define OPRND(f) par_exec->operands.fmt_bra8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define OPRND(f) par_exec->operands.fmt_bcl8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+do {
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_14) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = FLD (f_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
+#define OPRND(f) par_exec->operands.fmt_bcl8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 3))
+    {
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+    }
+  if (written & (1 << 4))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_cmp.f
+#define OPRND(f) par_exec->operands.fmt_cmp.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpz.f
+#define OPRND(f) par_exec->operands.fmt_cmpz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src2), 0);
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_cmpz.f
+#define OPRND(f) par_exec->operands.fmt_cmpz.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JC) : /* jc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define OPRND(f) par_exec->operands.fmt_jc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_JC) : /* jc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define OPRND(f) par_exec->operands.fmt_jc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define OPRND(f) par_exec->operands.fmt_jc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
+#define OPRND(f) par_exec->operands.fmt_jc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JL) : /* jl $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define OPRND(f) par_exec->operands.fmt_jl.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  USI temp1;SI temp0;
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
+  {
+    SI opval = temp0;
+    OPRND (h_gr_14) = opval;
+    TRACE_RESULT (current_cpu, "gr-14", 'x', opval);
+  }
+  {
+    USI opval = temp1;
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_JL) : /* jl $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define OPRND(f) par_exec->operands.fmt_jl.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define OPRND(f) par_exec->operands.fmt_jmp.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define OPRND(f) par_exec->operands.fmt_jmp.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld.f
+#define OPRND(f) par_exec->operands.fmt_ld.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ld.f
+#define OPRND(f) par_exec->operands.fmt_ld.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb.f
+#define OPRND(f) par_exec->operands.fmt_ldb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ldb.f
+#define OPRND(f) par_exec->operands.fmt_ldb.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh.f
+#define OPRND(f) par_exec->operands.fmt_ldh.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ldh.f
+#define OPRND(f) par_exec->operands.fmt_ldh.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldb.f
+#define OPRND(f) par_exec->operands.fmt_ldb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ldb.f
+#define OPRND(f) par_exec->operands.fmt_ldb.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldh.f
+#define OPRND(f) par_exec->operands.fmt_ldh.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ldh.f
+#define OPRND(f) par_exec->operands.fmt_ldh.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define OPRND(f) par_exec->operands.fmt_ld_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI temp1;SI temp0;
+  temp0 = GETMEMSI (current_cpu, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    SI opval = temp1;
+    OPRND (sr) = opval;
+    TRACE_RESULT (current_cpu, "sr", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define OPRND(f) par_exec->operands.fmt_ld_plus.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  * FLD (i_sr) = OPRND (sr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_ldi8.f
+#define OPRND(f) par_exec->operands.fmt_ldi8.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_simm8);
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_ldi8.f
+#define OPRND(f) par_exec->operands.fmt_ldi8.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_lock.f
+#define OPRND(f) par_exec->operands.fmt_lock.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    BI opval = 1;
+    OPRND (h_lock_0) = opval;
+    TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_lock.f
+#define OPRND(f) par_exec->operands.fmt_lock.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_lock) = OPRND (h_lock_0);
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_machi_a.f
+#define OPRND(f) par_exec->operands.fmt_machi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, "acc", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mulhi_a.f
+#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_sr);
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 32));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 16));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvfc.f
+#define OPRND(f) par_exec->operands.fmt_mvfc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = m32rxf_h_cr_get (current_cpu, FLD (f_r2));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvfc.f
+#define OPRND(f) par_exec->operands.fmt_mvfc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    OPRND (accs) = opval;
+    TRACE_RESULT (current_cpu, "accs", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    OPRND (accs) = opval;
+    TRACE_RESULT (current_cpu, "accs", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mvtc.f
+#define OPRND(f) par_exec->operands.fmt_mvtc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_sr);
+    OPRND (dcr) = opval;
+    TRACE_RESULT (current_cpu, "dcr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mvtc.f
+#define OPRND(f) par_exec->operands.fmt_mvtc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_cr_set (current_cpu, FLD (f_r1), OPRND (dcr));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = NEGSI (* FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_nop.f
+#define OPRND(f) par_exec->operands.fmt_nop.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_nop.f
+#define OPRND(f) par_exec->operands.fmt_nop.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = INVSI (* FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mv.f
+#define OPRND(f) par_exec->operands.fmt_mv.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+    OPRND (accd) = opval;
+    TRACE_RESULT (current_cpu, "accd", 'D', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+    OPRND (accd) = opval;
+    TRACE_RESULT (current_cpu, "accd", 'D', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RTE) : /* rte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define OPRND(f) par_exec->operands.fmt_rte.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = ANDSI (m32rxf_h_cr_get (current_cpu, ((UINT) 6)), -4);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+  {
+    USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 14));
+    OPRND (h_cr_6) = opval;
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    OPRND (h_psw_0) = opval;
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bbpsw);
+    OPRND (h_bpsw_0) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_RTE) : /* rte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define OPRND(f) par_exec->operands.fmt_rte.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+  m32rxf_h_cr_set (current_cpu, ((UINT) 6), OPRND (h_cr_6));
+  m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0));
+  CPU (h_bpsw) = OPRND (h_bpsw_0);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_slli.f
+#define OPRND(f) par_exec->operands.fmt_slli.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st.f
+#define OPRND(f) par_exec->operands.fmt_st.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_src2) = opval;
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_st.f
+#define OPRND(f) par_exec->operands.fmt_st.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_stb.f
+#define OPRND(f) par_exec->operands.fmt_stb.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_src1);
+    OPRND (h_memory_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_src2) = opval;
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_stb.f
+#define OPRND(f) par_exec->operands.fmt_stb.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMQI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sth.f
+#define OPRND(f) par_exec->operands.fmt_sth.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_src1);
+    OPRND (h_memory_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_src2) = opval;
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_sth.f
+#define OPRND(f) par_exec->operands.fmt_sth.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMHI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_plus.f
+#define OPRND(f) par_exec->operands.fmt_st_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_new_src2;
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_new_src2) = opval;
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, "src2", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_st_plus.f
+#define OPRND(f) par_exec->operands.fmt_st_plus.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_st_plus.f
+#define OPRND(f) par_exec->operands.fmt_st_plus.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  SI tmp_new_src2;
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_new_src2) = opval;
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, "src2", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_st_plus.f
+#define OPRND(f) par_exec->operands.fmt_st_plus.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_add.f
+#define OPRND(f) par_exec->operands.fmt_add.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addv.f
+#define OPRND(f) par_exec->operands.fmt_addv.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_addv.f
+#define OPRND(f) par_exec->operands.fmt_addv.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_addx.f
+#define OPRND(f) par_exec->operands.fmt_addx.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, "dr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_addx.f
+#define OPRND(f) par_exec->operands.fmt_addx.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define OPRND(f) par_exec->operands.fmt_trap.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+  {
+    USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 6));
+    OPRND (h_cr_14) = opval;
+    TRACE_RESULT (current_cpu, "cr-14", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    OPRND (h_cr_6) = opval;
+    TRACE_RESULT (current_cpu, "cr-6", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    OPRND (h_bbpsw_0) = opval;
+    TRACE_RESULT (current_cpu, "bbpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = m32rxf_h_psw_get (current_cpu);
+    OPRND (h_bpsw_0) = opval;
+    TRACE_RESULT (current_cpu, "bpsw-0", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (m32rxf_h_psw_get (current_cpu), 128);
+    OPRND (h_psw_0) = opval;
+    TRACE_RESULT (current_cpu, "psw-0", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, "pc", 'x', opval);
+  }
+} while (0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define OPRND(f) par_exec->operands.fmt_trap.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_cr_set (current_cpu, ((UINT) 14), OPRND (h_cr_14));
+  m32rxf_h_cr_set (current_cpu, ((UINT) 6), OPRND (h_cr_6));
+  CPU (h_bbpsw) = OPRND (h_bbpsw_0);
+  CPU (h_bpsw) = OPRND (h_bpsw_0);
+  m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0));
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_unlock.f
+#define OPRND(f) par_exec->operands.fmt_unlock.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+do {
+if (CPU (h_lock)) {
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_src2) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, "memory", 'x', opval);
+  }
+}
+  {
+    BI opval = 0;
+    OPRND (h_lock_0) = opval;
+    TRACE_RESULT (current_cpu, "lock-0", 'x', opval);
+  }
+} while (0);
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_unlock.f
+#define OPRND(f) par_exec->operands.fmt_unlock.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 3))
+    {
+      SETMEMSI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+    }
+  CPU (h_lock) = OPRND (h_lock_0);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_cmpz.f
+#define OPRND(f) par_exec->operands.fmt_cmpz.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, "condbit", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_cmpz.f
+#define OPRND(f) par_exec->operands.fmt_cmpz.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SADD) : /* sadd */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_sadd.f
+#define OPRND(f) par_exec->operands.fmt_sadd.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (SRADI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), 16), m32rxf_h_accums_get (current_cpu, ((UINT) 0)));
+    OPRND (h_accums_0) = opval;
+    TRACE_RESULT (current_cpu, "accums-0", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SADD) : /* sadd */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_sadd.f
+#define OPRND(f) par_exec->operands.fmt_sadd.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, ((UINT) 0), OPRND (h_accums_0));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_macwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+    OPRND (h_accums_1) = opval;
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_macwu1.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_msblo.f
+#define OPRND(f) par_exec->operands.fmt_msblo.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (SUBDI (m32rxf_h_accum_get (current_cpu), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+    OPRND (accum) = opval;
+    TRACE_RESULT (current_cpu, "accum", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_msblo.f
+#define OPRND(f) par_exec->operands.fmt_msblo.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accum_set (current_cpu, OPRND (accum));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulwu1.f
+#define OPRND(f) par_exec->operands.fmt_mulwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+    OPRND (h_accums_1) = opval;
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_mulwu1.f
+#define OPRND(f) par_exec->operands.fmt_mulwu1.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_macwu1.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+    OPRND (h_accums_1) = opval;
+    TRACE_RESULT (current_cpu, "accums-1", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_macwu1.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SC) : /* sc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define OPRND(f) par_exec->operands.fmt_sc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+SEM_SKIP_INSN (current_cpu, 1);
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SC) : /* sc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define OPRND(f) par_exec->operands.fmt_sc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SNC) : /* snc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define OPRND(f) par_exec->operands.fmt_sc.f
+  int UNUSED written = 0;
+  PCADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+SEM_SKIP_INSN (current_cpu, 1);
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_WRITE_SNC) : /* snc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
+#define OPRND(f) par_exec->operands.fmt_sc.f
+  int UNUSED written = abuf->written;
+  PCADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+  SEM_BRANCH_FINI
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+
+    }
+  ENDSWITCH (sem) /* End of semantic switch.  */
+
+  /* At this point `vpc' contains the next insn to execute.  */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */